| blob | 3bf17abc7965ec6c490d12a1f0399990cf9574e6 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32 -asm-show-inst |\
3 ; RUN: FileCheck %s -check-prefixes=M32
4 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -asm-show-inst |\
5 ; RUN: FileCheck %s -check-prefixes=M32
6 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst |\
7 ; RUN: FileCheck %s -check-prefixes=M32R2-FP64
8 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+soft-float -asm-show-inst |\
9 ; RUN: FileCheck %s -check-prefixes=M32R2-SF
10 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r3 -asm-show-inst |\
11 ; RUN: FileCheck %s -check-prefixes=M32R3R5
12 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r5 -asm-show-inst |\
13 ; RUN: FileCheck %s -check-prefixes=M32R3R5
14 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -asm-show-inst |\
15 ; RUN: FileCheck %s -check-prefixes=M32R6
16 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips3 -asm-show-inst |\
17 ; RUN: FileCheck %s -check-prefixes=M64
18 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64 -asm-show-inst |\
19 ; RUN: FileCheck %s -check-prefixes=M64
20 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r2 -asm-show-inst |\
21 ; RUN: FileCheck %s -check-prefixes=M64
22 ; RUN: llc < %s -mtriple=mips64-linux-gnu -mcpu=mips64r6 -asm-show-inst |\
23 ; RUN: FileCheck %s -check-prefixes=M64R6
24 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips -asm-show-inst |\
25 ; RUN: FileCheck %s -check-prefixes=MMR2-FP32
26 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,fp64 -asm-show-inst |\
27 ; RUN: FileCheck %s -check-prefixes=MMR2-FP64
28 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r2 -mattr=+micromips,soft-float -asm-show-inst |\
29 ; RUN: FileCheck %s -check-prefixes=MMR2-SF
30 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips -asm-show-inst |\
31 ; RUN: FileCheck %s -check-prefixes=MMR6
32 ; RUN: llc < %s -mtriple=mips-linux-gnu -mcpu=mips32r6 -mattr=+micromips,soft-float -asm-show-inst |\
33 ; RUN: FileCheck %s -check-prefixes=MMR6-SF
35 ; Test that fptosi can be matched for MIPS targets for various FPU
36 ; configurations
38 define i32 @test1(float %t) {
39 ; M32-LABEL: test1:
40 ; M32: # %bb.0: # %entry
41 ; M32-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
42 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
43 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
44 ; M32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
45 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
46 ; M32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
47 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
48 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
49 ;
50 ; M32R2-FP64-LABEL: test1:
51 ; M32R2-FP64: # %bb.0: # %entry
52 ; M32R2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
53 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
54 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
55 ; M32R2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
56 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
57 ; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
58 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
59 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
60 ;
61 ; M32R2-SF-LABEL: test1:
62 ; M32R2-SF: # %bb.0: # %entry
63 ; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
64 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
65 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
66 ; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
67 ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
68 ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
69 ; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} SW
70 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
71 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
72 ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
73 ; M32R2-SF-NEXT: .cfi_offset 31, -4
74 ; M32R2-SF-NEXT: jal __fixsfsi # <MCInst #{{[0-9]+}} JAL
75 ; M32R2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
76 ; M32R2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
77 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
78 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
79 ; M32R2-SF-NEXT: # <MCOperand Imm:0>>
80 ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
81 ; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} LW
82 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
83 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
84 ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
85 ; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
86 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
87 ; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
88 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
89 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
90 ; M32R2-SF-NEXT: # <MCOperand Imm:24>>
91 ;
92 ; M32R3R5-LABEL: test1:
93 ; M32R3R5: # %bb.0: # %entry
94 ; M32R3R5-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
95 ; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
96 ; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
97 ; M32R3R5-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
98 ; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
99 ; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
100 ; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
101 ; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
102 ;
103 ; M32R6-LABEL: test1:
104 ; M32R6: # %bb.0: # %entry
105 ; M32R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
106 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
107 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
108 ; M32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
109 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
110 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
111 ; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
112 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
113 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
114 ;
115 ; M64-LABEL: test1:
116 ; M64: # %bb.0: # %entry
117 ; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
118 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
119 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
120 ; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
121 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
122 ; M64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
123 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
124 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
125 ;
126 ; M64R6-LABEL: test1:
127 ; M64R6: # %bb.0: # %entry
128 ; M64R6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
129 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
130 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
131 ; M64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
132 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
133 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
134 ; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
135 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
136 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
137 ;
138 ; MMR2-FP32-LABEL: test1:
139 ; MMR2-FP32: # %bb.0: # %entry
140 ; MMR2-FP32-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
141 ; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
142 ; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
143 ; MMR2-FP32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
144 ; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
145 ; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
146 ; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
147 ; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
148 ;
149 ; MMR2-FP64-LABEL: test1:
150 ; MMR2-FP64: # %bb.0: # %entry
151 ; MMR2-FP64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MM
152 ; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
153 ; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
154 ; MMR2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
155 ; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
156 ; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
157 ; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
158 ; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
159 ;
160 ; MMR2-SF-LABEL: test1:
161 ; MMR2-SF: # %bb.0: # %entry
162 ; MMR2-SF-NEXT: addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
163 ; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
164 ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
165 ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
166 ; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} SWSP_MM
167 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
168 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
169 ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
170 ; MMR2-SF-NEXT: .cfi_offset 31, -4
171 ; MMR2-SF-NEXT: jal __fixsfsi # <MCInst #{{[0-9]+}} JAL_MM
172 ; MMR2-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
173 ; MMR2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
174 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
175 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
176 ; MMR2-SF-NEXT: # <MCOperand Imm:0>>
177 ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
178 ; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} LWSP_MM
179 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
180 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
181 ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
182 ; MMR2-SF-NEXT: addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
183 ; MMR2-SF-NEXT: # <MCOperand Imm:24>>
184 ; MMR2-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
185 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
186 ;
187 ; MMR6-LABEL: test1:
188 ; MMR6: # %bb.0: # %entry
189 ; MMR6-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S_MMR6
190 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
191 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
192 ; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
193 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
194 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
195 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
196 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
197 ;
198 ; MMR6-SF-LABEL: test1:
199 ; MMR6-SF: # %bb.0: # %entry
200 ; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
201 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
202 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
203 ; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
204 ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
205 ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
206 ; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} SW
207 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
208 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
209 ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
210 ; MMR6-SF-NEXT: .cfi_offset 31, -4
211 ; MMR6-SF-NEXT: balc __fixsfsi # <MCInst #{{[0-9]+}} BALC_MMR6
212 ; MMR6-SF-NEXT: # <MCOperand Expr:(__fixsfsi)>>
213 ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
214 ; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
215 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
216 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
217 ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
218 ; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
219 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
220 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
221 ; MMR6-SF-NEXT: # <MCOperand Imm:24>>
222 ; MMR6-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
223 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
224 entry:
225 %conv = fptosi float %t to i32
226 ret i32 %conv
227 }
229 define i32 @test2(double %t) {
230 ; M32-LABEL: test2:
231 ; M32: # %bb.0: # %entry
232 ; M32-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
233 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
234 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
235 ; M32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
236 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
237 ; M32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
238 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
239 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
240 ;
241 ; M32R2-FP64-LABEL: test2:
242 ; M32R2-FP64: # %bb.0: # %entry
243 ; M32R2-FP64-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
244 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
245 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
246 ; M32R2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
247 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
248 ; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
249 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
250 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
251 ;
252 ; M32R2-SF-LABEL: test2:
253 ; M32R2-SF: # %bb.0: # %entry
254 ; M32R2-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
255 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
256 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
257 ; M32R2-SF-NEXT: # <MCOperand Imm:-24>>
258 ; M32R2-SF-NEXT: .cfi_def_cfa_offset 24
259 ; M32R2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
260 ; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} SW
261 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
262 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
263 ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
264 ; M32R2-SF-NEXT: .cfi_offset 31, -4
265 ; M32R2-SF-NEXT: jal __fixdfsi # <MCInst #{{[0-9]+}} JAL
266 ; M32R2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
267 ; M32R2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
268 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
269 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
270 ; M32R2-SF-NEXT: # <MCOperand Imm:0>>
271 ; M32R2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
272 ; M32R2-SF-NEXT: # <MCInst #{{[0-9]+}} LW
273 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
274 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
275 ; M32R2-SF-NEXT: # <MCOperand Imm:20>>
276 ; M32R2-SF-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
277 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
278 ; M32R2-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
279 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
280 ; M32R2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
281 ; M32R2-SF-NEXT: # <MCOperand Imm:24>>
282 ;
283 ; M32R3R5-LABEL: test2:
284 ; M32R3R5: # %bb.0: # %entry
285 ; M32R3R5-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D32
286 ; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
287 ; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
288 ; M32R3R5-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
289 ; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
290 ; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
291 ; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>
292 ; M32R3R5-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
293 ;
294 ; M32R6-LABEL: test2:
295 ; M32R6: # %bb.0: # %entry
296 ; M32R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
297 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
298 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
299 ; M32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
300 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
301 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
302 ; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
303 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
304 ; M32R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
305 ;
306 ; M64-LABEL: test2:
307 ; M64: # %bb.0: # %entry
308 ; M64-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
309 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
310 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
311 ; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
312 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
313 ; M64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
314 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
315 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
316 ;
317 ; M64R6-LABEL: test2:
318 ; M64R6: # %bb.0: # %entry
319 ; M64R6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D64
320 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
321 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
322 ; M64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
323 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
324 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
325 ; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
326 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
327 ; M64R6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
328 ;
329 ; MMR2-FP32-LABEL: test2:
330 ; MMR2-FP32: # %bb.0: # %entry
331 ; MMR2-FP32-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_MM
332 ; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
333 ; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
334 ; MMR2-FP32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
335 ; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
336 ; MMR2-FP32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
337 ; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
338 ; MMR2-FP32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
339 ;
340 ; MMR2-FP64-LABEL: test2:
341 ; MMR2-FP64: # %bb.0: # %entry
342 ; MMR2-FP64-NEXT: cvt.w.d $f0, $f12 # <MCInst #{{[0-9]+}} CVT_W_D64_MM
343 ; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
344 ; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
345 ; MMR2-FP64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
346 ; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
347 ; MMR2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
348 ; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
349 ; MMR2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
350 ;
351 ; MMR2-SF-LABEL: test2:
352 ; MMR2-SF: # %bb.0: # %entry
353 ; MMR2-SF-NEXT: addiusp -24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
354 ; MMR2-SF-NEXT: # <MCOperand Imm:-24>>
355 ; MMR2-SF-NEXT: .cfi_def_cfa_offset 24
356 ; MMR2-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
357 ; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} SWSP_MM
358 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
359 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
360 ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
361 ; MMR2-SF-NEXT: .cfi_offset 31, -4
362 ; MMR2-SF-NEXT: jal __fixdfsi # <MCInst #{{[0-9]+}} JAL_MM
363 ; MMR2-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
364 ; MMR2-SF-NEXT: nop # <MCInst #{{[0-9]+}} SLL
365 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
366 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
367 ; MMR2-SF-NEXT: # <MCOperand Imm:0>>
368 ; MMR2-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
369 ; MMR2-SF-NEXT: # <MCInst #{{[0-9]+}} LWSP_MM
370 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
371 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
372 ; MMR2-SF-NEXT: # <MCOperand Imm:20>>
373 ; MMR2-SF-NEXT: addiusp 24 # <MCInst #{{[0-9]+}} ADDIUSP_MM
374 ; MMR2-SF-NEXT: # <MCOperand Imm:24>>
375 ; MMR2-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
376 ; MMR2-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
377 ;
378 ; MMR6-LABEL: test2:
379 ; MMR6: # %bb.0: # %entry
380 ; MMR6-NEXT: trunc.w.d $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_D_MMR6
381 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
382 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
383 ; MMR6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1_MM
384 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>
385 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
386 ; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
387 ; MMR6-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
388 ;
389 ; MMR6-SF-LABEL: test2:
390 ; MMR6-SF: # %bb.0: # %entry
391 ; MMR6-SF-NEXT: addiu $sp, $sp, -24 # <MCInst #{{[0-9]+}} ADDiu
392 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
393 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
394 ; MMR6-SF-NEXT: # <MCOperand Imm:-24>>
395 ; MMR6-SF-NEXT: .cfi_def_cfa_offset 24
396 ; MMR6-SF-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
397 ; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} SW
398 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
399 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
400 ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
401 ; MMR6-SF-NEXT: .cfi_offset 31, -4
402 ; MMR6-SF-NEXT: balc __fixdfsi # <MCInst #{{[0-9]+}} BALC_MMR6
403 ; MMR6-SF-NEXT: # <MCOperand Expr:(__fixdfsi)>>
404 ; MMR6-SF-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
405 ; MMR6-SF-NEXT: # <MCInst #{{[0-9]+}} LW
406 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
407 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
408 ; MMR6-SF-NEXT: # <MCOperand Imm:20>>
409 ; MMR6-SF-NEXT: addiu $sp, $sp, 24 # <MCInst #{{[0-9]+}} ADDiu
410 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
411 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>
412 ; MMR6-SF-NEXT: # <MCOperand Imm:24>>
413 ; MMR6-SF-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
414 ; MMR6-SF-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
415 entry:
416 %conv = fptosi double %t to i32
417 ret i32 %conv
418 }