| blob | 4105d67da6f1acceebe69edb6b1283671a6dd522 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
3 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
4 ; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
5 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R2
6 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic \
7 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
8 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic \
9 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
10 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic \
11 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
12 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic \
13 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP32R6
15 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
16 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
17 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic \
18 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
19 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
20 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
21 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic \
22 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
23 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic \
24 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
25 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic \
26 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
27 ; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic \
28 ; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP64R6
30 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips \
31 ; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
32 ; RUN: FileCheck %s -check-prefix=MMR3
33 ; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -mattr=+micromips \
34 ; RUN: -relocation-model=pic -mips-jalr-reloc=false | \
35 ; RUN: FileCheck %s -check-prefix=MMR6
37 define signext i1 @urem_i1(i1 signext %a, i1 signext %b) {
38 ; GP32-LABEL: urem_i1:
39 ; GP32: # %bb.0: # %entry
40 ; GP32-NEXT: jr $ra
41 ; GP32-NEXT: addiu $2, $zero, 0
42 ;
43 ; GP32R6-LABEL: urem_i1:
44 ; GP32R6: # %bb.0: # %entry
45 ; GP32R6-NEXT: jr $ra
46 ; GP32R6-NEXT: addiu $2, $zero, 0
47 ;
48 ; GP64-LABEL: urem_i1:
49 ; GP64: # %bb.0: # %entry
50 ; GP64-NEXT: jr $ra
51 ; GP64-NEXT: addiu $2, $zero, 0
52 ;
53 ; GP64R6-LABEL: urem_i1:
54 ; GP64R6: # %bb.0: # %entry
55 ; GP64R6-NEXT: jr $ra
56 ; GP64R6-NEXT: addiu $2, $zero, 0
57 ;
58 ; MMR3-LABEL: urem_i1:
59 ; MMR3: # %bb.0: # %entry
60 ; MMR3-NEXT: li16 $2, 0
61 ; MMR3-NEXT: jrc $ra
62 ;
63 ; MMR6-LABEL: urem_i1:
64 ; MMR6: # %bb.0: # %entry
65 ; MMR6-NEXT: li16 $2, 0
66 ; MMR6-NEXT: jrc $ra
67 entry:
68 %r = urem i1 %a, %b
69 ret i1 %r
70 }
72 define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
73 ; GP32R0R2-LABEL: urem_i8:
74 ; GP32R0R2: # %bb.0: # %entry
75 ; GP32R0R2-NEXT: andi $1, $5, 255
76 ; GP32R0R2-NEXT: andi $2, $4, 255
77 ; GP32R0R2-NEXT: divu $zero, $2, $1
78 ; GP32R0R2-NEXT: teq $1, $zero, 7
79 ; GP32R0R2-NEXT: mfhi $1
80 ; GP32R0R2-NEXT: sll $1, $1, 24
81 ; GP32R0R2-NEXT: jr $ra
82 ; GP32R0R2-NEXT: sra $2, $1, 24
83 ;
84 ; GP32R2R5-LABEL: urem_i8:
85 ; GP32R2R5: # %bb.0: # %entry
86 ; GP32R2R5-NEXT: andi $1, $5, 255
87 ; GP32R2R5-NEXT: andi $2, $4, 255
88 ; GP32R2R5-NEXT: divu $zero, $2, $1
89 ; GP32R2R5-NEXT: teq $1, $zero, 7
90 ; GP32R2R5-NEXT: mfhi $1
91 ; GP32R2R5-NEXT: jr $ra
92 ; GP32R2R5-NEXT: seb $2, $1
93 ;
94 ; GP32R6-LABEL: urem_i8:
95 ; GP32R6: # %bb.0: # %entry
96 ; GP32R6-NEXT: andi $1, $5, 255
97 ; GP32R6-NEXT: andi $2, $4, 255
98 ; GP32R6-NEXT: modu $2, $2, $1
99 ; GP32R6-NEXT: teq $1, $zero, 7
100 ; GP32R6-NEXT: jr $ra
101 ; GP32R6-NEXT: seb $2, $2
102 ;
103 ; GP64R0R1-LABEL: urem_i8:
104 ; GP64R0R1: # %bb.0: # %entry
105 ; GP64R0R1-NEXT: andi $1, $5, 255
106 ; GP64R0R1-NEXT: andi $2, $4, 255
107 ; GP64R0R1-NEXT: divu $zero, $2, $1
108 ; GP64R0R1-NEXT: teq $1, $zero, 7
109 ; GP64R0R1-NEXT: mfhi $1
110 ; GP64R0R1-NEXT: sll $1, $1, 24
111 ; GP64R0R1-NEXT: jr $ra
112 ; GP64R0R1-NEXT: sra $2, $1, 24
113 ;
114 ; GP64R2R5-LABEL: urem_i8:
115 ; GP64R2R5: # %bb.0: # %entry
116 ; GP64R2R5-NEXT: andi $1, $5, 255
117 ; GP64R2R5-NEXT: andi $2, $4, 255
118 ; GP64R2R5-NEXT: divu $zero, $2, $1
119 ; GP64R2R5-NEXT: teq $1, $zero, 7
120 ; GP64R2R5-NEXT: mfhi $1
121 ; GP64R2R5-NEXT: jr $ra
122 ; GP64R2R5-NEXT: seb $2, $1
123 ;
124 ; GP64R6-LABEL: urem_i8:
125 ; GP64R6: # %bb.0: # %entry
126 ; GP64R6-NEXT: andi $1, $5, 255
127 ; GP64R6-NEXT: andi $2, $4, 255
128 ; GP64R6-NEXT: modu $2, $2, $1
129 ; GP64R6-NEXT: teq $1, $zero, 7
130 ; GP64R6-NEXT: jr $ra
131 ; GP64R6-NEXT: seb $2, $2
132 ;
133 ; MMR3-LABEL: urem_i8:
134 ; MMR3: # %bb.0: # %entry
135 ; MMR3-NEXT: andi16 $2, $5, 255
136 ; MMR3-NEXT: andi16 $3, $4, 255
137 ; MMR3-NEXT: divu $zero, $3, $2
138 ; MMR3-NEXT: teq $2, $zero, 7
139 ; MMR3-NEXT: mfhi16 $1
140 ; MMR3-NEXT: jr $ra
141 ; MMR3-NEXT: seb $2, $1
142 ;
143 ; MMR6-LABEL: urem_i8:
144 ; MMR6: # %bb.0: # %entry
145 ; MMR6-NEXT: andi16 $2, $5, 255
146 ; MMR6-NEXT: andi16 $3, $4, 255
147 ; MMR6-NEXT: modu $1, $3, $2
148 ; MMR6-NEXT: teq $2, $zero, 7
149 ; MMR6-NEXT: seb $2, $1
150 ; MMR6-NEXT: jrc $ra
151 entry:
152 %r = urem i8 %a, %b
153 ret i8 %r
154 }
156 define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
157 ; GP32R0R2-LABEL: urem_i16:
158 ; GP32R0R2: # %bb.0: # %entry
159 ; GP32R0R2-NEXT: andi $1, $5, 65535
160 ; GP32R0R2-NEXT: andi $2, $4, 65535
161 ; GP32R0R2-NEXT: divu $zero, $2, $1
162 ; GP32R0R2-NEXT: teq $1, $zero, 7
163 ; GP32R0R2-NEXT: mfhi $1
164 ; GP32R0R2-NEXT: sll $1, $1, 16
165 ; GP32R0R2-NEXT: jr $ra
166 ; GP32R0R2-NEXT: sra $2, $1, 16
167 ;
168 ; GP32R2R5-LABEL: urem_i16:
169 ; GP32R2R5: # %bb.0: # %entry
170 ; GP32R2R5-NEXT: andi $1, $5, 65535
171 ; GP32R2R5-NEXT: andi $2, $4, 65535
172 ; GP32R2R5-NEXT: divu $zero, $2, $1
173 ; GP32R2R5-NEXT: teq $1, $zero, 7
174 ; GP32R2R5-NEXT: mfhi $1
175 ; GP32R2R5-NEXT: jr $ra
176 ; GP32R2R5-NEXT: seh $2, $1
177 ;
178 ; GP32R6-LABEL: urem_i16:
179 ; GP32R6: # %bb.0: # %entry
180 ; GP32R6-NEXT: andi $1, $5, 65535
181 ; GP32R6-NEXT: andi $2, $4, 65535
182 ; GP32R6-NEXT: modu $2, $2, $1
183 ; GP32R6-NEXT: teq $1, $zero, 7
184 ; GP32R6-NEXT: jr $ra
185 ; GP32R6-NEXT: seh $2, $2
186 ;
187 ; GP64R0R1-LABEL: urem_i16:
188 ; GP64R0R1: # %bb.0: # %entry
189 ; GP64R0R1-NEXT: andi $1, $5, 65535
190 ; GP64R0R1-NEXT: andi $2, $4, 65535
191 ; GP64R0R1-NEXT: divu $zero, $2, $1
192 ; GP64R0R1-NEXT: teq $1, $zero, 7
193 ; GP64R0R1-NEXT: mfhi $1
194 ; GP64R0R1-NEXT: sll $1, $1, 16
195 ; GP64R0R1-NEXT: jr $ra
196 ; GP64R0R1-NEXT: sra $2, $1, 16
197 ;
198 ; GP64R2R5-LABEL: urem_i16:
199 ; GP64R2R5: # %bb.0: # %entry
200 ; GP64R2R5-NEXT: andi $1, $5, 65535
201 ; GP64R2R5-NEXT: andi $2, $4, 65535
202 ; GP64R2R5-NEXT: divu $zero, $2, $1
203 ; GP64R2R5-NEXT: teq $1, $zero, 7
204 ; GP64R2R5-NEXT: mfhi $1
205 ; GP64R2R5-NEXT: jr $ra
206 ; GP64R2R5-NEXT: seh $2, $1
207 ;
208 ; GP64R6-LABEL: urem_i16:
209 ; GP64R6: # %bb.0: # %entry
210 ; GP64R6-NEXT: andi $1, $5, 65535
211 ; GP64R6-NEXT: andi $2, $4, 65535
212 ; GP64R6-NEXT: modu $2, $2, $1
213 ; GP64R6-NEXT: teq $1, $zero, 7
214 ; GP64R6-NEXT: jr $ra
215 ; GP64R6-NEXT: seh $2, $2
216 ;
217 ; MMR3-LABEL: urem_i16:
218 ; MMR3: # %bb.0: # %entry
219 ; MMR3-NEXT: andi16 $2, $5, 65535
220 ; MMR3-NEXT: andi16 $3, $4, 65535
221 ; MMR3-NEXT: divu $zero, $3, $2
222 ; MMR3-NEXT: teq $2, $zero, 7
223 ; MMR3-NEXT: mfhi16 $1
224 ; MMR3-NEXT: jr $ra
225 ; MMR3-NEXT: seh $2, $1
226 ;
227 ; MMR6-LABEL: urem_i16:
228 ; MMR6: # %bb.0: # %entry
229 ; MMR6-NEXT: andi16 $2, $5, 65535
230 ; MMR6-NEXT: andi16 $3, $4, 65535
231 ; MMR6-NEXT: modu $1, $3, $2
232 ; MMR6-NEXT: teq $2, $zero, 7
233 ; MMR6-NEXT: seh $2, $1
234 ; MMR6-NEXT: jrc $ra
235 entry:
236 %r = urem i16 %a, %b
237 ret i16 %r
238 }
240 define signext i32 @urem_i32(i32 signext %a, i32 signext %b) {
241 ; GP32-LABEL: urem_i32:
242 ; GP32: # %bb.0: # %entry
243 ; GP32-NEXT: divu $zero, $4, $5
244 ; GP32-NEXT: teq $5, $zero, 7
245 ; GP32-NEXT: jr $ra
246 ; GP32-NEXT: mfhi $2
247 ;
248 ; GP32R6-LABEL: urem_i32:
249 ; GP32R6: # %bb.0: # %entry
250 ; GP32R6-NEXT: modu $2, $4, $5
251 ; GP32R6-NEXT: teq $5, $zero, 7
252 ; GP32R6-NEXT: jrc $ra
253 ;
254 ; GP64-LABEL: urem_i32:
255 ; GP64: # %bb.0: # %entry
256 ; GP64-NEXT: divu $zero, $4, $5
257 ; GP64-NEXT: teq $5, $zero, 7
258 ; GP64-NEXT: jr $ra
259 ; GP64-NEXT: mfhi $2
260 ;
261 ; GP64R6-LABEL: urem_i32:
262 ; GP64R6: # %bb.0: # %entry
263 ; GP64R6-NEXT: modu $2, $4, $5
264 ; GP64R6-NEXT: teq $5, $zero, 7
265 ; GP64R6-NEXT: jrc $ra
266 ;
267 ; MMR3-LABEL: urem_i32:
268 ; MMR3: # %bb.0: # %entry
269 ; MMR3-NEXT: divu $zero, $4, $5
270 ; MMR3-NEXT: teq $5, $zero, 7
271 ; MMR3-NEXT: mfhi16 $2
272 ; MMR3-NEXT: jrc $ra
273 ;
274 ; MMR6-LABEL: urem_i32:
275 ; MMR6: # %bb.0: # %entry
276 ; MMR6-NEXT: modu $2, $4, $5
277 ; MMR6-NEXT: teq $5, $zero, 7
278 ; MMR6-NEXT: jrc $ra
279 entry:
280 %r = urem i32 %a, %b
281 ret i32 %r
282 }
284 define signext i64 @urem_i64(i64 signext %a, i64 signext %b) {
285 ; GP32-LABEL: urem_i64:
286 ; GP32: # %bb.0: # %entry
287 ; GP32-NEXT: lui $2, %hi(_gp_disp)
288 ; GP32-NEXT: addiu $2, $2, %lo(_gp_disp)
289 ; GP32-NEXT: addiu $sp, $sp, -24
290 ; GP32-NEXT: .cfi_def_cfa_offset 24
291 ; GP32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
292 ; GP32-NEXT: .cfi_offset 31, -4
293 ; GP32-NEXT: addu $gp, $2, $25
294 ; GP32-NEXT: lw $25, %call16(__umoddi3)($gp)
295 ; GP32-NEXT: jalr $25
296 ; GP32-NEXT: nop
297 ; GP32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
298 ; GP32-NEXT: jr $ra
299 ; GP32-NEXT: addiu $sp, $sp, 24
300 ;
301 ; GP32R6-LABEL: urem_i64:
302 ; GP32R6: # %bb.0: # %entry
303 ; GP32R6-NEXT: lui $2, %hi(_gp_disp)
304 ; GP32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
305 ; GP32R6-NEXT: addiu $sp, $sp, -24
306 ; GP32R6-NEXT: .cfi_def_cfa_offset 24
307 ; GP32R6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
308 ; GP32R6-NEXT: .cfi_offset 31, -4
309 ; GP32R6-NEXT: addu $gp, $2, $25
310 ; GP32R6-NEXT: lw $25, %call16(__umoddi3)($gp)
311 ; GP32R6-NEXT: jalrc $25
312 ; GP32R6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
313 ; GP32R6-NEXT: jr $ra
314 ; GP32R6-NEXT: addiu $sp, $sp, 24
315 ;
316 ; GP64-LABEL: urem_i64:
317 ; GP64: # %bb.0: # %entry
318 ; GP64-NEXT: ddivu $zero, $4, $5
319 ; GP64-NEXT: teq $5, $zero, 7
320 ; GP64-NEXT: jr $ra
321 ; GP64-NEXT: mfhi $2
322 ;
323 ; GP64R6-LABEL: urem_i64:
324 ; GP64R6: # %bb.0: # %entry
325 ; GP64R6-NEXT: dmodu $2, $4, $5
326 ; GP64R6-NEXT: teq $5, $zero, 7
327 ; GP64R6-NEXT: jrc $ra
328 ;
329 ; MMR3-LABEL: urem_i64:
330 ; MMR3: # %bb.0: # %entry
331 ; MMR3-NEXT: lui $2, %hi(_gp_disp)
332 ; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
333 ; MMR3-NEXT: addiusp -24
334 ; MMR3-NEXT: .cfi_def_cfa_offset 24
335 ; MMR3-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
336 ; MMR3-NEXT: .cfi_offset 31, -4
337 ; MMR3-NEXT: addu $2, $2, $25
338 ; MMR3-NEXT: lw $25, %call16(__umoddi3)($2)
339 ; MMR3-NEXT: move $gp, $2
340 ; MMR3-NEXT: jalr $25
341 ; MMR3-NEXT: nop
342 ; MMR3-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
343 ; MMR3-NEXT: addiusp 24
344 ; MMR3-NEXT: jrc $ra
345 ;
346 ; MMR6-LABEL: urem_i64:
347 ; MMR6: # %bb.0: # %entry
348 ; MMR6-NEXT: lui $2, %hi(_gp_disp)
349 ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
350 ; MMR6-NEXT: addiu $sp, $sp, -24
351 ; MMR6-NEXT: .cfi_def_cfa_offset 24
352 ; MMR6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
353 ; MMR6-NEXT: .cfi_offset 31, -4
354 ; MMR6-NEXT: addu $2, $2, $25
355 ; MMR6-NEXT: lw $25, %call16(__umoddi3)($2)
356 ; MMR6-NEXT: move $gp, $2
357 ; MMR6-NEXT: jalr $25
358 ; MMR6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
359 ; MMR6-NEXT: addiu $sp, $sp, 24
360 ; MMR6-NEXT: jrc $ra
361 entry:
362 %r = urem i64 %a, %b
363 ret i64 %r
364 }
366 define signext i128 @urem_i128(i128 signext %a, i128 signext %b) {
367 ; GP32-LABEL: urem_i128:
368 ; GP32: # %bb.0: # %entry
369 ; GP32-NEXT: lui $2, %hi(_gp_disp)
370 ; GP32-NEXT: addiu $2, $2, %lo(_gp_disp)
371 ; GP32-NEXT: addiu $sp, $sp, -40
372 ; GP32-NEXT: .cfi_def_cfa_offset 40
373 ; GP32-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
374 ; GP32-NEXT: .cfi_offset 31, -4
375 ; GP32-NEXT: addu $gp, $2, $25
376 ; GP32-NEXT: lw $1, 60($sp)
377 ; GP32-NEXT: lw $2, 64($sp)
378 ; GP32-NEXT: lw $3, 68($sp)
379 ; GP32-NEXT: sw $3, 28($sp)
380 ; GP32-NEXT: sw $2, 24($sp)
381 ; GP32-NEXT: sw $1, 20($sp)
382 ; GP32-NEXT: lw $1, 56($sp)
383 ; GP32-NEXT: sw $1, 16($sp)
384 ; GP32-NEXT: lw $25, %call16(__umodti3)($gp)
385 ; GP32-NEXT: jalr $25
386 ; GP32-NEXT: nop
387 ; GP32-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
388 ; GP32-NEXT: jr $ra
389 ; GP32-NEXT: addiu $sp, $sp, 40
390 ;
391 ; GP32R6-LABEL: urem_i128:
392 ; GP32R6: # %bb.0: # %entry
393 ; GP32R6-NEXT: lui $2, %hi(_gp_disp)
394 ; GP32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
395 ; GP32R6-NEXT: addiu $sp, $sp, -40
396 ; GP32R6-NEXT: .cfi_def_cfa_offset 40
397 ; GP32R6-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
398 ; GP32R6-NEXT: .cfi_offset 31, -4
399 ; GP32R6-NEXT: addu $gp, $2, $25
400 ; GP32R6-NEXT: lw $1, 60($sp)
401 ; GP32R6-NEXT: lw $2, 64($sp)
402 ; GP32R6-NEXT: lw $3, 68($sp)
403 ; GP32R6-NEXT: sw $3, 28($sp)
404 ; GP32R6-NEXT: sw $2, 24($sp)
405 ; GP32R6-NEXT: sw $1, 20($sp)
406 ; GP32R6-NEXT: lw $1, 56($sp)
407 ; GP32R6-NEXT: sw $1, 16($sp)
408 ; GP32R6-NEXT: lw $25, %call16(__umodti3)($gp)
409 ; GP32R6-NEXT: jalrc $25
410 ; GP32R6-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
411 ; GP32R6-NEXT: jr $ra
412 ; GP32R6-NEXT: addiu $sp, $sp, 40
413 ;
414 ; GP64-LABEL: urem_i128:
415 ; GP64: # %bb.0: # %entry
416 ; GP64-NEXT: daddiu $sp, $sp, -16
417 ; GP64-NEXT: .cfi_def_cfa_offset 16
418 ; GP64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
419 ; GP64-NEXT: sd $gp, 0($sp) # 8-byte Folded Spill
420 ; GP64-NEXT: .cfi_offset 31, -8
421 ; GP64-NEXT: .cfi_offset 28, -16
422 ; GP64-NEXT: lui $1, %hi(%neg(%gp_rel(urem_i128)))
423 ; GP64-NEXT: daddu $1, $1, $25
424 ; GP64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(urem_i128)))
425 ; GP64-NEXT: ld $25, %call16(__umodti3)($gp)
426 ; GP64-NEXT: jalr $25
427 ; GP64-NEXT: nop
428 ; GP64-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
429 ; GP64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
430 ; GP64-NEXT: jr $ra
431 ; GP64-NEXT: daddiu $sp, $sp, 16
432 ;
433 ; GP64R6-LABEL: urem_i128:
434 ; GP64R6: # %bb.0: # %entry
435 ; GP64R6-NEXT: daddiu $sp, $sp, -16
436 ; GP64R6-NEXT: .cfi_def_cfa_offset 16
437 ; GP64R6-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
438 ; GP64R6-NEXT: sd $gp, 0($sp) # 8-byte Folded Spill
439 ; GP64R6-NEXT: .cfi_offset 31, -8
440 ; GP64R6-NEXT: .cfi_offset 28, -16
441 ; GP64R6-NEXT: lui $1, %hi(%neg(%gp_rel(urem_i128)))
442 ; GP64R6-NEXT: daddu $1, $1, $25
443 ; GP64R6-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(urem_i128)))
444 ; GP64R6-NEXT: ld $25, %call16(__umodti3)($gp)
445 ; GP64R6-NEXT: jalrc $25
446 ; GP64R6-NEXT: ld $gp, 0($sp) # 8-byte Folded Reload
447 ; GP64R6-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
448 ; GP64R6-NEXT: jr $ra
449 ; GP64R6-NEXT: daddiu $sp, $sp, 16
450 ;
451 ; MMR3-LABEL: urem_i128:
452 ; MMR3: # %bb.0: # %entry
453 ; MMR3-NEXT: lui $2, %hi(_gp_disp)
454 ; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
455 ; MMR3-NEXT: addiusp -48
456 ; MMR3-NEXT: .cfi_def_cfa_offset 48
457 ; MMR3-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
458 ; MMR3-NEXT: swp $16, 36($sp)
459 ; MMR3-NEXT: .cfi_offset 31, -4
460 ; MMR3-NEXT: .cfi_offset 17, -8
461 ; MMR3-NEXT: .cfi_offset 16, -12
462 ; MMR3-NEXT: addu $16, $2, $25
463 ; MMR3-NEXT: move $1, $7
464 ; MMR3-NEXT: lw $7, 68($sp)
465 ; MMR3-NEXT: lw $17, 72($sp)
466 ; MMR3-NEXT: lw $3, 76($sp)
467 ; MMR3-NEXT: move $2, $sp
468 ; MMR3-NEXT: sw16 $3, 28($2)
469 ; MMR3-NEXT: sw16 $17, 24($2)
470 ; MMR3-NEXT: sw16 $7, 20($2)
471 ; MMR3-NEXT: lw $3, 64($sp)
472 ; MMR3-NEXT: sw16 $3, 16($2)
473 ; MMR3-NEXT: lw $25, %call16(__umodti3)($16)
474 ; MMR3-NEXT: move $7, $1
475 ; MMR3-NEXT: move $gp, $16
476 ; MMR3-NEXT: jalr $25
477 ; MMR3-NEXT: nop
478 ; MMR3-NEXT: lwp $16, 36($sp)
479 ; MMR3-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
480 ; MMR3-NEXT: addiusp 48
481 ; MMR3-NEXT: jrc $ra
482 ;
483 ; MMR6-LABEL: urem_i128:
484 ; MMR6: # %bb.0: # %entry
485 ; MMR6-NEXT: lui $2, %hi(_gp_disp)
486 ; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
487 ; MMR6-NEXT: addiu $sp, $sp, -48
488 ; MMR6-NEXT: .cfi_def_cfa_offset 48
489 ; MMR6-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
490 ; MMR6-NEXT: sw $17, 40($sp) # 4-byte Folded Spill
491 ; MMR6-NEXT: sw $16, 36($sp) # 4-byte Folded Spill
492 ; MMR6-NEXT: .cfi_offset 31, -4
493 ; MMR6-NEXT: .cfi_offset 17, -8
494 ; MMR6-NEXT: .cfi_offset 16, -12
495 ; MMR6-NEXT: addu $16, $2, $25
496 ; MMR6-NEXT: move $1, $7
497 ; MMR6-NEXT: lw $7, 68($sp)
498 ; MMR6-NEXT: lw $17, 72($sp)
499 ; MMR6-NEXT: lw $3, 76($sp)
500 ; MMR6-NEXT: move $2, $sp
501 ; MMR6-NEXT: sw16 $3, 28($2)
502 ; MMR6-NEXT: sw16 $17, 24($2)
503 ; MMR6-NEXT: sw16 $7, 20($2)
504 ; MMR6-NEXT: lw $3, 64($sp)
505 ; MMR6-NEXT: sw16 $3, 16($2)
506 ; MMR6-NEXT: lw $25, %call16(__umodti3)($16)
507 ; MMR6-NEXT: move $7, $1
508 ; MMR6-NEXT: move $gp, $16
509 ; MMR6-NEXT: jalr $25
510 ; MMR6-NEXT: lw $16, 36($sp) # 4-byte Folded Reload
511 ; MMR6-NEXT: lw $17, 40($sp) # 4-byte Folded Reload
512 ; MMR6-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
513 ; MMR6-NEXT: addiu $sp, $sp, 48
514 ; MMR6-NEXT: jrc $ra
515 entry:
516 %r = urem i128 %a, %b
517 ret i128 %r
518 }