| blob | f729018dd41061ed8b917e3040357aa3b3228c31 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
3 ; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
4 ; RUN: -check-prefix=P9BE -implicit-check-not frsp
5 ; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6 ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
7 ; RUN: -check-prefix=P9LE -implicit-check-not frsp
8 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
9 ; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
10 ; RUN: -check-prefix=P8BE -implicit-check-not frsp
11 ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
12 ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
13 ; RUN: -check-prefix=P8LE -implicit-check-not frsp
15 ; This test case comes from the following C test case (included as it may be
16 ; slightly more readable than the LLVM IR.
18 ;/* This test case provides various ways of building vectors to ensure we
19 ; produce optimal code for all cases. The cases are (for each type):
20 ; - All zeros
21 ; - All ones - split to build-vector-allones.ll
22 ; - Splat of a constant
23 ; - From different values already in registers
24 ; - From different constants
25 ; - From different values in memory
26 ; - Splat of a value in register
27 ; - Splat of a value in memory
28 ; - Inserting element into existing vector
29 ; - Inserting element from existing vector into existing vector
30 ;
31 ; With conversions (float <-> int)
32 ; - Splat of a constant
33 ; - From different values already in registers
34 ; - From different constants
35 ; - From different values in memory
36 ; - Splat of a value in register
37 ; - Splat of a value in memory
38 ; - Inserting element into existing vector
39 ; - Inserting element from existing vector into existing vector
40 ;*/
41 ;
42 ;/*=================================== int ===================================*/
43 ;// P8: xxlxor //
44 ;// P9: xxlxor //
45 ;vector int allZeroi() { //
46 ; return (vector int)0; //
47 ;} //
48 ;// P8: vspltisb -1 //
49 ;// P9: xxspltisb 255 //
50 ;vector int spltConst1i() { //
51 ; return (vector int)1; //
52 ;} //
53 ;// P8: vspltisw -15; vsrw //
54 ;// P9: vspltisw -15; vsrw //
55 ;vector int spltConst16ki() { //
56 ; return (vector int)((1<<15) - 1); //
57 ;} //
58 ;// P8: vspltisw -16; vsrw //
59 ;// P9: vspltisw -16; vsrw //
60 ;vector int spltConst32ki() { //
61 ; return (vector int)((1<<16) - 1); //
62 ;} //
63 ;// P8: 4 x mtvsrwz, 2 x xxmrgh, vmrgow //
64 ;// P9: 2 x mtvsrdd, vmrgow //
65 ;vector int fromRegsi(int a, int b, int c, int d) { //
66 ; return (vector int){ a, b, c, d }; //
67 ;} //
68 ;// P8: lxvd2x, xxswapd //
69 ;// P9: lxvx (or even lxv) //
70 ;vector int fromDiffConstsi() { //
71 ; return (vector int) { 242, -113, 889, 19 }; //
72 ;} //
73 ;// P8: lxvd2x, xxswapd //
74 ;// P9: lxvx //
75 ;vector int fromDiffMemConsAi(int *arr) { //
76 ; return (vector int) { arr[0], arr[1], arr[2], arr[3] }; //
77 ;} //
78 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm //
79 ;// P9: 2 x lxvx, vperm //
80 ;vector int fromDiffMemConsDi(int *arr) { //
81 ; return (vector int) { arr[3], arr[2], arr[1], arr[0] }; //
82 ;} //
83 ;// P8: sldi 2, lxvd2x, xxswapd //
84 ;// P9: sldi 2, lxvx //
85 ;vector int fromDiffMemVarAi(int *arr, int elem) { //
86 ; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
87 ;} //
88 ;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //
89 ;// P9: sldi 2, 2 x lxvx, vperm //
90 ;vector int fromDiffMemVarDi(int *arr, int elem) { //
91 ; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
92 ;} //
93 ;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
94 ;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //
95 ;vector int fromRandMemConsi(int *arr) { //
96 ; return (vector int) { arr[4], arr[18], arr[2], arr[88] }; //
97 ;} //
98 ;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
99 ;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
100 ;vector int fromRandMemVari(int *arr, int elem) { //
101 ; return (vector int) { arr[elem+4], arr[elem+1], arr[elem+2], arr[elem+8] };//
102 ;} //
103 ;// P8: mtvsrwz, xxspltw //
104 ;// P9: mtvsrws //
105 ;vector int spltRegVali(int val) { //
106 ; return (vector int) val; //
107 ;} //
108 ;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
109 ;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
110 ;vector int spltMemVali(int *ptr) { //
111 ; return (vector int)*ptr; //
112 ;} //
113 ;// P8: vspltisw //
114 ;// P9: vspltisw //
115 ;vector int spltCnstConvftoi() { //
116 ; return (vector int) 4.74f; //
117 ;} //
118 ;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
119 ;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
120 ;vector int fromRegsConvftoi(float a, float b, float c, float d) { //
121 ; return (vector int) { a, b, c, d }; //
122 ;} //
123 ;// P8: lxvd2x, xxswapd //
124 ;// P9: lxvx (even lxv) //
125 ;vector int fromDiffConstsConvftoi() { //
126 ; return (vector int) { 24.46f, 234.f, 988.19f, 422.39f }; //
127 ;} //
128 ;// P8: lxvd2x, xxswapd, xvcvspsxws //
129 ;// P9: lxvx, xvcvspsxws //
130 ;vector int fromDiffMemConsAConvftoi(ptr ptr) { //
131 ; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
132 ;} //
133 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspsxws //
134 ;// P9: 2 x lxvx, vperm, xvcvspsxws //
135 ;vector int fromDiffMemConsDConvftoi(ptr ptr) { //
136 ; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
137 ;} //
138 ;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
139 ;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
140 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
141 ;// sldi 2, load, xvcvspuxws //
142 ;vector int fromDiffMemVarAConvftoi(ptr arr, int elem) { //
143 ; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
144 ;} //
145 ;// P8: 4 x lxsspx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
146 ;// P9: 4 x lxssp, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
147 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
148 ;// sldi 2, 2 x load, vperm, xvcvspuxws //
149 ;vector int fromDiffMemVarDConvftoi(ptr arr, int elem) { //
150 ; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
151 ;} //
152 ;// P8: xscvdpsxws, xxspltw //
153 ;// P9: xscvdpsxws, xxspltw //
154 ;vector int spltRegValConvftoi(float val) { //
155 ; return (vector int) val; //
156 ;} //
157 ;// P8: lxsspx, xscvdpsxws, xxspltw //
158 ;// P9: lxvwsx, xvcvspsxws //
159 ;vector int spltMemValConvftoi(ptr ptr) { //
160 ; return (vector int)*ptr; //
161 ;} //
162 ;// P8: vspltisw //
163 ;// P9: vspltisw //
164 ;vector int spltCnstConvdtoi() { //
165 ; return (vector int) 4.74; //
166 ;} //
167 ;// P8: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
168 ;// P9: 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
169 ;vector int fromRegsConvdtoi(double a, double b, double c, double d) { //
170 ; return (vector int) { a, b, c, d }; //
171 ;} //
172 ;// P8: lxvd2x, xxswapd //
173 ;// P9: lxvx (even lxv) //
174 ;vector int fromDiffConstsConvdtoi() { //
175 ; return (vector int) { 24.46, 234., 988.19, 422.39 }; //
176 ;} //
177 ;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew //
178 ;// P9: 2 x lxvx, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspsxws, vmrgew //
179 ;vector int fromDiffMemConsAConvdtoi(ptr ptr) { //
180 ; return (vector int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
181 ;} //
182 ;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
183 ;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
184 ;vector int fromDiffMemConsDConvdtoi(ptr ptr) { //
185 ; return (vector int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
186 ;} //
187 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
188 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
189 ;vector int fromDiffMemVarAConvdtoi(ptr arr, int elem) { //
190 ; return (vector int) { arr[elem], arr[elem+1], arr[elem+2], arr[elem+3] }; //
191 ;} //
192 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
193 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspsxws, vmrgew //
194 ;vector int fromDiffMemVarDConvdtoi(ptr arr, int elem) { //
195 ; return (vector int) { arr[elem], arr[elem-1], arr[elem-2], arr[elem-3] }; //
196 ;} //
197 ;// P8: xscvdpsxws, xxspltw //
198 ;// P9: xscvdpsxws, xxspltw //
199 ;vector int spltRegValConvdtoi(double val) { //
200 ; return (vector int) val; //
201 ;} //
202 ;// P8: lxsdx, xscvdpsxws, xxspltw //
203 ;// P9: lxssp, xscvdpsxws, xxspltw //
204 ;vector int spltMemValConvdtoi(ptr ptr) { //
205 ; return (vector int)*ptr; //
206 ;} //
207 ;/*=================================== int ===================================*/
208 ;/*=============================== unsigned int ==============================*/
209 ;// P8: xxlxor //
210 ;// P9: xxlxor //
211 ;vector unsigned int allZeroui() { //
212 ; return (vector unsigned int)0; //
213 ;} //
214 ;// P8: vspltisb -1 //
215 ;// P9: xxspltisb 255 //
216 ;vector unsigned int spltConst1ui() { //
217 ; return (vector unsigned int)1; //
218 ;} //
219 ;// P8: vspltisw -15; vsrw //
220 ;// P9: vspltisw -15; vsrw //
221 ;vector unsigned int spltConst16kui() { //
222 ; return (vector unsigned int)((1<<15) - 1); //
223 ;} //
224 ;// P8: vspltisw -16; vsrw //
225 ;// P9: vspltisw -16; vsrw //
226 ;vector unsigned int spltConst32kui() { //
227 ; return (vector unsigned int)((1<<16) - 1); //
228 ;} //
229 ;// P8: 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
230 ;// P9: 2 x mtvsrdd, vmrgow //
231 ;vector unsigned int fromRegsui(unsigned int a, unsigned int b, //
232 ; unsigned int c, unsigned int d) { //
233 ; return (vector unsigned int){ a, b, c, d }; //
234 ;} //
235 ;// P8: lxvd2x, xxswapd //
236 ;// P9: lxvx (or even lxv) //
237 ;vector unsigned int fromDiffConstsui() { //
238 ; return (vector unsigned int) { 242, -113, 889, 19 }; //
239 ;} //
240 ;// P8: lxvd2x, xxswapd //
241 ;// P9: lxvx //
242 ;vector unsigned int fromDiffMemConsAui(unsigned int *arr) { //
243 ; return (vector unsigned int) { arr[0], arr[1], arr[2], arr[3] }; //
244 ;} //
245 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm //
246 ;// P9: 2 x lxvx, vperm //
247 ;vector unsigned int fromDiffMemConsDui(unsigned int *arr) { //
248 ; return (vector unsigned int) { arr[3], arr[2], arr[1], arr[0] }; //
249 ;} //
250 ;// P8: sldi 2, lxvd2x, xxswapd //
251 ;// P9: sldi 2, lxvx //
252 ;vector unsigned int fromDiffMemVarAui(unsigned int *arr, int elem) { //
253 ; return (vector unsigned int) { arr[elem], arr[elem+1], //
254 ; arr[elem+2], arr[elem+3] }; //
255 ;} //
256 ;// P8: sldi 2, 2 x lxvd2x, 2 x xxswapd, vperm //
257 ;// P9: sldi 2, 2 x lxvx, vperm //
258 ;vector unsigned int fromDiffMemVarDui(unsigned int *arr, int elem) { //
259 ; return (vector unsigned int) { arr[elem], arr[elem-1], //
260 ; arr[elem-2], arr[elem-3] }; //
261 ;} //
262 ;// P8: 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
263 ;// P9: 4 x lwz, 2 x mtvsrdd, vmrgow //
264 ;vector unsigned int fromRandMemConsui(unsigned int *arr) { //
265 ; return (vector unsigned int) { arr[4], arr[18], arr[2], arr[88] }; //
266 ;} //
267 ;// P8: sldi 2, 4 x lwz, 4 x mtvsrwz, 2 x xxmrghd, vmrgow //
268 ;// P9: sldi 2, add, 4 x lwz, 2 x mtvsrdd, vmrgow //
269 ;vector unsigned int fromRandMemVarui(unsigned int *arr, int elem) { //
270 ; return (vector unsigned int) { arr[elem+4], arr[elem+1], //
271 ; arr[elem+2], arr[elem+8] }; //
272 ;} //
273 ;// P8: mtvsrwz, xxspltw //
274 ;// P9: mtvsrws //
275 ;vector unsigned int spltRegValui(unsigned int val) { //
276 ; return (vector unsigned int) val; //
277 ;} //
278 ;// P8: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
279 ;// P9: (LE) lfiwzx, xxpermdi, xxspltw (BE): lfiwzx, xxsldwi, xxspltw //
280 ;vector unsigned int spltMemValui(unsigned int *ptr) { //
281 ; return (vector unsigned int)*ptr; //
282 ;} //
283 ;// P8: vspltisw //
284 ;// P9: vspltisw //
285 ;vector unsigned int spltCnstConvftoui() { //
286 ; return (vector unsigned int) 4.74f; //
287 ;} //
288 ;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
289 ;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
290 ;vector unsigned int fromRegsConvftoui(float a, float b, float c, float d) { //
291 ; return (vector unsigned int) { a, b, c, d }; //
292 ;} //
293 ;// P8: lxvd2x, xxswapd //
294 ;// P9: lxvx (even lxv) //
295 ;vector unsigned int fromDiffConstsConvftoui() { //
296 ; return (vector unsigned int) { 24.46f, 234.f, 988.19f, 422.39f }; //
297 ;} //
298 ;// P8: lxvd2x, xxswapd, xvcvspuxws //
299 ;// P9: lxvx, xvcvspuxws //
300 ;vector unsigned int fromDiffMemConsAConvftoui(ptr ptr) { //
301 ; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
302 ;} //
303 ;// P8: 2 x lxvd2x, 2 x xxswapd, vperm, xvcvspuxws //
304 ;// P9: 2 x lxvx, vperm, xvcvspuxws //
305 ;vector unsigned int fromDiffMemConsDConvftoui(ptr ptr) { //
306 ; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
307 ;} //
308 ;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
309 ;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
310 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
311 ;// sldi 2, load, xvcvspuxws //
312 ;vector unsigned int fromDiffMemVarAConvftoui(ptr arr, int elem) { //
313 ; return (vector unsigned int) { arr[elem], arr[elem+1], //
314 ; arr[elem+2], arr[elem+3] }; //
315 ;} //
316 ;// P8: lfsux, 3 x lxsspx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
317 ;// P9: lfsux, 3 x lfs, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
318 ;// Note: if the consecutive loads learns to handle pre-inc, this can be: //
319 ;// sldi 2, 2 x load, vperm, xvcvspuxws //
320 ;vector unsigned int fromDiffMemVarDConvftoui(ptr arr, int elem) { //
321 ; return (vector unsigned int) { arr[elem], arr[elem-1], //
322 ; arr[elem-2], arr[elem-3] }; //
323 ;} //
324 ;// P8: xscvdpuxws, xxspltw //
325 ;// P9: xscvdpuxws, xxspltw //
326 ;vector unsigned int spltRegValConvftoui(float val) { //
327 ; return (vector unsigned int) val; //
328 ;} //
329 ;// P8: lxsspx, xscvdpuxws, xxspltw //
330 ;// P9: lxvwsx, xvcvspuxws //
331 ;vector unsigned int spltMemValConvftoui(ptr ptr) { //
332 ; return (vector unsigned int)*ptr; //
333 ;} //
334 ;// P8: vspltisw //
335 ;// P9: vspltisw //
336 ;vector unsigned int spltCnstConvdtoui() { //
337 ; return (vector unsigned int) 4.74; //
338 ;} //
339 ;// P8: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
340 ;// P9: 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
341 ;vector unsigned int fromRegsConvdtoui(double a, double b, //
342 ; double c, double d) { //
343 ; return (vector unsigned int) { a, b, c, d }; //
344 ;} //
345 ;// P8: lxvd2x, xxswapd //
346 ;// P9: lxvx (even lxv) //
347 ;vector unsigned int fromDiffConstsConvdtoui() { //
348 ; return (vector unsigned int) { 24.46, 234., 988.19, 422.39 }; //
349 ;} //
350 ;// P8: 2 x lxvd2x, 2 x xxswapd, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew //
351 ;// P9: 2 x lxvx, xxmrgld, xxmrghd, 2 x xvcvspuxws, vmrgew //
352 ;vector unsigned int fromDiffMemConsAConvdtoui(ptr ptr) { //
353 ; return (vector unsigned int) { ptr[0], ptr[1], ptr[2], ptr[3] }; //
354 ;} //
355 ;// P8: 4 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
356 ;// P9: 4 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
357 ;vector unsigned int fromDiffMemConsDConvdtoui(ptr ptr) { //
358 ; return (vector unsigned int) { ptr[3], ptr[2], ptr[1], ptr[0] }; //
359 ;} //
360 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
361 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
362 ;vector unsigned int fromDiffMemVarAConvdtoui(ptr arr, int elem) { //
363 ; return (vector unsigned int) { arr[elem], arr[elem+1], //
364 ; arr[elem+2], arr[elem+3] }; //
365 ;} //
366 ;// P8: lfdux, 3 x lxsdx, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
367 ;// P9: lfdux, 3 x lfd, 2 x xxmrghd, 2 x xvcvspuxws, vmrgew //
368 ;vector unsigned int fromDiffMemVarDConvdtoui(ptr arr, int elem) { //
369 ; return (vector unsigned int) { arr[elem], arr[elem-1], //
370 ; arr[elem-2], arr[elem-3] }; //
371 ;} //
372 ;// P8: xscvdpuxws, xxspltw //
373 ;// P9: xscvdpuxws, xxspltw //
374 ;vector unsigned int spltRegValConvdtoui(double val) { //
375 ; return (vector unsigned int) val; //
376 ;} //
377 ;// P8: lxsspx, xscvdpuxws, xxspltw //
378 ;// P9: lfd, xscvdpuxws, xxspltw //
379 ;vector unsigned int spltMemValConvdtoui(ptr ptr) { //
380 ; return (vector unsigned int)*ptr; //
381 ;} //
382 ;/*=============================== unsigned int ==============================*/
383 ;/*=============================== long long =================================*/
384 ;// P8: xxlxor //
385 ;// P9: xxlxor //
386 ;vector long long allZeroll() { //
387 ; return (vector long long)0; //
388 ;} //
389 ;// P8: vspltisb -1 //
390 ;// P9: xxspltisb 255 //
391 ;vector long long spltConst1ll() { //
392 ; return (vector long long)1; //
393 ;} //
394 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
395 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
396 ;vector long long spltConst16kll() { //
397 ; return (vector long long)((1<<15) - 1); //
398 ;} //
399 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
400 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
401 ;vector long long spltConst32kll() { //
402 ; return (vector long long)((1<<16) - 1); //
403 ;} //
404 ;// P8: 2 x mtvsrd, xxmrghd //
405 ;// P9: mtvsrdd //
406 ;vector long long fromRegsll(long long a, long long b) { //
407 ; return (vector long long){ a, b }; //
408 ;} //
409 ;// P8: lxvd2x, xxswapd //
410 ;// P9: lxvx (or even lxv) //
411 ;vector long long fromDiffConstsll() { //
412 ; return (vector long long) { 242, -113 }; //
413 ;} //
414 ;// P8: lxvd2x, xxswapd //
415 ;// P9: lxvx //
416 ;vector long long fromDiffMemConsAll(long long *arr) { //
417 ; return (vector long long) { arr[0], arr[1] }; //
418 ;} //
419 ;// P8: lxvd2x //
420 ;// P9: lxvx, xxswapd (maybe just use lxvd2x) //
421 ;vector long long fromDiffMemConsDll(long long *arr) { //
422 ; return (vector long long) { arr[3], arr[2] }; //
423 ;} //
424 ;// P8: sldi 3, lxvd2x, xxswapd //
425 ;// P9: sldi 3, lxvx //
426 ;vector long long fromDiffMemVarAll(long long *arr, int elem) { //
427 ; return (vector long long) { arr[elem], arr[elem+1] }; //
428 ;} //
429 ;// P8: sldi 3, lxvd2x //
430 ;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) //
431 ;vector long long fromDiffMemVarDll(long long *arr, int elem) { //
432 ; return (vector long long) { arr[elem], arr[elem-1] }; //
433 ;} //
434 ;// P8: 2 x ld, 2 x mtvsrd, xxmrghd //
435 ;// P9: 2 x ld, mtvsrdd //
436 ;vector long long fromRandMemConsll(long long *arr) { //
437 ; return (vector long long) { arr[4], arr[18] }; //
438 ;} //
439 ;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd //
440 ;// P9: sldi 3, add, 2 x ld, mtvsrdd //
441 ;vector long long fromRandMemVarll(long long *arr, int elem) { //
442 ; return (vector long long) { arr[elem+4], arr[elem+1] }; //
443 ;} //
444 ;// P8: mtvsrd, xxspltd //
445 ;// P9: mtvsrdd //
446 ;vector long long spltRegValll(long long val) { //
447 ; return (vector long long) val; //
448 ;} //
449 ;// P8: lxvdsx //
450 ;// P9: lxvdsx //
451 ;vector long long spltMemValll(long long *ptr) { //
452 ; return (vector long long)*ptr; //
453 ;} //
454 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
455 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
456 ;vector long long spltCnstConvftoll() { //
457 ; return (vector long long) 4.74f; //
458 ;} //
459 ;// P8: xxmrghd, xvcvdpsxds //
460 ;// P9: xxmrghd, xvcvdpsxds //
461 ;vector long long fromRegsConvftoll(float a, float b) { //
462 ; return (vector long long) { a, b }; //
463 ;} //
464 ;// P8: lxvd2x, xxswapd //
465 ;// P9: lxvx (even lxv) //
466 ;vector long long fromDiffConstsConvftoll() { //
467 ; return (vector long long) { 24.46f, 234.f }; //
468 ;} //
469 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds //
470 ;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds //
471 ;vector long long fromDiffMemConsAConvftoll(ptr ptr) { //
472 ; return (vector long long) { ptr[0], ptr[1] }; //
473 ;} //
474 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpsxds //
475 ;// P9: 2 x lxssp, xxmrghd, xvcvdpsxds //
476 ;vector long long fromDiffMemConsDConvftoll(ptr ptr) { //
477 ; return (vector long long) { ptr[3], ptr[2] }; //
478 ;} //
479 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds //
480 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds //
481 ;vector long long fromDiffMemVarAConvftoll(ptr arr, int elem) { //
482 ; return (vector long long) { arr[elem], arr[elem+1] }; //
483 ;} //
484 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpsxds //
485 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpsxds //
486 ;vector long long fromDiffMemVarDConvftoll(ptr arr, int elem) { //
487 ; return (vector long long) { arr[elem], arr[elem-1] }; //
488 ;} //
489 ;// P8: xscvdpsxds, xxspltd //
490 ;// P9: xscvdpsxds, xxspltd //
491 ;vector long long spltRegValConvftoll(float val) { //
492 ; return (vector long long) val; //
493 ;} //
494 ;// P8: lxsspx, xscvdpsxds, xxspltd //
495 ;// P9: lfs, xscvdpsxds, xxspltd //
496 ;vector long long spltMemValConvftoll(ptr ptr) { //
497 ; return (vector long long)*ptr; //
498 ;} //
499 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
500 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
501 ;vector long long spltCnstConvdtoll() { //
502 ; return (vector long long) 4.74; //
503 ;} //
504 ;// P8: xxmrghd, xvcvdpsxds //
505 ;// P9: xxmrghd, xvcvdpsxds //
506 ;vector long long fromRegsConvdtoll(double a, double b) { //
507 ; return (vector long long) { a, b }; //
508 ;} //
509 ;// P8: lxvd2x, xxswapd //
510 ;// P9: lxvx (even lxv) //
511 ;vector long long fromDiffConstsConvdtoll() { //
512 ; return (vector long long) { 24.46, 234. }; //
513 ;} //
514 ;// P8: lxvd2x, xxswapd, xvcvdpsxds //
515 ;// P9: lxvx, xvcvdpsxds //
516 ;vector long long fromDiffMemConsAConvdtoll(ptr ptr) { //
517 ; return (vector long long) { ptr[0], ptr[1] }; //
518 ;} //
519 ;// P8: lxvd2x, xvcvdpsxds //
520 ;// P9: lxvx, xxswapd, xvcvdpsxds //
521 ;vector long long fromDiffMemConsDConvdtoll(ptr ptr) { //
522 ; return (vector long long) { ptr[3], ptr[2] }; //
523 ;} //
524 ;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpsxds //
525 ;// P9: sldi 3, lxvx, xvcvdpsxds //
526 ;vector long long fromDiffMemVarAConvdtoll(ptr arr, int elem) { //
527 ; return (vector long long) { arr[elem], arr[elem+1] }; //
528 ;} //
529 ;// P8: sldi 3, lxvd2x, xvcvdpsxds //
530 ;// P9: sldi 3, lxvx, xxswapd, xvcvdpsxds //
531 ;vector long long fromDiffMemVarDConvdtoll(ptr arr, int elem) { //
532 ; return (vector long long) { arr[elem], arr[elem-1] }; //
533 ;} //
534 ;// P8: xscvdpsxds, xxspltd //
535 ;// P9: xscvdpsxds, xxspltd //
536 ;vector long long spltRegValConvdtoll(double val) { //
537 ; return (vector long long) val; //
538 ;} //
539 ;// P8: lxvdsx, xvcvdpsxds //
540 ;// P9: lxvdsx, xvcvdpsxds //
541 ;vector long long spltMemValConvdtoll(ptr ptr) { //
542 ; return (vector long long)*ptr; //
543 ;} //
544 ;/*=============================== long long =================================*/
545 ;/*========================== unsigned long long =============================*/
546 ;// P8: xxlxor //
547 ;// P9: xxlxor //
548 ;vector unsigned long long allZeroull() { //
549 ; return (vector unsigned long long)0; //
550 ;} //
551 ;// P8: vspltisb -1 //
552 ;// P9: xxspltisb 255 //
553 ;vector unsigned long long spltConst1ull() { //
554 ; return (vector unsigned long long)1; //
555 ;} //
556 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
557 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
558 ;vector unsigned long long spltConst16kull() { //
559 ; return (vector unsigned long long)((1<<15) - 1); //
560 ;} //
561 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
562 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw, vsrw)) //
563 ;vector unsigned long long spltConst32kull() { //
564 ; return (vector unsigned long long)((1<<16) - 1); //
565 ;} //
566 ;// P8: 2 x mtvsrd, xxmrghd //
567 ;// P9: mtvsrdd //
568 ;vector unsigned long long fromRegsull(unsigned long long a, //
569 ; unsigned long long b) { //
570 ; return (vector unsigned long long){ a, b }; //
571 ;} //
572 ;// P8: lxvd2x, xxswapd //
573 ;// P9: lxvx (or even lxv) //
574 ;vector unsigned long long fromDiffConstsull() { //
575 ; return (vector unsigned long long) { 242, -113 }; //
576 ;} //
577 ;// P8: lxvd2x, xxswapd //
578 ;// P9: lxvx //
579 ;vector unsigned long long fromDiffMemConsAull(unsigned long long *arr) { //
580 ; return (vector unsigned long long) { arr[0], arr[1] }; //
581 ;} //
582 ;// P8: lxvd2x //
583 ;// P9: lxvx, xxswapd (maybe just use lxvd2x) //
584 ;vector unsigned long long fromDiffMemConsDull(unsigned long long *arr) { //
585 ; return (vector unsigned long long) { arr[3], arr[2] }; //
586 ;} //
587 ;// P8: sldi 3, lxvd2x, xxswapd //
588 ;// P9: sldi 3, lxvx //
589 ;vector unsigned long long fromDiffMemVarAull(unsigned long long *arr, //
590 ; int elem) { //
591 ; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
592 ;} //
593 ;// P8: sldi 3, lxvd2x //
594 ;// P9: sldi 3, lxvx, xxswapd (maybe just use lxvd2x) //
595 ;vector unsigned long long fromDiffMemVarDull(unsigned long long *arr, //
596 ; int elem) { //
597 ; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
598 ;} //
599 ;// P8: 2 x ld, 2 x mtvsrd, xxmrghd //
600 ;// P9: 2 x ld, mtvsrdd //
601 ;vector unsigned long long fromRandMemConsull(unsigned long long *arr) { //
602 ; return (vector unsigned long long) { arr[4], arr[18] }; //
603 ;} //
604 ;// P8: sldi 3, add, 2 x ld, 2 x mtvsrd, xxmrghd //
605 ;// P9: sldi 3, add, 2 x ld, mtvsrdd //
606 ;vector unsigned long long fromRandMemVarull(unsigned long long *arr, //
607 ; int elem) { //
608 ; return (vector unsigned long long) { arr[elem+4], arr[elem+1] }; //
609 ;} //
610 ;// P8: mtvsrd, xxspltd //
611 ;// P9: mtvsrdd //
612 ;vector unsigned long long spltRegValull(unsigned long long val) { //
613 ; return (vector unsigned long long) val; //
614 ;} //
615 ;// P8: lxvdsx //
616 ;// P9: lxvdsx //
617 ;vector unsigned long long spltMemValull(unsigned long long *ptr) { //
618 ; return (vector unsigned long long)*ptr; //
619 ;} //
620 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
621 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
622 ;vector unsigned long long spltCnstConvftoull() { //
623 ; return (vector unsigned long long) 4.74f; //
624 ;} //
625 ;// P8: xxmrghd, xvcvdpuxds //
626 ;// P9: xxmrghd, xvcvdpuxds //
627 ;vector unsigned long long fromRegsConvftoull(float a, float b) { //
628 ; return (vector unsigned long long) { a, b }; //
629 ;} //
630 ;// P8: lxvd2x, xxswapd //
631 ;// P9: lxvx (even lxv) //
632 ;vector unsigned long long fromDiffConstsConvftoull() { //
633 ; return (vector unsigned long long) { 24.46f, 234.f }; //
634 ;} //
635 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds //
636 ;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds //
637 ;vector unsigned long long fromDiffMemConsAConvftoull(ptr ptr) { //
638 ; return (vector unsigned long long) { ptr[0], ptr[1] }; //
639 ;} //
640 ;// P8: 2 x lxsspx, xxmrghd, xvcvdpuxds //
641 ;// P9: 2 x lxssp, xxmrghd, xvcvdpuxds //
642 ;vector unsigned long long fromDiffMemConsDConvftoull(ptr ptr) { //
643 ; return (vector unsigned long long) { ptr[3], ptr[2] }; //
644 ;} //
645 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds //
646 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds //
647 ;vector unsigned long long fromDiffMemVarAConvftoull(ptr arr, int elem) { //
648 ; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
649 ;} //
650 ;// P8: sldi 2, lfsux, lxsspx, xxmrghd, xvcvdpuxds //
651 ;// P9: sldi 2, lfsux, lfs, xxmrghd, xvcvdpuxds //
652 ;vector unsigned long long fromDiffMemVarDConvftoull(ptr arr, int elem) { //
653 ; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
654 ;} //
655 ;// P8: xscvdpuxds, xxspltd //
656 ;// P9: xscvdpuxds, xxspltd //
657 ;vector unsigned long long spltRegValConvftoull(float val) { //
658 ; return (vector unsigned long long) val; //
659 ;} //
660 ;// P8: lxsspx, xscvdpuxds, xxspltd //
661 ;// P9: lfs, xscvdpuxds, xxspltd //
662 ;vector unsigned long long spltMemValConvftoull(ptr ptr) { //
663 ; return (vector unsigned long long)*ptr; //
664 ;} //
665 ;// P8: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
666 ;// P9: constant pool load (possible: vmrgew (xxlxor), (vspltisw)) //
667 ;vector unsigned long long spltCnstConvdtoull() { //
668 ; return (vector unsigned long long) 4.74; //
669 ;} //
670 ;// P8: xxmrghd, xvcvdpuxds //
671 ;// P9: xxmrghd, xvcvdpuxds //
672 ;vector unsigned long long fromRegsConvdtoull(double a, double b) { //
673 ; return (vector unsigned long long) { a, b }; //
674 ;} //
675 ;// P8: lxvd2x, xxswapd //
676 ;// P9: lxvx (even lxv) //
677 ;vector unsigned long long fromDiffConstsConvdtoull() { //
678 ; return (vector unsigned long long) { 24.46, 234. }; //
679 ;} //
680 ;// P8: lxvd2x, xxswapd, xvcvdpuxds //
681 ;// P9: lxvx, xvcvdpuxds //
682 ;vector unsigned long long fromDiffMemConsAConvdtoull(ptr ptr) { //
683 ; return (vector unsigned long long) { ptr[0], ptr[1] }; //
684 ;} //
685 ;// P8: lxvd2x, xvcvdpuxds //
686 ;// P9: lxvx, xxswapd, xvcvdpuxds //
687 ;vector unsigned long long fromDiffMemConsDConvdtoull(ptr ptr) { //
688 ; return (vector unsigned long long) { ptr[3], ptr[2] }; //
689 ;} //
690 ;// P8: sldi 3, lxvd2x, xxswapd, xvcvdpuxds //
691 ;// P9: sldi 3, lxvx, xvcvdpuxds //
692 ;vector unsigned long long fromDiffMemVarAConvdtoull(ptr arr, int elem) { //
693 ; return (vector unsigned long long) { arr[elem], arr[elem+1] }; //
694 ;} //
695 ;// P8: sldi 3, lxvd2x, xvcvdpuxds //
696 ;// P9: sldi 3, lxvx, xxswapd, xvcvdpuxds //
697 ;vector unsigned long long fromDiffMemVarDConvdtoull(ptr arr, int elem) { //
698 ; return (vector unsigned long long) { arr[elem], arr[elem-1] }; //
699 ;} //
700 ;// P8: xscvdpuxds, xxspltd //
701 ;// P9: xscvdpuxds, xxspltd //
702 ;vector unsigned long long spltRegValConvdtoull(double val) { //
703 ; return (vector unsigned long long) val; //
704 ;} //
705 ;// P8: lxvdsx, xvcvdpuxds //
706 ;// P9: lxvdsx, xvcvdpuxds //
707 ;vector unsigned long long spltMemValConvdtoull(ptr ptr) { //
708 ; return (vector unsigned long long)*ptr; //
709 ;} //
710 ;/*========================== unsigned long long ==============================*/
712 define <4 x i32> @allZeroi() {
713 ; P9BE-LABEL: allZeroi:
714 ; P9BE: # %bb.0: # %entry
715 ; P9BE-NEXT: xxlxor v2, v2, v2
716 ; P9BE-NEXT: blr
717 ;
718 ; P9LE-LABEL: allZeroi:
719 ; P9LE: # %bb.0: # %entry
720 ; P9LE-NEXT: xxlxor v2, v2, v2
721 ; P9LE-NEXT: blr
722 ;
723 ; P8BE-LABEL: allZeroi:
724 ; P8BE: # %bb.0: # %entry
725 ; P8BE-NEXT: xxlxor v2, v2, v2
726 ; P8BE-NEXT: blr
727 ;
728 ; P8LE-LABEL: allZeroi:
729 ; P8LE: # %bb.0: # %entry
730 ; P8LE-NEXT: xxlxor v2, v2, v2
731 ; P8LE-NEXT: blr
732 entry:
733 ret <4 x i32> zeroinitializer
734 }
736 define <4 x i32> @spltConst1i() {
737 ; P9BE-LABEL: spltConst1i:
738 ; P9BE: # %bb.0: # %entry
739 ; P9BE-NEXT: vspltisw v2, 1
740 ; P9BE-NEXT: blr
741 ;
742 ; P9LE-LABEL: spltConst1i:
743 ; P9LE: # %bb.0: # %entry
744 ; P9LE-NEXT: vspltisw v2, 1
745 ; P9LE-NEXT: blr
746 ;
747 ; P8BE-LABEL: spltConst1i:
748 ; P8BE: # %bb.0: # %entry
749 ; P8BE-NEXT: vspltisw v2, 1
750 ; P8BE-NEXT: blr
751 ;
752 ; P8LE-LABEL: spltConst1i:
753 ; P8LE: # %bb.0: # %entry
754 ; P8LE-NEXT: vspltisw v2, 1
755 ; P8LE-NEXT: blr
756 entry:
757 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
758 }
760 define <4 x i32> @spltConst16ki() {
761 ; P9BE-LABEL: spltConst16ki:
762 ; P9BE: # %bb.0: # %entry
763 ; P9BE-NEXT: vspltisw v2, -15
764 ; P9BE-NEXT: vsrw v2, v2, v2
765 ; P9BE-NEXT: blr
766 ;
767 ; P9LE-LABEL: spltConst16ki:
768 ; P9LE: # %bb.0: # %entry
769 ; P9LE-NEXT: vspltisw v2, -15
770 ; P9LE-NEXT: vsrw v2, v2, v2
771 ; P9LE-NEXT: blr
772 ;
773 ; P8BE-LABEL: spltConst16ki:
774 ; P8BE: # %bb.0: # %entry
775 ; P8BE-NEXT: vspltisw v2, -15
776 ; P8BE-NEXT: vsrw v2, v2, v2
777 ; P8BE-NEXT: blr
778 ;
779 ; P8LE-LABEL: spltConst16ki:
780 ; P8LE: # %bb.0: # %entry
781 ; P8LE-NEXT: vspltisw v2, -15
782 ; P8LE-NEXT: vsrw v2, v2, v2
783 ; P8LE-NEXT: blr
784 entry:
785 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
786 }
788 define <4 x i32> @spltConst32ki() {
789 ; P9BE-LABEL: spltConst32ki:
790 ; P9BE: # %bb.0: # %entry
791 ; P9BE-NEXT: vspltisw v2, -16
792 ; P9BE-NEXT: vsrw v2, v2, v2
793 ; P9BE-NEXT: blr
794 ;
795 ; P9LE-LABEL: spltConst32ki:
796 ; P9LE: # %bb.0: # %entry
797 ; P9LE-NEXT: vspltisw v2, -16
798 ; P9LE-NEXT: vsrw v2, v2, v2
799 ; P9LE-NEXT: blr
800 ;
801 ; P8BE-LABEL: spltConst32ki:
802 ; P8BE: # %bb.0: # %entry
803 ; P8BE-NEXT: vspltisw v2, -16
804 ; P8BE-NEXT: vsrw v2, v2, v2
805 ; P8BE-NEXT: blr
806 ;
807 ; P8LE-LABEL: spltConst32ki:
808 ; P8LE: # %bb.0: # %entry
809 ; P8LE-NEXT: vspltisw v2, -16
810 ; P8LE-NEXT: vsrw v2, v2, v2
811 ; P8LE-NEXT: blr
812 entry:
813 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
814 }
816 define <4 x i32> @fromRegsi(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) {
817 ; P9BE-LABEL: fromRegsi:
818 ; P9BE: # %bb.0: # %entry
819 ; P9BE-NEXT: rldimi r6, r5, 32, 0
820 ; P9BE-NEXT: rldimi r4, r3, 32, 0
821 ; P9BE-NEXT: mtvsrdd v2, r4, r6
822 ; P9BE-NEXT: blr
823 ;
824 ; P9LE-LABEL: fromRegsi:
825 ; P9LE: # %bb.0: # %entry
826 ; P9LE-NEXT: rldimi r3, r4, 32, 0
827 ; P9LE-NEXT: rldimi r5, r6, 32, 0
828 ; P9LE-NEXT: mtvsrdd v2, r5, r3
829 ; P9LE-NEXT: blr
830 ;
831 ; P8BE-LABEL: fromRegsi:
832 ; P8BE: # %bb.0: # %entry
833 ; P8BE-NEXT: rldimi r6, r5, 32, 0
834 ; P8BE-NEXT: rldimi r4, r3, 32, 0
835 ; P8BE-NEXT: mtfprd f0, r6
836 ; P8BE-NEXT: mtfprd f1, r4
837 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
838 ; P8BE-NEXT: blr
839 ;
840 ; P8LE-LABEL: fromRegsi:
841 ; P8LE: # %bb.0: # %entry
842 ; P8LE-NEXT: rldimi r3, r4, 32, 0
843 ; P8LE-NEXT: rldimi r5, r6, 32, 0
844 ; P8LE-NEXT: mtfprd f0, r3
845 ; P8LE-NEXT: mtfprd f1, r5
846 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
847 ; P8LE-NEXT: blr
848 entry:
849 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
850 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
851 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
852 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
853 ret <4 x i32> %vecinit3
854 }
856 define <4 x i32> @fromDiffConstsi() {
857 ; P9BE-LABEL: fromDiffConstsi:
858 ; P9BE: # %bb.0: # %entry
859 ; P9BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
860 ; P9BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
861 ; P9BE-NEXT: lxv v2, 0(r3)
862 ; P9BE-NEXT: blr
863 ;
864 ; P9LE-LABEL: fromDiffConstsi:
865 ; P9LE: # %bb.0: # %entry
866 ; P9LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
867 ; P9LE-NEXT: addi r3, r3, .LCPI5_0@toc@l
868 ; P9LE-NEXT: lxv v2, 0(r3)
869 ; P9LE-NEXT: blr
870 ;
871 ; P8BE-LABEL: fromDiffConstsi:
872 ; P8BE: # %bb.0: # %entry
873 ; P8BE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
874 ; P8BE-NEXT: addi r3, r3, .LCPI5_0@toc@l
875 ; P8BE-NEXT: lxvw4x v2, 0, r3
876 ; P8BE-NEXT: blr
877 ;
878 ; P8LE-LABEL: fromDiffConstsi:
879 ; P8LE: # %bb.0: # %entry
880 ; P8LE-NEXT: addis r3, r2, .LCPI5_0@toc@ha
881 ; P8LE-NEXT: addi r3, r3, .LCPI5_0@toc@l
882 ; P8LE-NEXT: lxvd2x vs0, 0, r3
883 ; P8LE-NEXT: xxswapd v2, vs0
884 ; P8LE-NEXT: blr
885 entry:
886 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
887 }
889 define <4 x i32> @fromDiffMemConsAi(ptr nocapture readonly %arr) {
890 ; P9BE-LABEL: fromDiffMemConsAi:
891 ; P9BE: # %bb.0: # %entry
892 ; P9BE-NEXT: lxv v2, 0(r3)
893 ; P9BE-NEXT: blr
894 ;
895 ; P9LE-LABEL: fromDiffMemConsAi:
896 ; P9LE: # %bb.0: # %entry
897 ; P9LE-NEXT: lxv v2, 0(r3)
898 ; P9LE-NEXT: blr
899 ;
900 ; P8BE-LABEL: fromDiffMemConsAi:
901 ; P8BE: # %bb.0: # %entry
902 ; P8BE-NEXT: lxvw4x v2, 0, r3
903 ; P8BE-NEXT: blr
904 ;
905 ; P8LE-LABEL: fromDiffMemConsAi:
906 ; P8LE: # %bb.0: # %entry
907 ; P8LE-NEXT: lxvd2x vs0, 0, r3
908 ; P8LE-NEXT: xxswapd v2, vs0
909 ; P8LE-NEXT: blr
910 entry:
911 %0 = load i32, ptr %arr, align 4
912 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
913 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 1
914 %1 = load i32, ptr %arrayidx1, align 4
915 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
916 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2
917 %2 = load i32, ptr %arrayidx3, align 4
918 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
919 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 3
920 %3 = load i32, ptr %arrayidx5, align 4
921 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
922 ret <4 x i32> %vecinit6
923 }
925 define <4 x i32> @fromDiffMemConsDi(ptr nocapture readonly %arr) {
926 ; P9BE-LABEL: fromDiffMemConsDi:
927 ; P9BE: # %bb.0: # %entry
928 ; P9BE-NEXT: lxv v2, 0(r3)
929 ; P9BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha
930 ; P9BE-NEXT: addi r3, r3, .LCPI7_0@toc@l
931 ; P9BE-NEXT: lxv vs0, 0(r3)
932 ; P9BE-NEXT: xxperm v2, v2, vs0
933 ; P9BE-NEXT: blr
934 ;
935 ; P9LE-LABEL: fromDiffMemConsDi:
936 ; P9LE: # %bb.0: # %entry
937 ; P9LE-NEXT: lxvw4x v2, 0, r3
938 ; P9LE-NEXT: blr
939 ;
940 ; P8BE-LABEL: fromDiffMemConsDi:
941 ; P8BE: # %bb.0: # %entry
942 ; P8BE-NEXT: lxvw4x v2, 0, r3
943 ; P8BE-NEXT: addis r3, r2, .LCPI7_0@toc@ha
944 ; P8BE-NEXT: addi r3, r3, .LCPI7_0@toc@l
945 ; P8BE-NEXT: lxvw4x v3, 0, r3
946 ; P8BE-NEXT: vperm v2, v2, v2, v3
947 ; P8BE-NEXT: blr
948 ;
949 ; P8LE-LABEL: fromDiffMemConsDi:
950 ; P8LE: # %bb.0: # %entry
951 ; P8LE-NEXT: lxvd2x vs0, 0, r3
952 ; P8LE-NEXT: addis r3, r2, .LCPI7_0@toc@ha
953 ; P8LE-NEXT: addi r3, r3, .LCPI7_0@toc@l
954 ; P8LE-NEXT: xxswapd v2, vs0
955 ; P8LE-NEXT: lxvd2x vs0, 0, r3
956 ; P8LE-NEXT: xxswapd v3, vs0
957 ; P8LE-NEXT: vperm v2, v2, v2, v3
958 ; P8LE-NEXT: blr
959 entry:
960 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 3
961 %0 = load i32, ptr %arrayidx, align 4
962 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
963 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 2
964 %1 = load i32, ptr %arrayidx1, align 4
965 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
966 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 1
967 %2 = load i32, ptr %arrayidx3, align 4
968 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
969 %3 = load i32, ptr %arr, align 4
970 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
971 ret <4 x i32> %vecinit6
972 }
974 define <4 x i32> @fromDiffMemVarAi(ptr nocapture readonly %arr, i32 signext %elem) {
975 ; P9BE-LABEL: fromDiffMemVarAi:
976 ; P9BE: # %bb.0: # %entry
977 ; P9BE-NEXT: sldi r4, r4, 2
978 ; P9BE-NEXT: lxvx v2, r3, r4
979 ; P9BE-NEXT: blr
980 ;
981 ; P9LE-LABEL: fromDiffMemVarAi:
982 ; P9LE: # %bb.0: # %entry
983 ; P9LE-NEXT: sldi r4, r4, 2
984 ; P9LE-NEXT: lxvx v2, r3, r4
985 ; P9LE-NEXT: blr
986 ;
987 ; P8BE-LABEL: fromDiffMemVarAi:
988 ; P8BE: # %bb.0: # %entry
989 ; P8BE-NEXT: sldi r4, r4, 2
990 ; P8BE-NEXT: lxvw4x v2, r3, r4
991 ; P8BE-NEXT: blr
992 ;
993 ; P8LE-LABEL: fromDiffMemVarAi:
994 ; P8LE: # %bb.0: # %entry
995 ; P8LE-NEXT: sldi r4, r4, 2
996 ; P8LE-NEXT: lxvd2x vs0, r3, r4
997 ; P8LE-NEXT: xxswapd v2, vs0
998 ; P8LE-NEXT: blr
999 entry:
1000 %idxprom = sext i32 %elem to i64
1001 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
1002 %0 = load i32, ptr %arrayidx, align 4
1003 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1004 %add = add nsw i32 %elem, 1
1005 %idxprom1 = sext i32 %add to i64
1006 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1
1007 %1 = load i32, ptr %arrayidx2, align 4
1008 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1009 %add4 = add nsw i32 %elem, 2
1010 %idxprom5 = sext i32 %add4 to i64
1011 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5
1012 %2 = load i32, ptr %arrayidx6, align 4
1013 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
1014 %add8 = add nsw i32 %elem, 3
1015 %idxprom9 = sext i32 %add8 to i64
1016 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9
1017 %3 = load i32, ptr %arrayidx10, align 4
1018 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
1019 ret <4 x i32> %vecinit11
1020 }
1022 define <4 x i32> @fromDiffMemVarDi(ptr nocapture readonly %arr, i32 signext %elem) {
1023 ; P9BE-LABEL: fromDiffMemVarDi:
1024 ; P9BE: # %bb.0: # %entry
1025 ; P9BE-NEXT: sldi r4, r4, 2
1026 ; P9BE-NEXT: add r3, r3, r4
1027 ; P9BE-NEXT: li r4, -12
1028 ; P9BE-NEXT: lxvx v2, r3, r4
1029 ; P9BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha
1030 ; P9BE-NEXT: addi r3, r3, .LCPI9_0@toc@l
1031 ; P9BE-NEXT: lxv vs0, 0(r3)
1032 ; P9BE-NEXT: xxperm v2, v2, vs0
1033 ; P9BE-NEXT: blr
1034 ;
1035 ; P9LE-LABEL: fromDiffMemVarDi:
1036 ; P9LE: # %bb.0: # %entry
1037 ; P9LE-NEXT: sldi r4, r4, 2
1038 ; P9LE-NEXT: add r3, r3, r4
1039 ; P9LE-NEXT: li r4, -12
1040 ; P9LE-NEXT: lxvx v2, r3, r4
1041 ; P9LE-NEXT: addis r3, r2, .LCPI9_0@toc@ha
1042 ; P9LE-NEXT: addi r3, r3, .LCPI9_0@toc@l
1043 ; P9LE-NEXT: lxv vs0, 0(r3)
1044 ; P9LE-NEXT: xxperm v2, v2, vs0
1045 ; P9LE-NEXT: blr
1046 ;
1047 ; P8BE-LABEL: fromDiffMemVarDi:
1048 ; P8BE: # %bb.0: # %entry
1049 ; P8BE-NEXT: sldi r4, r4, 2
1050 ; P8BE-NEXT: add r3, r3, r4
1051 ; P8BE-NEXT: addi r3, r3, -12
1052 ; P8BE-NEXT: lxvw4x v2, 0, r3
1053 ; P8BE-NEXT: addis r3, r2, .LCPI9_0@toc@ha
1054 ; P8BE-NEXT: addi r3, r3, .LCPI9_0@toc@l
1055 ; P8BE-NEXT: lxvw4x v3, 0, r3
1056 ; P8BE-NEXT: vperm v2, v2, v2, v3
1057 ; P8BE-NEXT: blr
1058 ;
1059 ; P8LE-LABEL: fromDiffMemVarDi:
1060 ; P8LE: # %bb.0: # %entry
1061 ; P8LE-NEXT: addis r5, r2, .LCPI9_0@toc@ha
1062 ; P8LE-NEXT: sldi r4, r4, 2
1063 ; P8LE-NEXT: addi r5, r5, .LCPI9_0@toc@l
1064 ; P8LE-NEXT: add r3, r3, r4
1065 ; P8LE-NEXT: lxvd2x vs0, 0, r5
1066 ; P8LE-NEXT: addi r3, r3, -12
1067 ; P8LE-NEXT: lxvd2x v3, 0, r3
1068 ; P8LE-NEXT: xxswapd v2, vs0
1069 ; P8LE-NEXT: vperm v2, v3, v3, v2
1070 ; P8LE-NEXT: blr
1071 entry:
1072 %idxprom = sext i32 %elem to i64
1073 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
1074 %0 = load i32, ptr %arrayidx, align 4
1075 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1076 %sub = add nsw i32 %elem, -1
1077 %idxprom1 = sext i32 %sub to i64
1078 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1
1079 %1 = load i32, ptr %arrayidx2, align 4
1080 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1081 %sub4 = add nsw i32 %elem, -2
1082 %idxprom5 = sext i32 %sub4 to i64
1083 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5
1084 %2 = load i32, ptr %arrayidx6, align 4
1085 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
1086 %sub8 = add nsw i32 %elem, -3
1087 %idxprom9 = sext i32 %sub8 to i64
1088 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9
1089 %3 = load i32, ptr %arrayidx10, align 4
1090 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
1091 ret <4 x i32> %vecinit11
1092 }
1094 define <4 x i32> @fromRandMemConsi(ptr nocapture readonly %arr) {
1095 ; P9BE-LABEL: fromRandMemConsi:
1096 ; P9BE: # %bb.0: # %entry
1097 ; P9BE-NEXT: lwz r4, 16(r3)
1098 ; P9BE-NEXT: lwz r5, 72(r3)
1099 ; P9BE-NEXT: lwz r6, 8(r3)
1100 ; P9BE-NEXT: lwz r3, 352(r3)
1101 ; P9BE-NEXT: rldimi r3, r6, 32, 0
1102 ; P9BE-NEXT: rldimi r5, r4, 32, 0
1103 ; P9BE-NEXT: mtvsrdd v2, r5, r3
1104 ; P9BE-NEXT: blr
1105 ;
1106 ; P9LE-LABEL: fromRandMemConsi:
1107 ; P9LE: # %bb.0: # %entry
1108 ; P9LE-NEXT: lwz r4, 16(r3)
1109 ; P9LE-NEXT: lwz r5, 72(r3)
1110 ; P9LE-NEXT: lwz r6, 8(r3)
1111 ; P9LE-NEXT: lwz r3, 352(r3)
1112 ; P9LE-NEXT: rldimi r4, r5, 32, 0
1113 ; P9LE-NEXT: rldimi r6, r3, 32, 0
1114 ; P9LE-NEXT: mtvsrdd v2, r6, r4
1115 ; P9LE-NEXT: blr
1116 ;
1117 ; P8BE-LABEL: fromRandMemConsi:
1118 ; P8BE: # %bb.0: # %entry
1119 ; P8BE-NEXT: lwz r4, 16(r3)
1120 ; P8BE-NEXT: lwz r5, 72(r3)
1121 ; P8BE-NEXT: lwz r6, 8(r3)
1122 ; P8BE-NEXT: lwz r3, 352(r3)
1123 ; P8BE-NEXT: rldimi r3, r6, 32, 0
1124 ; P8BE-NEXT: rldimi r5, r4, 32, 0
1125 ; P8BE-NEXT: mtfprd f0, r3
1126 ; P8BE-NEXT: mtfprd f1, r5
1127 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
1128 ; P8BE-NEXT: blr
1129 ;
1130 ; P8LE-LABEL: fromRandMemConsi:
1131 ; P8LE: # %bb.0: # %entry
1132 ; P8LE-NEXT: lwz r4, 16(r3)
1133 ; P8LE-NEXT: lwz r5, 72(r3)
1134 ; P8LE-NEXT: lwz r6, 8(r3)
1135 ; P8LE-NEXT: lwz r3, 352(r3)
1136 ; P8LE-NEXT: rldimi r4, r5, 32, 0
1137 ; P8LE-NEXT: rldimi r6, r3, 32, 0
1138 ; P8LE-NEXT: mtfprd f0, r4
1139 ; P8LE-NEXT: mtfprd f1, r6
1140 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
1141 ; P8LE-NEXT: blr
1142 entry:
1143 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 4
1144 %0 = load i32, ptr %arrayidx, align 4
1145 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1146 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 18
1147 %1 = load i32, ptr %arrayidx1, align 4
1148 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1149 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2
1150 %2 = load i32, ptr %arrayidx3, align 4
1151 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
1152 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 88
1153 %3 = load i32, ptr %arrayidx5, align 4
1154 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
1155 ret <4 x i32> %vecinit6
1156 }
1158 define <4 x i32> @fromRandMemVari(ptr nocapture readonly %arr, i32 signext %elem) {
1159 ; P9BE-LABEL: fromRandMemVari:
1160 ; P9BE: # %bb.0: # %entry
1161 ; P9BE-NEXT: sldi r4, r4, 2
1162 ; P9BE-NEXT: add r3, r3, r4
1163 ; P9BE-NEXT: lwz r4, 16(r3)
1164 ; P9BE-NEXT: lwz r5, 4(r3)
1165 ; P9BE-NEXT: lwz r6, 8(r3)
1166 ; P9BE-NEXT: lwz r3, 32(r3)
1167 ; P9BE-NEXT: rldimi r3, r6, 32, 0
1168 ; P9BE-NEXT: rldimi r5, r4, 32, 0
1169 ; P9BE-NEXT: mtvsrdd v2, r5, r3
1170 ; P9BE-NEXT: blr
1171 ;
1172 ; P9LE-LABEL: fromRandMemVari:
1173 ; P9LE: # %bb.0: # %entry
1174 ; P9LE-NEXT: sldi r4, r4, 2
1175 ; P9LE-NEXT: add r3, r3, r4
1176 ; P9LE-NEXT: lwz r4, 16(r3)
1177 ; P9LE-NEXT: lwz r5, 4(r3)
1178 ; P9LE-NEXT: lwz r6, 8(r3)
1179 ; P9LE-NEXT: lwz r3, 32(r3)
1180 ; P9LE-NEXT: rldimi r4, r5, 32, 0
1181 ; P9LE-NEXT: rldimi r6, r3, 32, 0
1182 ; P9LE-NEXT: mtvsrdd v2, r6, r4
1183 ; P9LE-NEXT: blr
1184 ;
1185 ; P8BE-LABEL: fromRandMemVari:
1186 ; P8BE: # %bb.0: # %entry
1187 ; P8BE-NEXT: sldi r4, r4, 2
1188 ; P8BE-NEXT: add r3, r3, r4
1189 ; P8BE-NEXT: lwz r4, 16(r3)
1190 ; P8BE-NEXT: lwz r5, 4(r3)
1191 ; P8BE-NEXT: lwz r6, 8(r3)
1192 ; P8BE-NEXT: lwz r3, 32(r3)
1193 ; P8BE-NEXT: rldimi r3, r6, 32, 0
1194 ; P8BE-NEXT: rldimi r5, r4, 32, 0
1195 ; P8BE-NEXT: mtfprd f0, r3
1196 ; P8BE-NEXT: mtfprd f1, r5
1197 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
1198 ; P8BE-NEXT: blr
1199 ;
1200 ; P8LE-LABEL: fromRandMemVari:
1201 ; P8LE: # %bb.0: # %entry
1202 ; P8LE-NEXT: sldi r4, r4, 2
1203 ; P8LE-NEXT: add r3, r3, r4
1204 ; P8LE-NEXT: lwz r4, 16(r3)
1205 ; P8LE-NEXT: lwz r5, 4(r3)
1206 ; P8LE-NEXT: lwz r6, 8(r3)
1207 ; P8LE-NEXT: lwz r3, 32(r3)
1208 ; P8LE-NEXT: rldimi r4, r5, 32, 0
1209 ; P8LE-NEXT: rldimi r6, r3, 32, 0
1210 ; P8LE-NEXT: mtfprd f0, r4
1211 ; P8LE-NEXT: mtfprd f1, r6
1212 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
1213 ; P8LE-NEXT: blr
1214 entry:
1215 %add = add nsw i32 %elem, 4
1216 %idxprom = sext i32 %add to i64
1217 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
1218 %0 = load i32, ptr %arrayidx, align 4
1219 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
1220 %add1 = add nsw i32 %elem, 1
1221 %idxprom2 = sext i32 %add1 to i64
1222 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 %idxprom2
1223 %1 = load i32, ptr %arrayidx3, align 4
1224 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
1225 %add5 = add nsw i32 %elem, 2
1226 %idxprom6 = sext i32 %add5 to i64
1227 %arrayidx7 = getelementptr inbounds i32, ptr %arr, i64 %idxprom6
1228 %2 = load i32, ptr %arrayidx7, align 4
1229 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2
1230 %add9 = add nsw i32 %elem, 8
1231 %idxprom10 = sext i32 %add9 to i64
1232 %arrayidx11 = getelementptr inbounds i32, ptr %arr, i64 %idxprom10
1233 %3 = load i32, ptr %arrayidx11, align 4
1234 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3
1235 ret <4 x i32> %vecinit12
1236 }
1238 define <4 x i32> @spltRegVali(i32 signext %val) {
1239 ; P9BE-LABEL: spltRegVali:
1240 ; P9BE: # %bb.0: # %entry
1241 ; P9BE-NEXT: mtvsrws v2, r3
1242 ; P9BE-NEXT: blr
1243 ;
1244 ; P9LE-LABEL: spltRegVali:
1245 ; P9LE: # %bb.0: # %entry
1246 ; P9LE-NEXT: mtvsrws v2, r3
1247 ; P9LE-NEXT: blr
1248 ;
1249 ; P8BE-LABEL: spltRegVali:
1250 ; P8BE: # %bb.0: # %entry
1251 ; P8BE-NEXT: mtfprwz f0, r3
1252 ; P8BE-NEXT: xxspltw v2, vs0, 1
1253 ; P8BE-NEXT: blr
1254 ;
1255 ; P8LE-LABEL: spltRegVali:
1256 ; P8LE: # %bb.0: # %entry
1257 ; P8LE-NEXT: mtfprwz f0, r3
1258 ; P8LE-NEXT: xxspltw v2, vs0, 1
1259 ; P8LE-NEXT: blr
1260 entry:
1261 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0
1262 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1263 ret <4 x i32> %splat.splat
1264 }
1266 define <4 x i32> @spltMemVali(ptr nocapture readonly %ptr) {
1267 ; P9BE-LABEL: spltMemVali:
1268 ; P9BE: # %bb.0: # %entry
1269 ; P9BE-NEXT: lxvwsx v2, 0, r3
1270 ; P9BE-NEXT: blr
1271 ;
1272 ; P9LE-LABEL: spltMemVali:
1273 ; P9LE: # %bb.0: # %entry
1274 ; P9LE-NEXT: lxvwsx v2, 0, r3
1275 ; P9LE-NEXT: blr
1276 ;
1277 ; P8BE-LABEL: spltMemVali:
1278 ; P8BE: # %bb.0: # %entry
1279 ; P8BE-NEXT: lfiwzx f0, 0, r3
1280 ; P8BE-NEXT: xxspltw v2, vs0, 1
1281 ; P8BE-NEXT: blr
1282 ;
1283 ; P8LE-LABEL: spltMemVali:
1284 ; P8LE: # %bb.0: # %entry
1285 ; P8LE-NEXT: lfiwzx f0, 0, r3
1286 ; P8LE-NEXT: xxspltw v2, vs0, 1
1287 ; P8LE-NEXT: blr
1288 entry:
1289 %0 = load i32, ptr %ptr, align 4
1290 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
1291 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1292 ret <4 x i32> %splat.splat
1293 }
1295 define <4 x i32> @spltCnstConvftoi() {
1296 ; P9BE-LABEL: spltCnstConvftoi:
1297 ; P9BE: # %bb.0: # %entry
1298 ; P9BE-NEXT: vspltisw v2, 4
1299 ; P9BE-NEXT: blr
1300 ;
1301 ; P9LE-LABEL: spltCnstConvftoi:
1302 ; P9LE: # %bb.0: # %entry
1303 ; P9LE-NEXT: vspltisw v2, 4
1304 ; P9LE-NEXT: blr
1305 ;
1306 ; P8BE-LABEL: spltCnstConvftoi:
1307 ; P8BE: # %bb.0: # %entry
1308 ; P8BE-NEXT: vspltisw v2, 4
1309 ; P8BE-NEXT: blr
1310 ;
1311 ; P8LE-LABEL: spltCnstConvftoi:
1312 ; P8LE: # %bb.0: # %entry
1313 ; P8LE-NEXT: vspltisw v2, 4
1314 ; P8LE-NEXT: blr
1315 entry:
1316 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
1317 }
1319 define <4 x i32> @fromRegsConvftoi(float %a, float %b, float %c, float %d) {
1320 ; P9BE-LABEL: fromRegsConvftoi:
1321 ; P9BE: # %bb.0: # %entry
1322 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1323 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1324 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
1325 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1326 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1327 ; P9BE-NEXT: xvcvdpsxws v2, vs0
1328 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
1329 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1330 ; P9BE-NEXT: vmrgew v2, v3, v2
1331 ; P9BE-NEXT: blr
1332 ;
1333 ; P9LE-LABEL: fromRegsConvftoi:
1334 ; P9LE: # %bb.0: # %entry
1335 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1336 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1337 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
1338 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1339 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1340 ; P9LE-NEXT: xvcvdpsxws v2, vs0
1341 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
1342 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1343 ; P9LE-NEXT: vmrgew v2, v3, v2
1344 ; P9LE-NEXT: blr
1345 ;
1346 ; P8BE-LABEL: fromRegsConvftoi:
1347 ; P8BE: # %bb.0: # %entry
1348 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1349 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1350 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1351 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1352 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
1353 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
1354 ; P8BE-NEXT: xvcvdpsxws v2, vs0
1355 ; P8BE-NEXT: xvcvdpsxws v3, vs1
1356 ; P8BE-NEXT: vmrgew v2, v3, v2
1357 ; P8BE-NEXT: blr
1358 ;
1359 ; P8LE-LABEL: fromRegsConvftoi:
1360 ; P8LE: # %bb.0: # %entry
1361 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1362 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1363 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1364 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1365 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
1366 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
1367 ; P8LE-NEXT: xvcvdpsxws v2, vs0
1368 ; P8LE-NEXT: xvcvdpsxws v3, vs1
1369 ; P8LE-NEXT: vmrgew v2, v3, v2
1370 ; P8LE-NEXT: blr
1371 entry:
1372 %conv = fptosi float %a to i32
1373 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1374 %conv1 = fptosi float %b to i32
1375 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
1376 %conv3 = fptosi float %c to i32
1377 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
1378 %conv5 = fptosi float %d to i32
1379 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
1380 ret <4 x i32> %vecinit6
1381 }
1383 define <4 x i32> @fromDiffConstsConvftoi() {
1384 ; P9BE-LABEL: fromDiffConstsConvftoi:
1385 ; P9BE: # %bb.0: # %entry
1386 ; P9BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
1387 ; P9BE-NEXT: addi r3, r3, .LCPI16_0@toc@l
1388 ; P9BE-NEXT: lxv v2, 0(r3)
1389 ; P9BE-NEXT: blr
1390 ;
1391 ; P9LE-LABEL: fromDiffConstsConvftoi:
1392 ; P9LE: # %bb.0: # %entry
1393 ; P9LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
1394 ; P9LE-NEXT: addi r3, r3, .LCPI16_0@toc@l
1395 ; P9LE-NEXT: lxv v2, 0(r3)
1396 ; P9LE-NEXT: blr
1397 ;
1398 ; P8BE-LABEL: fromDiffConstsConvftoi:
1399 ; P8BE: # %bb.0: # %entry
1400 ; P8BE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
1401 ; P8BE-NEXT: addi r3, r3, .LCPI16_0@toc@l
1402 ; P8BE-NEXT: lxvw4x v2, 0, r3
1403 ; P8BE-NEXT: blr
1404 ;
1405 ; P8LE-LABEL: fromDiffConstsConvftoi:
1406 ; P8LE: # %bb.0: # %entry
1407 ; P8LE-NEXT: addis r3, r2, .LCPI16_0@toc@ha
1408 ; P8LE-NEXT: addi r3, r3, .LCPI16_0@toc@l
1409 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1410 ; P8LE-NEXT: xxswapd v2, vs0
1411 ; P8LE-NEXT: blr
1412 entry:
1413 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
1414 }
1416 define <4 x i32> @fromDiffMemConsAConvftoi(ptr nocapture readonly %ptr) {
1417 ; P9BE-LABEL: fromDiffMemConsAConvftoi:
1418 ; P9BE: # %bb.0: # %entry
1419 ; P9BE-NEXT: lxv vs0, 0(r3)
1420 ; P9BE-NEXT: xvcvspsxws v2, vs0
1421 ; P9BE-NEXT: blr
1422 ;
1423 ; P9LE-LABEL: fromDiffMemConsAConvftoi:
1424 ; P9LE: # %bb.0: # %entry
1425 ; P9LE-NEXT: lxv vs0, 0(r3)
1426 ; P9LE-NEXT: xvcvspsxws v2, vs0
1427 ; P9LE-NEXT: blr
1428 ;
1429 ; P8BE-LABEL: fromDiffMemConsAConvftoi:
1430 ; P8BE: # %bb.0: # %entry
1431 ; P8BE-NEXT: lxvw4x vs0, 0, r3
1432 ; P8BE-NEXT: xvcvspsxws v2, vs0
1433 ; P8BE-NEXT: blr
1434 ;
1435 ; P8LE-LABEL: fromDiffMemConsAConvftoi:
1436 ; P8LE: # %bb.0: # %entry
1437 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1438 ; P8LE-NEXT: xxswapd v2, vs0
1439 ; P8LE-NEXT: xvcvspsxws v2, v2
1440 ; P8LE-NEXT: blr
1441 entry:
1442 %0 = load <4 x float>, ptr %ptr, align 4
1443 %1 = fptosi <4 x float> %0 to <4 x i32>
1444 ret <4 x i32> %1
1445 }
1447 define <4 x i32> @fromDiffMemConsDConvftoi(ptr nocapture readonly %ptr) {
1448 ; P9BE-LABEL: fromDiffMemConsDConvftoi:
1449 ; P9BE: # %bb.0: # %entry
1450 ; P9BE-NEXT: lxv vs0, 0(r3)
1451 ; P9BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha
1452 ; P9BE-NEXT: addi r3, r3, .LCPI18_0@toc@l
1453 ; P9BE-NEXT: lxv vs1, 0(r3)
1454 ; P9BE-NEXT: xxperm vs0, vs0, vs1
1455 ; P9BE-NEXT: xvcvspsxws v2, vs0
1456 ; P9BE-NEXT: blr
1457 ;
1458 ; P9LE-LABEL: fromDiffMemConsDConvftoi:
1459 ; P9LE: # %bb.0: # %entry
1460 ; P9LE-NEXT: lxv vs0, 0(r3)
1461 ; P9LE-NEXT: addis r3, r2, .LCPI18_0@toc@ha
1462 ; P9LE-NEXT: addi r3, r3, .LCPI18_0@toc@l
1463 ; P9LE-NEXT: lxv vs1, 0(r3)
1464 ; P9LE-NEXT: xxperm vs0, vs0, vs1
1465 ; P9LE-NEXT: xvcvspsxws v2, vs0
1466 ; P9LE-NEXT: blr
1467 ;
1468 ; P8BE-LABEL: fromDiffMemConsDConvftoi:
1469 ; P8BE: # %bb.0: # %entry
1470 ; P8BE-NEXT: lxvw4x v2, 0, r3
1471 ; P8BE-NEXT: addis r3, r2, .LCPI18_0@toc@ha
1472 ; P8BE-NEXT: addi r3, r3, .LCPI18_0@toc@l
1473 ; P8BE-NEXT: lxvw4x v3, 0, r3
1474 ; P8BE-NEXT: vperm v2, v2, v2, v3
1475 ; P8BE-NEXT: xvcvspsxws v2, v2
1476 ; P8BE-NEXT: blr
1477 ;
1478 ; P8LE-LABEL: fromDiffMemConsDConvftoi:
1479 ; P8LE: # %bb.0: # %entry
1480 ; P8LE-NEXT: addis r4, r2, .LCPI18_0@toc@ha
1481 ; P8LE-NEXT: lxvd2x v3, 0, r3
1482 ; P8LE-NEXT: addi r4, r4, .LCPI18_0@toc@l
1483 ; P8LE-NEXT: lxvd2x vs0, 0, r4
1484 ; P8LE-NEXT: xxswapd v2, vs0
1485 ; P8LE-NEXT: vperm v2, v3, v3, v2
1486 ; P8LE-NEXT: xvcvspsxws v2, v2
1487 ; P8LE-NEXT: blr
1488 entry:
1489 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3
1490 %0 = load float, ptr %arrayidx, align 4
1491 %conv = fptosi float %0 to i32
1492 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1493 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2
1494 %1 = load float, ptr %arrayidx1, align 4
1495 %conv2 = fptosi float %1 to i32
1496 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
1497 %arrayidx4 = getelementptr inbounds float, ptr %ptr, i64 1
1498 %2 = load float, ptr %arrayidx4, align 4
1499 %conv5 = fptosi float %2 to i32
1500 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
1501 %3 = load float, ptr %ptr, align 4
1502 %conv8 = fptosi float %3 to i32
1503 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
1504 ret <4 x i32> %vecinit9
1505 }
1507 define <4 x i32> @fromDiffMemVarAConvftoi(ptr nocapture readonly %arr, i32 signext %elem) {
1508 ; P9BE-LABEL: fromDiffMemVarAConvftoi:
1509 ; P9BE: # %bb.0: # %entry
1510 ; P9BE-NEXT: sldi r4, r4, 2
1511 ; P9BE-NEXT: lfsux f0, r3, r4
1512 ; P9BE-NEXT: lfs f1, 12(r3)
1513 ; P9BE-NEXT: lfs f2, 4(r3)
1514 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
1515 ; P9BE-NEXT: xvcvdpsp v2, vs1
1516 ; P9BE-NEXT: lfs f1, 8(r3)
1517 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
1518 ; P9BE-NEXT: xvcvdpsp v3, vs0
1519 ; P9BE-NEXT: vmrgew v2, v3, v2
1520 ; P9BE-NEXT: xvcvspsxws v2, v2
1521 ; P9BE-NEXT: blr
1522 ;
1523 ; P9LE-LABEL: fromDiffMemVarAConvftoi:
1524 ; P9LE: # %bb.0: # %entry
1525 ; P9LE-NEXT: sldi r4, r4, 2
1526 ; P9LE-NEXT: lfsux f0, r3, r4
1527 ; P9LE-NEXT: lfs f1, 8(r3)
1528 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1529 ; P9LE-NEXT: lfs f1, 12(r3)
1530 ; P9LE-NEXT: xvcvdpsp v2, vs0
1531 ; P9LE-NEXT: lfs f0, 4(r3)
1532 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1533 ; P9LE-NEXT: xvcvdpsp v3, vs0
1534 ; P9LE-NEXT: vmrgew v2, v3, v2
1535 ; P9LE-NEXT: xvcvspsxws v2, v2
1536 ; P9LE-NEXT: blr
1537 ;
1538 ; P8BE-LABEL: fromDiffMemVarAConvftoi:
1539 ; P8BE: # %bb.0: # %entry
1540 ; P8BE-NEXT: sldi r4, r4, 2
1541 ; P8BE-NEXT: lfsux f0, r3, r4
1542 ; P8BE-NEXT: lfs f1, 12(r3)
1543 ; P8BE-NEXT: lfs f2, 4(r3)
1544 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
1545 ; P8BE-NEXT: lfs f2, 8(r3)
1546 ; P8BE-NEXT: xvcvdpsp v2, vs1
1547 ; P8BE-NEXT: xxmrghd vs0, vs0, vs2
1548 ; P8BE-NEXT: xvcvdpsp v3, vs0
1549 ; P8BE-NEXT: vmrgew v2, v3, v2
1550 ; P8BE-NEXT: xvcvspsxws v2, v2
1551 ; P8BE-NEXT: blr
1552 ;
1553 ; P8LE-LABEL: fromDiffMemVarAConvftoi:
1554 ; P8LE: # %bb.0: # %entry
1555 ; P8LE-NEXT: sldi r4, r4, 2
1556 ; P8LE-NEXT: lfsux f0, r3, r4
1557 ; P8LE-NEXT: lfs f1, 8(r3)
1558 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
1559 ; P8LE-NEXT: lfs f1, 4(r3)
1560 ; P8LE-NEXT: lfs f2, 12(r3)
1561 ; P8LE-NEXT: xvcvdpsp v2, vs0
1562 ; P8LE-NEXT: xxmrghd vs1, vs2, vs1
1563 ; P8LE-NEXT: xvcvdpsp v3, vs1
1564 ; P8LE-NEXT: vmrgew v2, v3, v2
1565 ; P8LE-NEXT: xvcvspsxws v2, v2
1566 ; P8LE-NEXT: blr
1567 entry:
1568 %idxprom = sext i32 %elem to i64
1569 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
1570 %0 = load float, ptr %arrayidx, align 4
1571 %conv = fptosi float %0 to i32
1572 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1573 %add = add nsw i32 %elem, 1
1574 %idxprom1 = sext i32 %add to i64
1575 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
1576 %1 = load float, ptr %arrayidx2, align 4
1577 %conv3 = fptosi float %1 to i32
1578 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
1579 %add5 = add nsw i32 %elem, 2
1580 %idxprom6 = sext i32 %add5 to i64
1581 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6
1582 %2 = load float, ptr %arrayidx7, align 4
1583 %conv8 = fptosi float %2 to i32
1584 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
1585 %add10 = add nsw i32 %elem, 3
1586 %idxprom11 = sext i32 %add10 to i64
1587 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11
1588 %3 = load float, ptr %arrayidx12, align 4
1589 %conv13 = fptosi float %3 to i32
1590 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
1591 ret <4 x i32> %vecinit14
1592 }
1594 define <4 x i32> @fromDiffMemVarDConvftoi(ptr nocapture readonly %arr, i32 signext %elem) {
1595 ; P9BE-LABEL: fromDiffMemVarDConvftoi:
1596 ; P9BE: # %bb.0: # %entry
1597 ; P9BE-NEXT: sldi r4, r4, 2
1598 ; P9BE-NEXT: lfsux f0, r3, r4
1599 ; P9BE-NEXT: lfs f1, -12(r3)
1600 ; P9BE-NEXT: lfs f2, -4(r3)
1601 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
1602 ; P9BE-NEXT: xvcvdpsp v2, vs1
1603 ; P9BE-NEXT: lfs f1, -8(r3)
1604 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
1605 ; P9BE-NEXT: xvcvdpsp v3, vs0
1606 ; P9BE-NEXT: vmrgew v2, v3, v2
1607 ; P9BE-NEXT: xvcvspsxws v2, v2
1608 ; P9BE-NEXT: blr
1609 ;
1610 ; P9LE-LABEL: fromDiffMemVarDConvftoi:
1611 ; P9LE: # %bb.0: # %entry
1612 ; P9LE-NEXT: sldi r4, r4, 2
1613 ; P9LE-NEXT: lfsux f0, r3, r4
1614 ; P9LE-NEXT: lfs f1, -8(r3)
1615 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1616 ; P9LE-NEXT: lfs f1, -12(r3)
1617 ; P9LE-NEXT: xvcvdpsp v2, vs0
1618 ; P9LE-NEXT: lfs f0, -4(r3)
1619 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1620 ; P9LE-NEXT: xvcvdpsp v3, vs0
1621 ; P9LE-NEXT: vmrgew v2, v3, v2
1622 ; P9LE-NEXT: xvcvspsxws v2, v2
1623 ; P9LE-NEXT: blr
1624 ;
1625 ; P8BE-LABEL: fromDiffMemVarDConvftoi:
1626 ; P8BE: # %bb.0: # %entry
1627 ; P8BE-NEXT: sldi r4, r4, 2
1628 ; P8BE-NEXT: lfsux f0, r3, r4
1629 ; P8BE-NEXT: lfs f1, -12(r3)
1630 ; P8BE-NEXT: lfs f2, -4(r3)
1631 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
1632 ; P8BE-NEXT: lfs f2, -8(r3)
1633 ; P8BE-NEXT: xvcvdpsp v2, vs1
1634 ; P8BE-NEXT: xxmrghd vs0, vs0, vs2
1635 ; P8BE-NEXT: xvcvdpsp v3, vs0
1636 ; P8BE-NEXT: vmrgew v2, v3, v2
1637 ; P8BE-NEXT: xvcvspsxws v2, v2
1638 ; P8BE-NEXT: blr
1639 ;
1640 ; P8LE-LABEL: fromDiffMemVarDConvftoi:
1641 ; P8LE: # %bb.0: # %entry
1642 ; P8LE-NEXT: sldi r4, r4, 2
1643 ; P8LE-NEXT: lfsux f0, r3, r4
1644 ; P8LE-NEXT: lfs f1, -8(r3)
1645 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
1646 ; P8LE-NEXT: lfs f1, -4(r3)
1647 ; P8LE-NEXT: lfs f2, -12(r3)
1648 ; P8LE-NEXT: xvcvdpsp v2, vs0
1649 ; P8LE-NEXT: xxmrghd vs1, vs2, vs1
1650 ; P8LE-NEXT: xvcvdpsp v3, vs1
1651 ; P8LE-NEXT: vmrgew v2, v3, v2
1652 ; P8LE-NEXT: xvcvspsxws v2, v2
1653 ; P8LE-NEXT: blr
1654 entry:
1655 %idxprom = sext i32 %elem to i64
1656 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
1657 %0 = load float, ptr %arrayidx, align 4
1658 %conv = fptosi float %0 to i32
1659 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1660 %sub = add nsw i32 %elem, -1
1661 %idxprom1 = sext i32 %sub to i64
1662 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
1663 %1 = load float, ptr %arrayidx2, align 4
1664 %conv3 = fptosi float %1 to i32
1665 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
1666 %sub5 = add nsw i32 %elem, -2
1667 %idxprom6 = sext i32 %sub5 to i64
1668 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6
1669 %2 = load float, ptr %arrayidx7, align 4
1670 %conv8 = fptosi float %2 to i32
1671 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
1672 %sub10 = add nsw i32 %elem, -3
1673 %idxprom11 = sext i32 %sub10 to i64
1674 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11
1675 %3 = load float, ptr %arrayidx12, align 4
1676 %conv13 = fptosi float %3 to i32
1677 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
1678 ret <4 x i32> %vecinit14
1679 ; FIXME: implement finding consecutive loads with pre-inc
1680 }
1682 define <4 x i32> @spltRegValConvftoi(float %val) {
1683 ; P9BE-LABEL: spltRegValConvftoi:
1684 ; P9BE: # %bb.0: # %entry
1685 ; P9BE-NEXT: xscvdpsxws f0, f1
1686 ; P9BE-NEXT: xxspltw v2, vs0, 1
1687 ; P9BE-NEXT: blr
1688 ;
1689 ; P9LE-LABEL: spltRegValConvftoi:
1690 ; P9LE: # %bb.0: # %entry
1691 ; P9LE-NEXT: xscvdpsxws f0, f1
1692 ; P9LE-NEXT: xxspltw v2, vs0, 1
1693 ; P9LE-NEXT: blr
1694 ;
1695 ; P8BE-LABEL: spltRegValConvftoi:
1696 ; P8BE: # %bb.0: # %entry
1697 ; P8BE-NEXT: xscvdpsxws f0, f1
1698 ; P8BE-NEXT: xxspltw v2, vs0, 1
1699 ; P8BE-NEXT: blr
1700 ;
1701 ; P8LE-LABEL: spltRegValConvftoi:
1702 ; P8LE: # %bb.0: # %entry
1703 ; P8LE-NEXT: xscvdpsxws f0, f1
1704 ; P8LE-NEXT: xxspltw v2, vs0, 1
1705 ; P8LE-NEXT: blr
1706 entry:
1707 %conv = fptosi float %val to i32
1708 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
1709 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1710 ret <4 x i32> %splat.splat
1711 }
1713 define <4 x i32> @spltMemValConvftoi(ptr nocapture readonly %ptr) {
1714 ; P9BE-LABEL: spltMemValConvftoi:
1715 ; P9BE: # %bb.0: # %entry
1716 ; P9BE-NEXT: lfiwzx f0, 0, r3
1717 ; P9BE-NEXT: xvcvspsxws vs0, vs0
1718 ; P9BE-NEXT: xxspltw v2, vs0, 1
1719 ; P9BE-NEXT: blr
1720 ;
1721 ; P9LE-LABEL: spltMemValConvftoi:
1722 ; P9LE: # %bb.0: # %entry
1723 ; P9LE-NEXT: lfiwzx f0, 0, r3
1724 ; P9LE-NEXT: xvcvspsxws vs0, vs0
1725 ; P9LE-NEXT: xxspltw v2, vs0, 1
1726 ; P9LE-NEXT: blr
1727 ;
1728 ; P8BE-LABEL: spltMemValConvftoi:
1729 ; P8BE: # %bb.0: # %entry
1730 ; P8BE-NEXT: lfsx f0, 0, r3
1731 ; P8BE-NEXT: xscvdpsxws f0, f0
1732 ; P8BE-NEXT: xxspltw v2, vs0, 1
1733 ; P8BE-NEXT: blr
1734 ;
1735 ; P8LE-LABEL: spltMemValConvftoi:
1736 ; P8LE: # %bb.0: # %entry
1737 ; P8LE-NEXT: lfsx f0, 0, r3
1738 ; P8LE-NEXT: xscvdpsxws f0, f0
1739 ; P8LE-NEXT: xxspltw v2, vs0, 1
1740 ; P8LE-NEXT: blr
1741 entry:
1742 %0 = load float, ptr %ptr, align 4
1743 %conv = fptosi float %0 to i32
1744 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
1745 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
1746 ret <4 x i32> %splat.splat
1747 }
1749 define <4 x i32> @spltCnstConvdtoi() {
1750 ; P9BE-LABEL: spltCnstConvdtoi:
1751 ; P9BE: # %bb.0: # %entry
1752 ; P9BE-NEXT: vspltisw v2, 4
1753 ; P9BE-NEXT: blr
1754 ;
1755 ; P9LE-LABEL: spltCnstConvdtoi:
1756 ; P9LE: # %bb.0: # %entry
1757 ; P9LE-NEXT: vspltisw v2, 4
1758 ; P9LE-NEXT: blr
1759 ;
1760 ; P8BE-LABEL: spltCnstConvdtoi:
1761 ; P8BE: # %bb.0: # %entry
1762 ; P8BE-NEXT: vspltisw v2, 4
1763 ; P8BE-NEXT: blr
1764 ;
1765 ; P8LE-LABEL: spltCnstConvdtoi:
1766 ; P8LE: # %bb.0: # %entry
1767 ; P8LE-NEXT: vspltisw v2, 4
1768 ; P8LE-NEXT: blr
1769 entry:
1770 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
1771 }
1773 define <4 x i32> @fromRegsConvdtoi(double %a, double %b, double %c, double %d) {
1774 ; P9BE-LABEL: fromRegsConvdtoi:
1775 ; P9BE: # %bb.0: # %entry
1776 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1777 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1778 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
1779 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1780 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1781 ; P9BE-NEXT: xvcvdpsxws v2, vs0
1782 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
1783 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1784 ; P9BE-NEXT: vmrgew v2, v3, v2
1785 ; P9BE-NEXT: blr
1786 ;
1787 ; P9LE-LABEL: fromRegsConvdtoi:
1788 ; P9LE: # %bb.0: # %entry
1789 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1790 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1791 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
1792 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1793 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1794 ; P9LE-NEXT: xvcvdpsxws v2, vs0
1795 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
1796 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1797 ; P9LE-NEXT: vmrgew v2, v3, v2
1798 ; P9LE-NEXT: blr
1799 ;
1800 ; P8BE-LABEL: fromRegsConvdtoi:
1801 ; P8BE: # %bb.0: # %entry
1802 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1803 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1804 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1805 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1806 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
1807 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
1808 ; P8BE-NEXT: xvcvdpsxws v2, vs0
1809 ; P8BE-NEXT: xvcvdpsxws v3, vs1
1810 ; P8BE-NEXT: vmrgew v2, v3, v2
1811 ; P8BE-NEXT: blr
1812 ;
1813 ; P8LE-LABEL: fromRegsConvdtoi:
1814 ; P8LE: # %bb.0: # %entry
1815 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
1816 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
1817 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
1818 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
1819 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
1820 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
1821 ; P8LE-NEXT: xvcvdpsxws v2, vs0
1822 ; P8LE-NEXT: xvcvdpsxws v3, vs1
1823 ; P8LE-NEXT: vmrgew v2, v3, v2
1824 ; P8LE-NEXT: blr
1825 entry:
1826 %conv = fptosi double %a to i32
1827 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1828 %conv1 = fptosi double %b to i32
1829 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
1830 %conv3 = fptosi double %c to i32
1831 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
1832 %conv5 = fptosi double %d to i32
1833 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
1834 ret <4 x i32> %vecinit6
1835 }
1837 define <4 x i32> @fromDiffConstsConvdtoi() {
1838 ; P9BE-LABEL: fromDiffConstsConvdtoi:
1839 ; P9BE: # %bb.0: # %entry
1840 ; P9BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
1841 ; P9BE-NEXT: addi r3, r3, .LCPI25_0@toc@l
1842 ; P9BE-NEXT: lxv v2, 0(r3)
1843 ; P9BE-NEXT: blr
1844 ;
1845 ; P9LE-LABEL: fromDiffConstsConvdtoi:
1846 ; P9LE: # %bb.0: # %entry
1847 ; P9LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
1848 ; P9LE-NEXT: addi r3, r3, .LCPI25_0@toc@l
1849 ; P9LE-NEXT: lxv v2, 0(r3)
1850 ; P9LE-NEXT: blr
1851 ;
1852 ; P8BE-LABEL: fromDiffConstsConvdtoi:
1853 ; P8BE: # %bb.0: # %entry
1854 ; P8BE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
1855 ; P8BE-NEXT: addi r3, r3, .LCPI25_0@toc@l
1856 ; P8BE-NEXT: lxvw4x v2, 0, r3
1857 ; P8BE-NEXT: blr
1858 ;
1859 ; P8LE-LABEL: fromDiffConstsConvdtoi:
1860 ; P8LE: # %bb.0: # %entry
1861 ; P8LE-NEXT: addis r3, r2, .LCPI25_0@toc@ha
1862 ; P8LE-NEXT: addi r3, r3, .LCPI25_0@toc@l
1863 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1864 ; P8LE-NEXT: xxswapd v2, vs0
1865 ; P8LE-NEXT: blr
1866 entry:
1867 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
1868 }
1870 define <4 x i32> @fromDiffMemConsAConvdtoi(ptr nocapture readonly %ptr) {
1871 ; P9BE-LABEL: fromDiffMemConsAConvdtoi:
1872 ; P9BE: # %bb.0: # %entry
1873 ; P9BE-NEXT: lxv vs0, 0(r3)
1874 ; P9BE-NEXT: lxv vs1, 16(r3)
1875 ; P9BE-NEXT: xxmrgld vs2, vs0, vs1
1876 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
1877 ; P9BE-NEXT: xvcvdpsxws v2, vs2
1878 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1879 ; P9BE-NEXT: vmrgew v2, v3, v2
1880 ; P9BE-NEXT: blr
1881 ;
1882 ; P9LE-LABEL: fromDiffMemConsAConvdtoi:
1883 ; P9LE: # %bb.0: # %entry
1884 ; P9LE-NEXT: lxv vs0, 0(r3)
1885 ; P9LE-NEXT: lxv vs1, 16(r3)
1886 ; P9LE-NEXT: xxmrgld vs2, vs1, vs0
1887 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
1888 ; P9LE-NEXT: xvcvdpsxws v2, vs2
1889 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1890 ; P9LE-NEXT: vmrgew v2, v3, v2
1891 ; P9LE-NEXT: blr
1892 ;
1893 ; P8BE-LABEL: fromDiffMemConsAConvdtoi:
1894 ; P8BE: # %bb.0: # %entry
1895 ; P8BE-NEXT: li r4, 16
1896 ; P8BE-NEXT: lxvd2x vs0, 0, r3
1897 ; P8BE-NEXT: lxvd2x vs1, r3, r4
1898 ; P8BE-NEXT: xxmrgld vs2, vs0, vs1
1899 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
1900 ; P8BE-NEXT: xvcvdpsxws v2, vs2
1901 ; P8BE-NEXT: xvcvdpsxws v3, vs0
1902 ; P8BE-NEXT: vmrgew v2, v3, v2
1903 ; P8BE-NEXT: blr
1904 ;
1905 ; P8LE-LABEL: fromDiffMemConsAConvdtoi:
1906 ; P8LE: # %bb.0: # %entry
1907 ; P8LE-NEXT: li r4, 16
1908 ; P8LE-NEXT: lxvd2x vs0, 0, r3
1909 ; P8LE-NEXT: lxvd2x vs1, r3, r4
1910 ; P8LE-NEXT: xxswapd vs0, vs0
1911 ; P8LE-NEXT: xxswapd vs1, vs1
1912 ; P8LE-NEXT: xxmrgld vs2, vs1, vs0
1913 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
1914 ; P8LE-NEXT: xvcvdpsxws v2, vs2
1915 ; P8LE-NEXT: xvcvdpsxws v3, vs0
1916 ; P8LE-NEXT: vmrgew v2, v3, v2
1917 ; P8LE-NEXT: blr
1918 entry:
1919 %0 = load <2 x double>, ptr %ptr, align 8
1920 %1 = fptosi <2 x double> %0 to <2 x i32>
1921 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 2
1922 %2 = load <2 x double>, ptr %arrayidx4, align 8
1923 %3 = fptosi <2 x double> %2 to <2 x i32>
1924 %vecinit9 = shufflevector <2 x i32> %1, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
1925 ret <4 x i32> %vecinit9
1926 }
1928 define <4 x i32> @fromDiffMemConsDConvdtoi(ptr nocapture readonly %ptr) {
1929 ; P9BE-LABEL: fromDiffMemConsDConvdtoi:
1930 ; P9BE: # %bb.0: # %entry
1931 ; P9BE-NEXT: lfd f0, 24(r3)
1932 ; P9BE-NEXT: lfd f1, 16(r3)
1933 ; P9BE-NEXT: lfd f2, 8(r3)
1934 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
1935 ; P9BE-NEXT: lfd f3, 0(r3)
1936 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
1937 ; P9BE-NEXT: xvcvdpsxws v2, vs1
1938 ; P9BE-NEXT: xvcvdpsxws v3, vs0
1939 ; P9BE-NEXT: vmrgew v2, v3, v2
1940 ; P9BE-NEXT: blr
1941 ;
1942 ; P9LE-LABEL: fromDiffMemConsDConvdtoi:
1943 ; P9LE: # %bb.0: # %entry
1944 ; P9LE-NEXT: lfd f0, 24(r3)
1945 ; P9LE-NEXT: lfd f2, 8(r3)
1946 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
1947 ; P9LE-NEXT: lfd f1, 16(r3)
1948 ; P9LE-NEXT: lfd f3, 0(r3)
1949 ; P9LE-NEXT: xvcvdpsxws v2, vs0
1950 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
1951 ; P9LE-NEXT: xvcvdpsxws v3, vs0
1952 ; P9LE-NEXT: vmrgew v2, v3, v2
1953 ; P9LE-NEXT: blr
1954 ;
1955 ; P8BE-LABEL: fromDiffMemConsDConvdtoi:
1956 ; P8BE: # %bb.0: # %entry
1957 ; P8BE-NEXT: lfd f0, 24(r3)
1958 ; P8BE-NEXT: lfd f1, 16(r3)
1959 ; P8BE-NEXT: lfd f2, 8(r3)
1960 ; P8BE-NEXT: lfd f3, 0(r3)
1961 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
1962 ; P8BE-NEXT: xxmrghd vs0, vs0, vs2
1963 ; P8BE-NEXT: xvcvdpsxws v2, vs1
1964 ; P8BE-NEXT: xvcvdpsxws v3, vs0
1965 ; P8BE-NEXT: vmrgew v2, v3, v2
1966 ; P8BE-NEXT: blr
1967 ;
1968 ; P8LE-LABEL: fromDiffMemConsDConvdtoi:
1969 ; P8LE: # %bb.0: # %entry
1970 ; P8LE-NEXT: lfd f0, 24(r3)
1971 ; P8LE-NEXT: lfd f1, 16(r3)
1972 ; P8LE-NEXT: lfd f2, 8(r3)
1973 ; P8LE-NEXT: lfd f3, 0(r3)
1974 ; P8LE-NEXT: xxmrghd vs0, vs2, vs0
1975 ; P8LE-NEXT: xxmrghd vs1, vs3, vs1
1976 ; P8LE-NEXT: xvcvdpsxws v2, vs0
1977 ; P8LE-NEXT: xvcvdpsxws v3, vs1
1978 ; P8LE-NEXT: vmrgew v2, v3, v2
1979 ; P8LE-NEXT: blr
1980 entry:
1981 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3
1982 %0 = load double, ptr %arrayidx, align 8
1983 %conv = fptosi double %0 to i32
1984 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
1985 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2
1986 %1 = load double, ptr %arrayidx1, align 8
1987 %conv2 = fptosi double %1 to i32
1988 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
1989 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 1
1990 %2 = load double, ptr %arrayidx4, align 8
1991 %conv5 = fptosi double %2 to i32
1992 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
1993 %3 = load double, ptr %ptr, align 8
1994 %conv8 = fptosi double %3 to i32
1995 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
1996 ret <4 x i32> %vecinit9
1997 }
1999 define <4 x i32> @fromDiffMemVarAConvdtoi(ptr nocapture readonly %arr, i32 signext %elem) {
2000 ; P9BE-LABEL: fromDiffMemVarAConvdtoi:
2001 ; P9BE: # %bb.0: # %entry
2002 ; P9BE-NEXT: sldi r4, r4, 3
2003 ; P9BE-NEXT: lfdux f0, r3, r4
2004 ; P9BE-NEXT: lfd f1, 8(r3)
2005 ; P9BE-NEXT: lfd f2, 16(r3)
2006 ; P9BE-NEXT: lfd f3, 24(r3)
2007 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
2008 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
2009 ; P9BE-NEXT: xvcvdpsxws v2, vs1
2010 ; P9BE-NEXT: xvcvdpsxws v3, vs0
2011 ; P9BE-NEXT: vmrgew v2, v3, v2
2012 ; P9BE-NEXT: blr
2013 ;
2014 ; P9LE-LABEL: fromDiffMemVarAConvdtoi:
2015 ; P9LE: # %bb.0: # %entry
2016 ; P9LE-NEXT: sldi r4, r4, 3
2017 ; P9LE-NEXT: lfdux f0, r3, r4
2018 ; P9LE-NEXT: lfd f2, 16(r3)
2019 ; P9LE-NEXT: lfd f1, 8(r3)
2020 ; P9LE-NEXT: lfd f3, 24(r3)
2021 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
2022 ; P9LE-NEXT: xvcvdpsxws v2, vs0
2023 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
2024 ; P9LE-NEXT: xvcvdpsxws v3, vs0
2025 ; P9LE-NEXT: vmrgew v2, v3, v2
2026 ; P9LE-NEXT: blr
2027 ;
2028 ; P8BE-LABEL: fromDiffMemVarAConvdtoi:
2029 ; P8BE: # %bb.0: # %entry
2030 ; P8BE-NEXT: sldi r4, r4, 3
2031 ; P8BE-NEXT: lfdux f0, r3, r4
2032 ; P8BE-NEXT: lfd f1, 8(r3)
2033 ; P8BE-NEXT: lfd f2, 16(r3)
2034 ; P8BE-NEXT: lfd f3, 24(r3)
2035 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
2036 ; P8BE-NEXT: xxmrghd vs0, vs0, vs2
2037 ; P8BE-NEXT: xvcvdpsxws v2, vs1
2038 ; P8BE-NEXT: xvcvdpsxws v3, vs0
2039 ; P8BE-NEXT: vmrgew v2, v3, v2
2040 ; P8BE-NEXT: blr
2041 ;
2042 ; P8LE-LABEL: fromDiffMemVarAConvdtoi:
2043 ; P8LE: # %bb.0: # %entry
2044 ; P8LE-NEXT: sldi r4, r4, 3
2045 ; P8LE-NEXT: lfdux f0, r3, r4
2046 ; P8LE-NEXT: lfd f1, 8(r3)
2047 ; P8LE-NEXT: lfd f2, 16(r3)
2048 ; P8LE-NEXT: lfd f3, 24(r3)
2049 ; P8LE-NEXT: xxmrghd vs0, vs2, vs0
2050 ; P8LE-NEXT: xxmrghd vs1, vs3, vs1
2051 ; P8LE-NEXT: xvcvdpsxws v2, vs0
2052 ; P8LE-NEXT: xvcvdpsxws v3, vs1
2053 ; P8LE-NEXT: vmrgew v2, v3, v2
2054 ; P8LE-NEXT: blr
2055 entry:
2056 %idxprom = sext i32 %elem to i64
2057 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
2058 %0 = load double, ptr %arrayidx, align 8
2059 %conv = fptosi double %0 to i32
2060 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2061 %add = add nsw i32 %elem, 1
2062 %idxprom1 = sext i32 %add to i64
2063 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
2064 %1 = load double, ptr %arrayidx2, align 8
2065 %conv3 = fptosi double %1 to i32
2066 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
2067 %add5 = add nsw i32 %elem, 2
2068 %idxprom6 = sext i32 %add5 to i64
2069 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6
2070 %2 = load double, ptr %arrayidx7, align 8
2071 %conv8 = fptosi double %2 to i32
2072 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
2073 %add10 = add nsw i32 %elem, 3
2074 %idxprom11 = sext i32 %add10 to i64
2075 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11
2076 %3 = load double, ptr %arrayidx12, align 8
2077 %conv13 = fptosi double %3 to i32
2078 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
2079 ret <4 x i32> %vecinit14
2080 }
2082 define <4 x i32> @fromDiffMemVarDConvdtoi(ptr nocapture readonly %arr, i32 signext %elem) {
2083 ; P9BE-LABEL: fromDiffMemVarDConvdtoi:
2084 ; P9BE: # %bb.0: # %entry
2085 ; P9BE-NEXT: sldi r4, r4, 3
2086 ; P9BE-NEXT: lfdux f0, r3, r4
2087 ; P9BE-NEXT: lfd f1, -8(r3)
2088 ; P9BE-NEXT: lfd f2, -16(r3)
2089 ; P9BE-NEXT: lfd f3, -24(r3)
2090 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
2091 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
2092 ; P9BE-NEXT: xvcvdpsxws v2, vs1
2093 ; P9BE-NEXT: xvcvdpsxws v3, vs0
2094 ; P9BE-NEXT: vmrgew v2, v3, v2
2095 ; P9BE-NEXT: blr
2096 ;
2097 ; P9LE-LABEL: fromDiffMemVarDConvdtoi:
2098 ; P9LE: # %bb.0: # %entry
2099 ; P9LE-NEXT: sldi r4, r4, 3
2100 ; P9LE-NEXT: lfdux f0, r3, r4
2101 ; P9LE-NEXT: lfd f2, -16(r3)
2102 ; P9LE-NEXT: lfd f1, -8(r3)
2103 ; P9LE-NEXT: lfd f3, -24(r3)
2104 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
2105 ; P9LE-NEXT: xvcvdpsxws v2, vs0
2106 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
2107 ; P9LE-NEXT: xvcvdpsxws v3, vs0
2108 ; P9LE-NEXT: vmrgew v2, v3, v2
2109 ; P9LE-NEXT: blr
2110 ;
2111 ; P8BE-LABEL: fromDiffMemVarDConvdtoi:
2112 ; P8BE: # %bb.0: # %entry
2113 ; P8BE-NEXT: sldi r4, r4, 3
2114 ; P8BE-NEXT: lfdux f0, r3, r4
2115 ; P8BE-NEXT: lfd f1, -8(r3)
2116 ; P8BE-NEXT: lfd f2, -16(r3)
2117 ; P8BE-NEXT: lfd f3, -24(r3)
2118 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
2119 ; P8BE-NEXT: xxmrghd vs0, vs0, vs2
2120 ; P8BE-NEXT: xvcvdpsxws v2, vs1
2121 ; P8BE-NEXT: xvcvdpsxws v3, vs0
2122 ; P8BE-NEXT: vmrgew v2, v3, v2
2123 ; P8BE-NEXT: blr
2124 ;
2125 ; P8LE-LABEL: fromDiffMemVarDConvdtoi:
2126 ; P8LE: # %bb.0: # %entry
2127 ; P8LE-NEXT: sldi r4, r4, 3
2128 ; P8LE-NEXT: lfdux f0, r3, r4
2129 ; P8LE-NEXT: lfd f1, -8(r3)
2130 ; P8LE-NEXT: lfd f2, -16(r3)
2131 ; P8LE-NEXT: lfd f3, -24(r3)
2132 ; P8LE-NEXT: xxmrghd vs0, vs2, vs0
2133 ; P8LE-NEXT: xxmrghd vs1, vs3, vs1
2134 ; P8LE-NEXT: xvcvdpsxws v2, vs0
2135 ; P8LE-NEXT: xvcvdpsxws v3, vs1
2136 ; P8LE-NEXT: vmrgew v2, v3, v2
2137 ; P8LE-NEXT: blr
2138 entry:
2139 %idxprom = sext i32 %elem to i64
2140 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
2141 %0 = load double, ptr %arrayidx, align 8
2142 %conv = fptosi double %0 to i32
2143 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2144 %sub = add nsw i32 %elem, -1
2145 %idxprom1 = sext i32 %sub to i64
2146 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
2147 %1 = load double, ptr %arrayidx2, align 8
2148 %conv3 = fptosi double %1 to i32
2149 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
2150 %sub5 = add nsw i32 %elem, -2
2151 %idxprom6 = sext i32 %sub5 to i64
2152 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6
2153 %2 = load double, ptr %arrayidx7, align 8
2154 %conv8 = fptosi double %2 to i32
2155 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
2156 %sub10 = add nsw i32 %elem, -3
2157 %idxprom11 = sext i32 %sub10 to i64
2158 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11
2159 %3 = load double, ptr %arrayidx12, align 8
2160 %conv13 = fptosi double %3 to i32
2161 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
2162 ret <4 x i32> %vecinit14
2163 }
2165 define <4 x i32> @spltRegValConvdtoi(double %val) {
2166 ; P9BE-LABEL: spltRegValConvdtoi:
2167 ; P9BE: # %bb.0: # %entry
2168 ; P9BE-NEXT: xscvdpsxws f0, f1
2169 ; P9BE-NEXT: xxspltw v2, vs0, 1
2170 ; P9BE-NEXT: blr
2171 ;
2172 ; P9LE-LABEL: spltRegValConvdtoi:
2173 ; P9LE: # %bb.0: # %entry
2174 ; P9LE-NEXT: xscvdpsxws f0, f1
2175 ; P9LE-NEXT: xxspltw v2, vs0, 1
2176 ; P9LE-NEXT: blr
2177 ;
2178 ; P8BE-LABEL: spltRegValConvdtoi:
2179 ; P8BE: # %bb.0: # %entry
2180 ; P8BE-NEXT: xscvdpsxws f0, f1
2181 ; P8BE-NEXT: xxspltw v2, vs0, 1
2182 ; P8BE-NEXT: blr
2183 ;
2184 ; P8LE-LABEL: spltRegValConvdtoi:
2185 ; P8LE: # %bb.0: # %entry
2186 ; P8LE-NEXT: xscvdpsxws f0, f1
2187 ; P8LE-NEXT: xxspltw v2, vs0, 1
2188 ; P8LE-NEXT: blr
2189 entry:
2190 %conv = fptosi double %val to i32
2191 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
2192 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2193 ret <4 x i32> %splat.splat
2194 }
2196 define <4 x i32> @spltMemValConvdtoi(ptr nocapture readonly %ptr) {
2197 ; P9BE-LABEL: spltMemValConvdtoi:
2198 ; P9BE: # %bb.0: # %entry
2199 ; P9BE-NEXT: lfd f0, 0(r3)
2200 ; P9BE-NEXT: xscvdpsxws f0, f0
2201 ; P9BE-NEXT: xxspltw v2, vs0, 1
2202 ; P9BE-NEXT: blr
2203 ;
2204 ; P9LE-LABEL: spltMemValConvdtoi:
2205 ; P9LE: # %bb.0: # %entry
2206 ; P9LE-NEXT: lfd f0, 0(r3)
2207 ; P9LE-NEXT: xscvdpsxws f0, f0
2208 ; P9LE-NEXT: xxspltw v2, vs0, 1
2209 ; P9LE-NEXT: blr
2210 ;
2211 ; P8BE-LABEL: spltMemValConvdtoi:
2212 ; P8BE: # %bb.0: # %entry
2213 ; P8BE-NEXT: lfdx f0, 0, r3
2214 ; P8BE-NEXT: xscvdpsxws f0, f0
2215 ; P8BE-NEXT: xxspltw v2, vs0, 1
2216 ; P8BE-NEXT: blr
2217 ;
2218 ; P8LE-LABEL: spltMemValConvdtoi:
2219 ; P8LE: # %bb.0: # %entry
2220 ; P8LE-NEXT: lfdx f0, 0, r3
2221 ; P8LE-NEXT: xscvdpsxws f0, f0
2222 ; P8LE-NEXT: xxspltw v2, vs0, 1
2223 ; P8LE-NEXT: blr
2224 entry:
2225 %0 = load double, ptr %ptr, align 8
2226 %conv = fptosi double %0 to i32
2227 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
2228 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2229 ret <4 x i32> %splat.splat
2230 }
2232 define <4 x i32> @allZeroui() {
2233 ; P9BE-LABEL: allZeroui:
2234 ; P9BE: # %bb.0: # %entry
2235 ; P9BE-NEXT: xxlxor v2, v2, v2
2236 ; P9BE-NEXT: blr
2237 ;
2238 ; P9LE-LABEL: allZeroui:
2239 ; P9LE: # %bb.0: # %entry
2240 ; P9LE-NEXT: xxlxor v2, v2, v2
2241 ; P9LE-NEXT: blr
2242 ;
2243 ; P8BE-LABEL: allZeroui:
2244 ; P8BE: # %bb.0: # %entry
2245 ; P8BE-NEXT: xxlxor v2, v2, v2
2246 ; P8BE-NEXT: blr
2247 ;
2248 ; P8LE-LABEL: allZeroui:
2249 ; P8LE: # %bb.0: # %entry
2250 ; P8LE-NEXT: xxlxor v2, v2, v2
2251 ; P8LE-NEXT: blr
2252 entry:
2253 ret <4 x i32> zeroinitializer
2254 }
2256 define <4 x i32> @spltConst1ui() {
2257 ; P9BE-LABEL: spltConst1ui:
2258 ; P9BE: # %bb.0: # %entry
2259 ; P9BE-NEXT: vspltisw v2, 1
2260 ; P9BE-NEXT: blr
2261 ;
2262 ; P9LE-LABEL: spltConst1ui:
2263 ; P9LE: # %bb.0: # %entry
2264 ; P9LE-NEXT: vspltisw v2, 1
2265 ; P9LE-NEXT: blr
2266 ;
2267 ; P8BE-LABEL: spltConst1ui:
2268 ; P8BE: # %bb.0: # %entry
2269 ; P8BE-NEXT: vspltisw v2, 1
2270 ; P8BE-NEXT: blr
2271 ;
2272 ; P8LE-LABEL: spltConst1ui:
2273 ; P8LE: # %bb.0: # %entry
2274 ; P8LE-NEXT: vspltisw v2, 1
2275 ; P8LE-NEXT: blr
2276 entry:
2277 ret <4 x i32> <i32 1, i32 1, i32 1, i32 1>
2278 }
2280 define <4 x i32> @spltConst16kui() {
2281 ; P9BE-LABEL: spltConst16kui:
2282 ; P9BE: # %bb.0: # %entry
2283 ; P9BE-NEXT: vspltisw v2, -15
2284 ; P9BE-NEXT: vsrw v2, v2, v2
2285 ; P9BE-NEXT: blr
2286 ;
2287 ; P9LE-LABEL: spltConst16kui:
2288 ; P9LE: # %bb.0: # %entry
2289 ; P9LE-NEXT: vspltisw v2, -15
2290 ; P9LE-NEXT: vsrw v2, v2, v2
2291 ; P9LE-NEXT: blr
2292 ;
2293 ; P8BE-LABEL: spltConst16kui:
2294 ; P8BE: # %bb.0: # %entry
2295 ; P8BE-NEXT: vspltisw v2, -15
2296 ; P8BE-NEXT: vsrw v2, v2, v2
2297 ; P8BE-NEXT: blr
2298 ;
2299 ; P8LE-LABEL: spltConst16kui:
2300 ; P8LE: # %bb.0: # %entry
2301 ; P8LE-NEXT: vspltisw v2, -15
2302 ; P8LE-NEXT: vsrw v2, v2, v2
2303 ; P8LE-NEXT: blr
2304 entry:
2305 ret <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
2306 }
2308 define <4 x i32> @spltConst32kui() {
2309 ; P9BE-LABEL: spltConst32kui:
2310 ; P9BE: # %bb.0: # %entry
2311 ; P9BE-NEXT: vspltisw v2, -16
2312 ; P9BE-NEXT: vsrw v2, v2, v2
2313 ; P9BE-NEXT: blr
2314 ;
2315 ; P9LE-LABEL: spltConst32kui:
2316 ; P9LE: # %bb.0: # %entry
2317 ; P9LE-NEXT: vspltisw v2, -16
2318 ; P9LE-NEXT: vsrw v2, v2, v2
2319 ; P9LE-NEXT: blr
2320 ;
2321 ; P8BE-LABEL: spltConst32kui:
2322 ; P8BE: # %bb.0: # %entry
2323 ; P8BE-NEXT: vspltisw v2, -16
2324 ; P8BE-NEXT: vsrw v2, v2, v2
2325 ; P8BE-NEXT: blr
2326 ;
2327 ; P8LE-LABEL: spltConst32kui:
2328 ; P8LE: # %bb.0: # %entry
2329 ; P8LE-NEXT: vspltisw v2, -16
2330 ; P8LE-NEXT: vsrw v2, v2, v2
2331 ; P8LE-NEXT: blr
2332 entry:
2333 ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
2334 }
2336 define <4 x i32> @fromRegsui(i32 zeroext %a, i32 zeroext %b, i32 zeroext %c, i32 zeroext %d) {
2337 ; P9BE-LABEL: fromRegsui:
2338 ; P9BE: # %bb.0: # %entry
2339 ; P9BE-NEXT: rldimi r6, r5, 32, 0
2340 ; P9BE-NEXT: rldimi r4, r3, 32, 0
2341 ; P9BE-NEXT: mtvsrdd v2, r4, r6
2342 ; P9BE-NEXT: blr
2343 ;
2344 ; P9LE-LABEL: fromRegsui:
2345 ; P9LE: # %bb.0: # %entry
2346 ; P9LE-NEXT: rldimi r3, r4, 32, 0
2347 ; P9LE-NEXT: rldimi r5, r6, 32, 0
2348 ; P9LE-NEXT: mtvsrdd v2, r5, r3
2349 ; P9LE-NEXT: blr
2350 ;
2351 ; P8BE-LABEL: fromRegsui:
2352 ; P8BE: # %bb.0: # %entry
2353 ; P8BE-NEXT: rldimi r6, r5, 32, 0
2354 ; P8BE-NEXT: rldimi r4, r3, 32, 0
2355 ; P8BE-NEXT: mtfprd f0, r6
2356 ; P8BE-NEXT: mtfprd f1, r4
2357 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
2358 ; P8BE-NEXT: blr
2359 ;
2360 ; P8LE-LABEL: fromRegsui:
2361 ; P8LE: # %bb.0: # %entry
2362 ; P8LE-NEXT: rldimi r3, r4, 32, 0
2363 ; P8LE-NEXT: rldimi r5, r6, 32, 0
2364 ; P8LE-NEXT: mtfprd f0, r3
2365 ; P8LE-NEXT: mtfprd f1, r5
2366 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
2367 ; P8LE-NEXT: blr
2368 entry:
2369 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
2370 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
2371 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
2372 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
2373 ret <4 x i32> %vecinit3
2374 }
2376 define <4 x i32> @fromDiffConstsui() {
2377 ; P9BE-LABEL: fromDiffConstsui:
2378 ; P9BE: # %bb.0: # %entry
2379 ; P9BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
2380 ; P9BE-NEXT: addi r3, r3, .LCPI37_0@toc@l
2381 ; P9BE-NEXT: lxv v2, 0(r3)
2382 ; P9BE-NEXT: blr
2383 ;
2384 ; P9LE-LABEL: fromDiffConstsui:
2385 ; P9LE: # %bb.0: # %entry
2386 ; P9LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
2387 ; P9LE-NEXT: addi r3, r3, .LCPI37_0@toc@l
2388 ; P9LE-NEXT: lxv v2, 0(r3)
2389 ; P9LE-NEXT: blr
2390 ;
2391 ; P8BE-LABEL: fromDiffConstsui:
2392 ; P8BE: # %bb.0: # %entry
2393 ; P8BE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
2394 ; P8BE-NEXT: addi r3, r3, .LCPI37_0@toc@l
2395 ; P8BE-NEXT: lxvw4x v2, 0, r3
2396 ; P8BE-NEXT: blr
2397 ;
2398 ; P8LE-LABEL: fromDiffConstsui:
2399 ; P8LE: # %bb.0: # %entry
2400 ; P8LE-NEXT: addis r3, r2, .LCPI37_0@toc@ha
2401 ; P8LE-NEXT: addi r3, r3, .LCPI37_0@toc@l
2402 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2403 ; P8LE-NEXT: xxswapd v2, vs0
2404 ; P8LE-NEXT: blr
2405 entry:
2406 ret <4 x i32> <i32 242, i32 -113, i32 889, i32 19>
2407 }
2409 define <4 x i32> @fromDiffMemConsAui(ptr nocapture readonly %arr) {
2410 ; P9BE-LABEL: fromDiffMemConsAui:
2411 ; P9BE: # %bb.0: # %entry
2412 ; P9BE-NEXT: lxv v2, 0(r3)
2413 ; P9BE-NEXT: blr
2414 ;
2415 ; P9LE-LABEL: fromDiffMemConsAui:
2416 ; P9LE: # %bb.0: # %entry
2417 ; P9LE-NEXT: lxv v2, 0(r3)
2418 ; P9LE-NEXT: blr
2419 ;
2420 ; P8BE-LABEL: fromDiffMemConsAui:
2421 ; P8BE: # %bb.0: # %entry
2422 ; P8BE-NEXT: lxvw4x v2, 0, r3
2423 ; P8BE-NEXT: blr
2424 ;
2425 ; P8LE-LABEL: fromDiffMemConsAui:
2426 ; P8LE: # %bb.0: # %entry
2427 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2428 ; P8LE-NEXT: xxswapd v2, vs0
2429 ; P8LE-NEXT: blr
2430 entry:
2431 %0 = load i32, ptr %arr, align 4
2432 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2433 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 1
2434 %1 = load i32, ptr %arrayidx1, align 4
2435 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2436 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2
2437 %2 = load i32, ptr %arrayidx3, align 4
2438 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2439 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 3
2440 %3 = load i32, ptr %arrayidx5, align 4
2441 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2442 ret <4 x i32> %vecinit6
2443 }
2445 define <4 x i32> @fromDiffMemConsDui(ptr nocapture readonly %arr) {
2446 ; P9BE-LABEL: fromDiffMemConsDui:
2447 ; P9BE: # %bb.0: # %entry
2448 ; P9BE-NEXT: lxv v2, 0(r3)
2449 ; P9BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha
2450 ; P9BE-NEXT: addi r3, r3, .LCPI39_0@toc@l
2451 ; P9BE-NEXT: lxv vs0, 0(r3)
2452 ; P9BE-NEXT: xxperm v2, v2, vs0
2453 ; P9BE-NEXT: blr
2454 ;
2455 ; P9LE-LABEL: fromDiffMemConsDui:
2456 ; P9LE: # %bb.0: # %entry
2457 ; P9LE-NEXT: lxvw4x v2, 0, r3
2458 ; P9LE-NEXT: blr
2459 ;
2460 ; P8BE-LABEL: fromDiffMemConsDui:
2461 ; P8BE: # %bb.0: # %entry
2462 ; P8BE-NEXT: lxvw4x v2, 0, r3
2463 ; P8BE-NEXT: addis r3, r2, .LCPI39_0@toc@ha
2464 ; P8BE-NEXT: addi r3, r3, .LCPI39_0@toc@l
2465 ; P8BE-NEXT: lxvw4x v3, 0, r3
2466 ; P8BE-NEXT: vperm v2, v2, v2, v3
2467 ; P8BE-NEXT: blr
2468 ;
2469 ; P8LE-LABEL: fromDiffMemConsDui:
2470 ; P8LE: # %bb.0: # %entry
2471 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2472 ; P8LE-NEXT: addis r3, r2, .LCPI39_0@toc@ha
2473 ; P8LE-NEXT: addi r3, r3, .LCPI39_0@toc@l
2474 ; P8LE-NEXT: xxswapd v2, vs0
2475 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2476 ; P8LE-NEXT: xxswapd v3, vs0
2477 ; P8LE-NEXT: vperm v2, v2, v2, v3
2478 ; P8LE-NEXT: blr
2479 entry:
2480 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 3
2481 %0 = load i32, ptr %arrayidx, align 4
2482 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2483 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 2
2484 %1 = load i32, ptr %arrayidx1, align 4
2485 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2486 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 1
2487 %2 = load i32, ptr %arrayidx3, align 4
2488 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2489 %3 = load i32, ptr %arr, align 4
2490 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2491 ret <4 x i32> %vecinit6
2492 }
2494 define <4 x i32> @fromDiffMemVarAui(ptr nocapture readonly %arr, i32 signext %elem) {
2495 ; P9BE-LABEL: fromDiffMemVarAui:
2496 ; P9BE: # %bb.0: # %entry
2497 ; P9BE-NEXT: sldi r4, r4, 2
2498 ; P9BE-NEXT: lxvx v2, r3, r4
2499 ; P9BE-NEXT: blr
2500 ;
2501 ; P9LE-LABEL: fromDiffMemVarAui:
2502 ; P9LE: # %bb.0: # %entry
2503 ; P9LE-NEXT: sldi r4, r4, 2
2504 ; P9LE-NEXT: lxvx v2, r3, r4
2505 ; P9LE-NEXT: blr
2506 ;
2507 ; P8BE-LABEL: fromDiffMemVarAui:
2508 ; P8BE: # %bb.0: # %entry
2509 ; P8BE-NEXT: sldi r4, r4, 2
2510 ; P8BE-NEXT: lxvw4x v2, r3, r4
2511 ; P8BE-NEXT: blr
2512 ;
2513 ; P8LE-LABEL: fromDiffMemVarAui:
2514 ; P8LE: # %bb.0: # %entry
2515 ; P8LE-NEXT: sldi r4, r4, 2
2516 ; P8LE-NEXT: lxvd2x vs0, r3, r4
2517 ; P8LE-NEXT: xxswapd v2, vs0
2518 ; P8LE-NEXT: blr
2519 entry:
2520 %idxprom = sext i32 %elem to i64
2521 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
2522 %0 = load i32, ptr %arrayidx, align 4
2523 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2524 %add = add nsw i32 %elem, 1
2525 %idxprom1 = sext i32 %add to i64
2526 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1
2527 %1 = load i32, ptr %arrayidx2, align 4
2528 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2529 %add4 = add nsw i32 %elem, 2
2530 %idxprom5 = sext i32 %add4 to i64
2531 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5
2532 %2 = load i32, ptr %arrayidx6, align 4
2533 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
2534 %add8 = add nsw i32 %elem, 3
2535 %idxprom9 = sext i32 %add8 to i64
2536 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9
2537 %3 = load i32, ptr %arrayidx10, align 4
2538 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
2539 ret <4 x i32> %vecinit11
2540 }
2542 define <4 x i32> @fromDiffMemVarDui(ptr nocapture readonly %arr, i32 signext %elem) {
2543 ; P9BE-LABEL: fromDiffMemVarDui:
2544 ; P9BE: # %bb.0: # %entry
2545 ; P9BE-NEXT: sldi r4, r4, 2
2546 ; P9BE-NEXT: add r3, r3, r4
2547 ; P9BE-NEXT: li r4, -12
2548 ; P9BE-NEXT: lxvx v2, r3, r4
2549 ; P9BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
2550 ; P9BE-NEXT: addi r3, r3, .LCPI41_0@toc@l
2551 ; P9BE-NEXT: lxv vs0, 0(r3)
2552 ; P9BE-NEXT: xxperm v2, v2, vs0
2553 ; P9BE-NEXT: blr
2554 ;
2555 ; P9LE-LABEL: fromDiffMemVarDui:
2556 ; P9LE: # %bb.0: # %entry
2557 ; P9LE-NEXT: sldi r4, r4, 2
2558 ; P9LE-NEXT: add r3, r3, r4
2559 ; P9LE-NEXT: li r4, -12
2560 ; P9LE-NEXT: lxvx v2, r3, r4
2561 ; P9LE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
2562 ; P9LE-NEXT: addi r3, r3, .LCPI41_0@toc@l
2563 ; P9LE-NEXT: lxv vs0, 0(r3)
2564 ; P9LE-NEXT: xxperm v2, v2, vs0
2565 ; P9LE-NEXT: blr
2566 ;
2567 ; P8BE-LABEL: fromDiffMemVarDui:
2568 ; P8BE: # %bb.0: # %entry
2569 ; P8BE-NEXT: sldi r4, r4, 2
2570 ; P8BE-NEXT: add r3, r3, r4
2571 ; P8BE-NEXT: addi r3, r3, -12
2572 ; P8BE-NEXT: lxvw4x v2, 0, r3
2573 ; P8BE-NEXT: addis r3, r2, .LCPI41_0@toc@ha
2574 ; P8BE-NEXT: addi r3, r3, .LCPI41_0@toc@l
2575 ; P8BE-NEXT: lxvw4x v3, 0, r3
2576 ; P8BE-NEXT: vperm v2, v2, v2, v3
2577 ; P8BE-NEXT: blr
2578 ;
2579 ; P8LE-LABEL: fromDiffMemVarDui:
2580 ; P8LE: # %bb.0: # %entry
2581 ; P8LE-NEXT: addis r5, r2, .LCPI41_0@toc@ha
2582 ; P8LE-NEXT: sldi r4, r4, 2
2583 ; P8LE-NEXT: addi r5, r5, .LCPI41_0@toc@l
2584 ; P8LE-NEXT: add r3, r3, r4
2585 ; P8LE-NEXT: lxvd2x vs0, 0, r5
2586 ; P8LE-NEXT: addi r3, r3, -12
2587 ; P8LE-NEXT: lxvd2x v3, 0, r3
2588 ; P8LE-NEXT: xxswapd v2, vs0
2589 ; P8LE-NEXT: vperm v2, v3, v3, v2
2590 ; P8LE-NEXT: blr
2591 entry:
2592 %idxprom = sext i32 %elem to i64
2593 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
2594 %0 = load i32, ptr %arrayidx, align 4
2595 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2596 %sub = add nsw i32 %elem, -1
2597 %idxprom1 = sext i32 %sub to i64
2598 %arrayidx2 = getelementptr inbounds i32, ptr %arr, i64 %idxprom1
2599 %1 = load i32, ptr %arrayidx2, align 4
2600 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2601 %sub4 = add nsw i32 %elem, -2
2602 %idxprom5 = sext i32 %sub4 to i64
2603 %arrayidx6 = getelementptr inbounds i32, ptr %arr, i64 %idxprom5
2604 %2 = load i32, ptr %arrayidx6, align 4
2605 %vecinit7 = insertelement <4 x i32> %vecinit3, i32 %2, i32 2
2606 %sub8 = add nsw i32 %elem, -3
2607 %idxprom9 = sext i32 %sub8 to i64
2608 %arrayidx10 = getelementptr inbounds i32, ptr %arr, i64 %idxprom9
2609 %3 = load i32, ptr %arrayidx10, align 4
2610 %vecinit11 = insertelement <4 x i32> %vecinit7, i32 %3, i32 3
2611 ret <4 x i32> %vecinit11
2612 }
2614 define <4 x i32> @fromRandMemConsui(ptr nocapture readonly %arr) {
2615 ; P9BE-LABEL: fromRandMemConsui:
2616 ; P9BE: # %bb.0: # %entry
2617 ; P9BE-NEXT: lwz r4, 16(r3)
2618 ; P9BE-NEXT: lwz r5, 72(r3)
2619 ; P9BE-NEXT: lwz r6, 8(r3)
2620 ; P9BE-NEXT: lwz r3, 352(r3)
2621 ; P9BE-NEXT: rldimi r3, r6, 32, 0
2622 ; P9BE-NEXT: rldimi r5, r4, 32, 0
2623 ; P9BE-NEXT: mtvsrdd v2, r5, r3
2624 ; P9BE-NEXT: blr
2625 ;
2626 ; P9LE-LABEL: fromRandMemConsui:
2627 ; P9LE: # %bb.0: # %entry
2628 ; P9LE-NEXT: lwz r4, 16(r3)
2629 ; P9LE-NEXT: lwz r5, 72(r3)
2630 ; P9LE-NEXT: lwz r6, 8(r3)
2631 ; P9LE-NEXT: lwz r3, 352(r3)
2632 ; P9LE-NEXT: rldimi r4, r5, 32, 0
2633 ; P9LE-NEXT: rldimi r6, r3, 32, 0
2634 ; P9LE-NEXT: mtvsrdd v2, r6, r4
2635 ; P9LE-NEXT: blr
2636 ;
2637 ; P8BE-LABEL: fromRandMemConsui:
2638 ; P8BE: # %bb.0: # %entry
2639 ; P8BE-NEXT: lwz r4, 16(r3)
2640 ; P8BE-NEXT: lwz r5, 72(r3)
2641 ; P8BE-NEXT: lwz r6, 8(r3)
2642 ; P8BE-NEXT: lwz r3, 352(r3)
2643 ; P8BE-NEXT: rldimi r3, r6, 32, 0
2644 ; P8BE-NEXT: rldimi r5, r4, 32, 0
2645 ; P8BE-NEXT: mtfprd f0, r3
2646 ; P8BE-NEXT: mtfprd f1, r5
2647 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
2648 ; P8BE-NEXT: blr
2649 ;
2650 ; P8LE-LABEL: fromRandMemConsui:
2651 ; P8LE: # %bb.0: # %entry
2652 ; P8LE-NEXT: lwz r4, 16(r3)
2653 ; P8LE-NEXT: lwz r5, 72(r3)
2654 ; P8LE-NEXT: lwz r6, 8(r3)
2655 ; P8LE-NEXT: lwz r3, 352(r3)
2656 ; P8LE-NEXT: rldimi r4, r5, 32, 0
2657 ; P8LE-NEXT: rldimi r6, r3, 32, 0
2658 ; P8LE-NEXT: mtfprd f0, r4
2659 ; P8LE-NEXT: mtfprd f1, r6
2660 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
2661 ; P8LE-NEXT: blr
2662 entry:
2663 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 4
2664 %0 = load i32, ptr %arrayidx, align 4
2665 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2666 %arrayidx1 = getelementptr inbounds i32, ptr %arr, i64 18
2667 %1 = load i32, ptr %arrayidx1, align 4
2668 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2669 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 2
2670 %2 = load i32, ptr %arrayidx3, align 4
2671 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %2, i32 2
2672 %arrayidx5 = getelementptr inbounds i32, ptr %arr, i64 88
2673 %3 = load i32, ptr %arrayidx5, align 4
2674 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %3, i32 3
2675 ret <4 x i32> %vecinit6
2676 }
2678 define <4 x i32> @fromRandMemVarui(ptr nocapture readonly %arr, i32 signext %elem) {
2679 ; P9BE-LABEL: fromRandMemVarui:
2680 ; P9BE: # %bb.0: # %entry
2681 ; P9BE-NEXT: sldi r4, r4, 2
2682 ; P9BE-NEXT: add r3, r3, r4
2683 ; P9BE-NEXT: lwz r4, 16(r3)
2684 ; P9BE-NEXT: lwz r5, 4(r3)
2685 ; P9BE-NEXT: lwz r6, 8(r3)
2686 ; P9BE-NEXT: lwz r3, 32(r3)
2687 ; P9BE-NEXT: rldimi r3, r6, 32, 0
2688 ; P9BE-NEXT: rldimi r5, r4, 32, 0
2689 ; P9BE-NEXT: mtvsrdd v2, r5, r3
2690 ; P9BE-NEXT: blr
2691 ;
2692 ; P9LE-LABEL: fromRandMemVarui:
2693 ; P9LE: # %bb.0: # %entry
2694 ; P9LE-NEXT: sldi r4, r4, 2
2695 ; P9LE-NEXT: add r3, r3, r4
2696 ; P9LE-NEXT: lwz r4, 16(r3)
2697 ; P9LE-NEXT: lwz r5, 4(r3)
2698 ; P9LE-NEXT: lwz r6, 8(r3)
2699 ; P9LE-NEXT: lwz r3, 32(r3)
2700 ; P9LE-NEXT: rldimi r4, r5, 32, 0
2701 ; P9LE-NEXT: rldimi r6, r3, 32, 0
2702 ; P9LE-NEXT: mtvsrdd v2, r6, r4
2703 ; P9LE-NEXT: blr
2704 ;
2705 ; P8BE-LABEL: fromRandMemVarui:
2706 ; P8BE: # %bb.0: # %entry
2707 ; P8BE-NEXT: sldi r4, r4, 2
2708 ; P8BE-NEXT: add r3, r3, r4
2709 ; P8BE-NEXT: lwz r4, 16(r3)
2710 ; P8BE-NEXT: lwz r5, 4(r3)
2711 ; P8BE-NEXT: lwz r6, 8(r3)
2712 ; P8BE-NEXT: lwz r3, 32(r3)
2713 ; P8BE-NEXT: rldimi r3, r6, 32, 0
2714 ; P8BE-NEXT: rldimi r5, r4, 32, 0
2715 ; P8BE-NEXT: mtfprd f0, r3
2716 ; P8BE-NEXT: mtfprd f1, r5
2717 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
2718 ; P8BE-NEXT: blr
2719 ;
2720 ; P8LE-LABEL: fromRandMemVarui:
2721 ; P8LE: # %bb.0: # %entry
2722 ; P8LE-NEXT: sldi r4, r4, 2
2723 ; P8LE-NEXT: add r3, r3, r4
2724 ; P8LE-NEXT: lwz r4, 16(r3)
2725 ; P8LE-NEXT: lwz r5, 4(r3)
2726 ; P8LE-NEXT: lwz r6, 8(r3)
2727 ; P8LE-NEXT: lwz r3, 32(r3)
2728 ; P8LE-NEXT: rldimi r4, r5, 32, 0
2729 ; P8LE-NEXT: rldimi r6, r3, 32, 0
2730 ; P8LE-NEXT: mtfprd f0, r4
2731 ; P8LE-NEXT: mtfprd f1, r6
2732 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
2733 ; P8LE-NEXT: blr
2734 entry:
2735 %add = add nsw i32 %elem, 4
2736 %idxprom = sext i32 %add to i64
2737 %arrayidx = getelementptr inbounds i32, ptr %arr, i64 %idxprom
2738 %0 = load i32, ptr %arrayidx, align 4
2739 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
2740 %add1 = add nsw i32 %elem, 1
2741 %idxprom2 = sext i32 %add1 to i64
2742 %arrayidx3 = getelementptr inbounds i32, ptr %arr, i64 %idxprom2
2743 %1 = load i32, ptr %arrayidx3, align 4
2744 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %1, i32 1
2745 %add5 = add nsw i32 %elem, 2
2746 %idxprom6 = sext i32 %add5 to i64
2747 %arrayidx7 = getelementptr inbounds i32, ptr %arr, i64 %idxprom6
2748 %2 = load i32, ptr %arrayidx7, align 4
2749 %vecinit8 = insertelement <4 x i32> %vecinit4, i32 %2, i32 2
2750 %add9 = add nsw i32 %elem, 8
2751 %idxprom10 = sext i32 %add9 to i64
2752 %arrayidx11 = getelementptr inbounds i32, ptr %arr, i64 %idxprom10
2753 %3 = load i32, ptr %arrayidx11, align 4
2754 %vecinit12 = insertelement <4 x i32> %vecinit8, i32 %3, i32 3
2755 ret <4 x i32> %vecinit12
2756 }
2758 define <4 x i32> @spltRegValui(i32 zeroext %val) {
2759 ; P9BE-LABEL: spltRegValui:
2760 ; P9BE: # %bb.0: # %entry
2761 ; P9BE-NEXT: mtvsrws v2, r3
2762 ; P9BE-NEXT: blr
2763 ;
2764 ; P9LE-LABEL: spltRegValui:
2765 ; P9LE: # %bb.0: # %entry
2766 ; P9LE-NEXT: mtvsrws v2, r3
2767 ; P9LE-NEXT: blr
2768 ;
2769 ; P8BE-LABEL: spltRegValui:
2770 ; P8BE: # %bb.0: # %entry
2771 ; P8BE-NEXT: mtfprwz f0, r3
2772 ; P8BE-NEXT: xxspltw v2, vs0, 1
2773 ; P8BE-NEXT: blr
2774 ;
2775 ; P8LE-LABEL: spltRegValui:
2776 ; P8LE: # %bb.0: # %entry
2777 ; P8LE-NEXT: mtfprwz f0, r3
2778 ; P8LE-NEXT: xxspltw v2, vs0, 1
2779 ; P8LE-NEXT: blr
2780 entry:
2781 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0
2782 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2783 ret <4 x i32> %splat.splat
2784 }
2786 define <4 x i32> @spltMemValui(ptr nocapture readonly %ptr) {
2787 ; P9BE-LABEL: spltMemValui:
2788 ; P9BE: # %bb.0: # %entry
2789 ; P9BE-NEXT: lxvwsx v2, 0, r3
2790 ; P9BE-NEXT: blr
2791 ;
2792 ; P9LE-LABEL: spltMemValui:
2793 ; P9LE: # %bb.0: # %entry
2794 ; P9LE-NEXT: lxvwsx v2, 0, r3
2795 ; P9LE-NEXT: blr
2796 ;
2797 ; P8BE-LABEL: spltMemValui:
2798 ; P8BE: # %bb.0: # %entry
2799 ; P8BE-NEXT: lfiwzx f0, 0, r3
2800 ; P8BE-NEXT: xxspltw v2, vs0, 1
2801 ; P8BE-NEXT: blr
2802 ;
2803 ; P8LE-LABEL: spltMemValui:
2804 ; P8LE: # %bb.0: # %entry
2805 ; P8LE-NEXT: lfiwzx f0, 0, r3
2806 ; P8LE-NEXT: xxspltw v2, vs0, 1
2807 ; P8LE-NEXT: blr
2808 entry:
2809 %0 = load i32, ptr %ptr, align 4
2810 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
2811 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
2812 ret <4 x i32> %splat.splat
2813 }
2815 define <4 x i32> @spltCnstConvftoui() {
2816 ; P9BE-LABEL: spltCnstConvftoui:
2817 ; P9BE: # %bb.0: # %entry
2818 ; P9BE-NEXT: vspltisw v2, 4
2819 ; P9BE-NEXT: blr
2820 ;
2821 ; P9LE-LABEL: spltCnstConvftoui:
2822 ; P9LE: # %bb.0: # %entry
2823 ; P9LE-NEXT: vspltisw v2, 4
2824 ; P9LE-NEXT: blr
2825 ;
2826 ; P8BE-LABEL: spltCnstConvftoui:
2827 ; P8BE: # %bb.0: # %entry
2828 ; P8BE-NEXT: vspltisw v2, 4
2829 ; P8BE-NEXT: blr
2830 ;
2831 ; P8LE-LABEL: spltCnstConvftoui:
2832 ; P8LE: # %bb.0: # %entry
2833 ; P8LE-NEXT: vspltisw v2, 4
2834 ; P8LE-NEXT: blr
2835 entry:
2836 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
2837 }
2839 define <4 x i32> @fromRegsConvftoui(float %a, float %b, float %c, float %d) {
2840 ; P9BE-LABEL: fromRegsConvftoui:
2841 ; P9BE: # %bb.0: # %entry
2842 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
2843 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
2844 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
2845 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
2846 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
2847 ; P9BE-NEXT: xvcvdpuxws v2, vs0
2848 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
2849 ; P9BE-NEXT: xvcvdpuxws v3, vs0
2850 ; P9BE-NEXT: vmrgew v2, v3, v2
2851 ; P9BE-NEXT: blr
2852 ;
2853 ; P9LE-LABEL: fromRegsConvftoui:
2854 ; P9LE: # %bb.0: # %entry
2855 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
2856 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
2857 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
2858 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
2859 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
2860 ; P9LE-NEXT: xvcvdpuxws v2, vs0
2861 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
2862 ; P9LE-NEXT: xvcvdpuxws v3, vs0
2863 ; P9LE-NEXT: vmrgew v2, v3, v2
2864 ; P9LE-NEXT: blr
2865 ;
2866 ; P8BE-LABEL: fromRegsConvftoui:
2867 ; P8BE: # %bb.0: # %entry
2868 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
2869 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
2870 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
2871 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
2872 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
2873 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
2874 ; P8BE-NEXT: xvcvdpuxws v2, vs0
2875 ; P8BE-NEXT: xvcvdpuxws v3, vs1
2876 ; P8BE-NEXT: vmrgew v2, v3, v2
2877 ; P8BE-NEXT: blr
2878 ;
2879 ; P8LE-LABEL: fromRegsConvftoui:
2880 ; P8LE: # %bb.0: # %entry
2881 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
2882 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
2883 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
2884 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
2885 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
2886 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
2887 ; P8LE-NEXT: xvcvdpuxws v2, vs0
2888 ; P8LE-NEXT: xvcvdpuxws v3, vs1
2889 ; P8LE-NEXT: vmrgew v2, v3, v2
2890 ; P8LE-NEXT: blr
2891 entry:
2892 %conv = fptoui float %a to i32
2893 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
2894 %conv1 = fptoui float %b to i32
2895 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
2896 %conv3 = fptoui float %c to i32
2897 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
2898 %conv5 = fptoui float %d to i32
2899 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
2900 ret <4 x i32> %vecinit6
2901 }
2903 define <4 x i32> @fromDiffConstsConvftoui() {
2904 ; P9BE-LABEL: fromDiffConstsConvftoui:
2905 ; P9BE: # %bb.0: # %entry
2906 ; P9BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
2907 ; P9BE-NEXT: addi r3, r3, .LCPI48_0@toc@l
2908 ; P9BE-NEXT: lxv v2, 0(r3)
2909 ; P9BE-NEXT: blr
2910 ;
2911 ; P9LE-LABEL: fromDiffConstsConvftoui:
2912 ; P9LE: # %bb.0: # %entry
2913 ; P9LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
2914 ; P9LE-NEXT: addi r3, r3, .LCPI48_0@toc@l
2915 ; P9LE-NEXT: lxv v2, 0(r3)
2916 ; P9LE-NEXT: blr
2917 ;
2918 ; P8BE-LABEL: fromDiffConstsConvftoui:
2919 ; P8BE: # %bb.0: # %entry
2920 ; P8BE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
2921 ; P8BE-NEXT: addi r3, r3, .LCPI48_0@toc@l
2922 ; P8BE-NEXT: lxvw4x v2, 0, r3
2923 ; P8BE-NEXT: blr
2924 ;
2925 ; P8LE-LABEL: fromDiffConstsConvftoui:
2926 ; P8LE: # %bb.0: # %entry
2927 ; P8LE-NEXT: addis r3, r2, .LCPI48_0@toc@ha
2928 ; P8LE-NEXT: addi r3, r3, .LCPI48_0@toc@l
2929 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2930 ; P8LE-NEXT: xxswapd v2, vs0
2931 ; P8LE-NEXT: blr
2932 entry:
2933 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
2934 }
2936 define <4 x i32> @fromDiffMemConsAConvftoui(ptr nocapture readonly %ptr) {
2937 ; P9BE-LABEL: fromDiffMemConsAConvftoui:
2938 ; P9BE: # %bb.0: # %entry
2939 ; P9BE-NEXT: lxv vs0, 0(r3)
2940 ; P9BE-NEXT: xvcvspuxws v2, vs0
2941 ; P9BE-NEXT: blr
2942 ;
2943 ; P9LE-LABEL: fromDiffMemConsAConvftoui:
2944 ; P9LE: # %bb.0: # %entry
2945 ; P9LE-NEXT: lxv vs0, 0(r3)
2946 ; P9LE-NEXT: xvcvspuxws v2, vs0
2947 ; P9LE-NEXT: blr
2948 ;
2949 ; P8BE-LABEL: fromDiffMemConsAConvftoui:
2950 ; P8BE: # %bb.0: # %entry
2951 ; P8BE-NEXT: lxvw4x vs0, 0, r3
2952 ; P8BE-NEXT: xvcvspuxws v2, vs0
2953 ; P8BE-NEXT: blr
2954 ;
2955 ; P8LE-LABEL: fromDiffMemConsAConvftoui:
2956 ; P8LE: # %bb.0: # %entry
2957 ; P8LE-NEXT: lxvd2x vs0, 0, r3
2958 ; P8LE-NEXT: xxswapd v2, vs0
2959 ; P8LE-NEXT: xvcvspuxws v2, v2
2960 ; P8LE-NEXT: blr
2961 entry:
2962 %0 = load <4 x float>, ptr %ptr, align 4
2963 %1 = fptoui <4 x float> %0 to <4 x i32>
2964 ret <4 x i32> %1
2965 }
2967 define <4 x i32> @fromDiffMemConsDConvftoui(ptr nocapture readonly %ptr) {
2968 ; P9BE-LABEL: fromDiffMemConsDConvftoui:
2969 ; P9BE: # %bb.0: # %entry
2970 ; P9BE-NEXT: lxv vs0, 0(r3)
2971 ; P9BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
2972 ; P9BE-NEXT: addi r3, r3, .LCPI50_0@toc@l
2973 ; P9BE-NEXT: lxv vs1, 0(r3)
2974 ; P9BE-NEXT: xxperm vs0, vs0, vs1
2975 ; P9BE-NEXT: xvcvspuxws v2, vs0
2976 ; P9BE-NEXT: blr
2977 ;
2978 ; P9LE-LABEL: fromDiffMemConsDConvftoui:
2979 ; P9LE: # %bb.0: # %entry
2980 ; P9LE-NEXT: lxv vs0, 0(r3)
2981 ; P9LE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
2982 ; P9LE-NEXT: addi r3, r3, .LCPI50_0@toc@l
2983 ; P9LE-NEXT: lxv vs1, 0(r3)
2984 ; P9LE-NEXT: xxperm vs0, vs0, vs1
2985 ; P9LE-NEXT: xvcvspuxws v2, vs0
2986 ; P9LE-NEXT: blr
2987 ;
2988 ; P8BE-LABEL: fromDiffMemConsDConvftoui:
2989 ; P8BE: # %bb.0: # %entry
2990 ; P8BE-NEXT: lxvw4x v2, 0, r3
2991 ; P8BE-NEXT: addis r3, r2, .LCPI50_0@toc@ha
2992 ; P8BE-NEXT: addi r3, r3, .LCPI50_0@toc@l
2993 ; P8BE-NEXT: lxvw4x v3, 0, r3
2994 ; P8BE-NEXT: vperm v2, v2, v2, v3
2995 ; P8BE-NEXT: xvcvspuxws v2, v2
2996 ; P8BE-NEXT: blr
2997 ;
2998 ; P8LE-LABEL: fromDiffMemConsDConvftoui:
2999 ; P8LE: # %bb.0: # %entry
3000 ; P8LE-NEXT: addis r4, r2, .LCPI50_0@toc@ha
3001 ; P8LE-NEXT: lxvd2x v3, 0, r3
3002 ; P8LE-NEXT: addi r4, r4, .LCPI50_0@toc@l
3003 ; P8LE-NEXT: lxvd2x vs0, 0, r4
3004 ; P8LE-NEXT: xxswapd v2, vs0
3005 ; P8LE-NEXT: vperm v2, v3, v3, v2
3006 ; P8LE-NEXT: xvcvspuxws v2, v2
3007 ; P8LE-NEXT: blr
3008 entry:
3009 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3
3010 %0 = load float, ptr %arrayidx, align 4
3011 %conv = fptoui float %0 to i32
3012 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3013 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2
3014 %1 = load float, ptr %arrayidx1, align 4
3015 %conv2 = fptoui float %1 to i32
3016 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
3017 %arrayidx4 = getelementptr inbounds float, ptr %ptr, i64 1
3018 %2 = load float, ptr %arrayidx4, align 4
3019 %conv5 = fptoui float %2 to i32
3020 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
3021 %3 = load float, ptr %ptr, align 4
3022 %conv8 = fptoui float %3 to i32
3023 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
3024 ret <4 x i32> %vecinit9
3025 }
3027 define <4 x i32> @fromDiffMemVarAConvftoui(ptr nocapture readonly %arr, i32 signext %elem) {
3028 ; P9BE-LABEL: fromDiffMemVarAConvftoui:
3029 ; P9BE: # %bb.0: # %entry
3030 ; P9BE-NEXT: sldi r4, r4, 2
3031 ; P9BE-NEXT: lfsux f0, r3, r4
3032 ; P9BE-NEXT: lfs f1, 12(r3)
3033 ; P9BE-NEXT: lfs f2, 4(r3)
3034 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
3035 ; P9BE-NEXT: xvcvdpsp v2, vs1
3036 ; P9BE-NEXT: lfs f1, 8(r3)
3037 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
3038 ; P9BE-NEXT: xvcvdpsp v3, vs0
3039 ; P9BE-NEXT: vmrgew v2, v3, v2
3040 ; P9BE-NEXT: xvcvspuxws v2, v2
3041 ; P9BE-NEXT: blr
3042 ;
3043 ; P9LE-LABEL: fromDiffMemVarAConvftoui:
3044 ; P9LE: # %bb.0: # %entry
3045 ; P9LE-NEXT: sldi r4, r4, 2
3046 ; P9LE-NEXT: lfsux f0, r3, r4
3047 ; P9LE-NEXT: lfs f1, 8(r3)
3048 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3049 ; P9LE-NEXT: lfs f1, 12(r3)
3050 ; P9LE-NEXT: xvcvdpsp v2, vs0
3051 ; P9LE-NEXT: lfs f0, 4(r3)
3052 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3053 ; P9LE-NEXT: xvcvdpsp v3, vs0
3054 ; P9LE-NEXT: vmrgew v2, v3, v2
3055 ; P9LE-NEXT: xvcvspuxws v2, v2
3056 ; P9LE-NEXT: blr
3057 ;
3058 ; P8BE-LABEL: fromDiffMemVarAConvftoui:
3059 ; P8BE: # %bb.0: # %entry
3060 ; P8BE-NEXT: sldi r4, r4, 2
3061 ; P8BE-NEXT: lfsux f0, r3, r4
3062 ; P8BE-NEXT: lfs f1, 12(r3)
3063 ; P8BE-NEXT: lfs f2, 4(r3)
3064 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
3065 ; P8BE-NEXT: lfs f2, 8(r3)
3066 ; P8BE-NEXT: xvcvdpsp v2, vs1
3067 ; P8BE-NEXT: xxmrghd vs0, vs0, vs2
3068 ; P8BE-NEXT: xvcvdpsp v3, vs0
3069 ; P8BE-NEXT: vmrgew v2, v3, v2
3070 ; P8BE-NEXT: xvcvspuxws v2, v2
3071 ; P8BE-NEXT: blr
3072 ;
3073 ; P8LE-LABEL: fromDiffMemVarAConvftoui:
3074 ; P8LE: # %bb.0: # %entry
3075 ; P8LE-NEXT: sldi r4, r4, 2
3076 ; P8LE-NEXT: lfsux f0, r3, r4
3077 ; P8LE-NEXT: lfs f1, 8(r3)
3078 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3079 ; P8LE-NEXT: lfs f1, 4(r3)
3080 ; P8LE-NEXT: lfs f2, 12(r3)
3081 ; P8LE-NEXT: xvcvdpsp v2, vs0
3082 ; P8LE-NEXT: xxmrghd vs1, vs2, vs1
3083 ; P8LE-NEXT: xvcvdpsp v3, vs1
3084 ; P8LE-NEXT: vmrgew v2, v3, v2
3085 ; P8LE-NEXT: xvcvspuxws v2, v2
3086 ; P8LE-NEXT: blr
3087 entry:
3088 %idxprom = sext i32 %elem to i64
3089 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
3090 %0 = load float, ptr %arrayidx, align 4
3091 %conv = fptoui float %0 to i32
3092 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3093 %add = add nsw i32 %elem, 1
3094 %idxprom1 = sext i32 %add to i64
3095 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
3096 %1 = load float, ptr %arrayidx2, align 4
3097 %conv3 = fptoui float %1 to i32
3098 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3099 %add5 = add nsw i32 %elem, 2
3100 %idxprom6 = sext i32 %add5 to i64
3101 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6
3102 %2 = load float, ptr %arrayidx7, align 4
3103 %conv8 = fptoui float %2 to i32
3104 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3105 %add10 = add nsw i32 %elem, 3
3106 %idxprom11 = sext i32 %add10 to i64
3107 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11
3108 %3 = load float, ptr %arrayidx12, align 4
3109 %conv13 = fptoui float %3 to i32
3110 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3111 ret <4 x i32> %vecinit14
3112 ; FIXME: implement finding consecutive loads with pre-inc
3113 }
3115 define <4 x i32> @fromDiffMemVarDConvftoui(ptr nocapture readonly %arr, i32 signext %elem) {
3116 ; P9BE-LABEL: fromDiffMemVarDConvftoui:
3117 ; P9BE: # %bb.0: # %entry
3118 ; P9BE-NEXT: sldi r4, r4, 2
3119 ; P9BE-NEXT: lfsux f0, r3, r4
3120 ; P9BE-NEXT: lfs f1, -12(r3)
3121 ; P9BE-NEXT: lfs f2, -4(r3)
3122 ; P9BE-NEXT: xxmrghd vs1, vs2, vs1
3123 ; P9BE-NEXT: xvcvdpsp v2, vs1
3124 ; P9BE-NEXT: lfs f1, -8(r3)
3125 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
3126 ; P9BE-NEXT: xvcvdpsp v3, vs0
3127 ; P9BE-NEXT: vmrgew v2, v3, v2
3128 ; P9BE-NEXT: xvcvspuxws v2, v2
3129 ; P9BE-NEXT: blr
3130 ;
3131 ; P9LE-LABEL: fromDiffMemVarDConvftoui:
3132 ; P9LE: # %bb.0: # %entry
3133 ; P9LE-NEXT: sldi r4, r4, 2
3134 ; P9LE-NEXT: lfsux f0, r3, r4
3135 ; P9LE-NEXT: lfs f1, -8(r3)
3136 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3137 ; P9LE-NEXT: lfs f1, -12(r3)
3138 ; P9LE-NEXT: xvcvdpsp v2, vs0
3139 ; P9LE-NEXT: lfs f0, -4(r3)
3140 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3141 ; P9LE-NEXT: xvcvdpsp v3, vs0
3142 ; P9LE-NEXT: vmrgew v2, v3, v2
3143 ; P9LE-NEXT: xvcvspuxws v2, v2
3144 ; P9LE-NEXT: blr
3145 ;
3146 ; P8BE-LABEL: fromDiffMemVarDConvftoui:
3147 ; P8BE: # %bb.0: # %entry
3148 ; P8BE-NEXT: sldi r4, r4, 2
3149 ; P8BE-NEXT: lfsux f0, r3, r4
3150 ; P8BE-NEXT: lfs f1, -12(r3)
3151 ; P8BE-NEXT: lfs f2, -4(r3)
3152 ; P8BE-NEXT: xxmrghd vs1, vs2, vs1
3153 ; P8BE-NEXT: lfs f2, -8(r3)
3154 ; P8BE-NEXT: xvcvdpsp v2, vs1
3155 ; P8BE-NEXT: xxmrghd vs0, vs0, vs2
3156 ; P8BE-NEXT: xvcvdpsp v3, vs0
3157 ; P8BE-NEXT: vmrgew v2, v3, v2
3158 ; P8BE-NEXT: xvcvspuxws v2, v2
3159 ; P8BE-NEXT: blr
3160 ;
3161 ; P8LE-LABEL: fromDiffMemVarDConvftoui:
3162 ; P8LE: # %bb.0: # %entry
3163 ; P8LE-NEXT: sldi r4, r4, 2
3164 ; P8LE-NEXT: lfsux f0, r3, r4
3165 ; P8LE-NEXT: lfs f1, -8(r3)
3166 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3167 ; P8LE-NEXT: lfs f1, -4(r3)
3168 ; P8LE-NEXT: lfs f2, -12(r3)
3169 ; P8LE-NEXT: xvcvdpsp v2, vs0
3170 ; P8LE-NEXT: xxmrghd vs1, vs2, vs1
3171 ; P8LE-NEXT: xvcvdpsp v3, vs1
3172 ; P8LE-NEXT: vmrgew v2, v3, v2
3173 ; P8LE-NEXT: xvcvspuxws v2, v2
3174 ; P8LE-NEXT: blr
3175 entry:
3176 %idxprom = sext i32 %elem to i64
3177 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
3178 %0 = load float, ptr %arrayidx, align 4
3179 %conv = fptoui float %0 to i32
3180 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3181 %sub = add nsw i32 %elem, -1
3182 %idxprom1 = sext i32 %sub to i64
3183 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
3184 %1 = load float, ptr %arrayidx2, align 4
3185 %conv3 = fptoui float %1 to i32
3186 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3187 %sub5 = add nsw i32 %elem, -2
3188 %idxprom6 = sext i32 %sub5 to i64
3189 %arrayidx7 = getelementptr inbounds float, ptr %arr, i64 %idxprom6
3190 %2 = load float, ptr %arrayidx7, align 4
3191 %conv8 = fptoui float %2 to i32
3192 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3193 %sub10 = add nsw i32 %elem, -3
3194 %idxprom11 = sext i32 %sub10 to i64
3195 %arrayidx12 = getelementptr inbounds float, ptr %arr, i64 %idxprom11
3196 %3 = load float, ptr %arrayidx12, align 4
3197 %conv13 = fptoui float %3 to i32
3198 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3199 ret <4 x i32> %vecinit14
3200 ; FIXME: implement finding consecutive loads with pre-inc
3201 }
3203 define <4 x i32> @spltRegValConvftoui(float %val) {
3204 ; P9BE-LABEL: spltRegValConvftoui:
3205 ; P9BE: # %bb.0: # %entry
3206 ; P9BE-NEXT: xscvdpuxws f0, f1
3207 ; P9BE-NEXT: xxspltw v2, vs0, 1
3208 ; P9BE-NEXT: blr
3209 ;
3210 ; P9LE-LABEL: spltRegValConvftoui:
3211 ; P9LE: # %bb.0: # %entry
3212 ; P9LE-NEXT: xscvdpuxws f0, f1
3213 ; P9LE-NEXT: xxspltw v2, vs0, 1
3214 ; P9LE-NEXT: blr
3215 ;
3216 ; P8BE-LABEL: spltRegValConvftoui:
3217 ; P8BE: # %bb.0: # %entry
3218 ; P8BE-NEXT: xscvdpuxws f0, f1
3219 ; P8BE-NEXT: xxspltw v2, vs0, 1
3220 ; P8BE-NEXT: blr
3221 ;
3222 ; P8LE-LABEL: spltRegValConvftoui:
3223 ; P8LE: # %bb.0: # %entry
3224 ; P8LE-NEXT: xscvdpuxws f0, f1
3225 ; P8LE-NEXT: xxspltw v2, vs0, 1
3226 ; P8LE-NEXT: blr
3227 entry:
3228 %conv = fptoui float %val to i32
3229 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3230 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3231 ret <4 x i32> %splat.splat
3232 }
3234 define <4 x i32> @spltMemValConvftoui(ptr nocapture readonly %ptr) {
3235 ; P9BE-LABEL: spltMemValConvftoui:
3236 ; P9BE: # %bb.0: # %entry
3237 ; P9BE-NEXT: lfiwzx f0, 0, r3
3238 ; P9BE-NEXT: xvcvspuxws vs0, vs0
3239 ; P9BE-NEXT: xxspltw v2, vs0, 1
3240 ; P9BE-NEXT: blr
3241 ;
3242 ; P9LE-LABEL: spltMemValConvftoui:
3243 ; P9LE: # %bb.0: # %entry
3244 ; P9LE-NEXT: lfiwzx f0, 0, r3
3245 ; P9LE-NEXT: xvcvspuxws vs0, vs0
3246 ; P9LE-NEXT: xxspltw v2, vs0, 1
3247 ; P9LE-NEXT: blr
3248 ;
3249 ; P8BE-LABEL: spltMemValConvftoui:
3250 ; P8BE: # %bb.0: # %entry
3251 ; P8BE-NEXT: lfsx f0, 0, r3
3252 ; P8BE-NEXT: xscvdpuxws f0, f0
3253 ; P8BE-NEXT: xxspltw v2, vs0, 1
3254 ; P8BE-NEXT: blr
3255 ;
3256 ; P8LE-LABEL: spltMemValConvftoui:
3257 ; P8LE: # %bb.0: # %entry
3258 ; P8LE-NEXT: lfsx f0, 0, r3
3259 ; P8LE-NEXT: xscvdpuxws f0, f0
3260 ; P8LE-NEXT: xxspltw v2, vs0, 1
3261 ; P8LE-NEXT: blr
3262 entry:
3263 %0 = load float, ptr %ptr, align 4
3264 %conv = fptoui float %0 to i32
3265 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3266 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3267 ret <4 x i32> %splat.splat
3268 }
3270 define <4 x i32> @spltCnstConvdtoui() {
3271 ; P9BE-LABEL: spltCnstConvdtoui:
3272 ; P9BE: # %bb.0: # %entry
3273 ; P9BE-NEXT: vspltisw v2, 4
3274 ; P9BE-NEXT: blr
3275 ;
3276 ; P9LE-LABEL: spltCnstConvdtoui:
3277 ; P9LE: # %bb.0: # %entry
3278 ; P9LE-NEXT: vspltisw v2, 4
3279 ; P9LE-NEXT: blr
3280 ;
3281 ; P8BE-LABEL: spltCnstConvdtoui:
3282 ; P8BE: # %bb.0: # %entry
3283 ; P8BE-NEXT: vspltisw v2, 4
3284 ; P8BE-NEXT: blr
3285 ;
3286 ; P8LE-LABEL: spltCnstConvdtoui:
3287 ; P8LE: # %bb.0: # %entry
3288 ; P8LE-NEXT: vspltisw v2, 4
3289 ; P8LE-NEXT: blr
3290 entry:
3291 ret <4 x i32> <i32 4, i32 4, i32 4, i32 4>
3292 }
3294 define <4 x i32> @fromRegsConvdtoui(double %a, double %b, double %c, double %d) {
3295 ; P9BE-LABEL: fromRegsConvdtoui:
3296 ; P9BE: # %bb.0: # %entry
3297 ; P9BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3298 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3299 ; P9BE-NEXT: xxmrghd vs0, vs2, vs4
3300 ; P9BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3301 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3302 ; P9BE-NEXT: xvcvdpuxws v2, vs0
3303 ; P9BE-NEXT: xxmrghd vs0, vs1, vs3
3304 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3305 ; P9BE-NEXT: vmrgew v2, v3, v2
3306 ; P9BE-NEXT: blr
3307 ;
3308 ; P9LE-LABEL: fromRegsConvdtoui:
3309 ; P9LE: # %bb.0: # %entry
3310 ; P9LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3311 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3312 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3313 ; P9LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3314 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3315 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3316 ; P9LE-NEXT: xxmrghd vs0, vs4, vs2
3317 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3318 ; P9LE-NEXT: vmrgew v2, v3, v2
3319 ; P9LE-NEXT: blr
3320 ;
3321 ; P8BE-LABEL: fromRegsConvdtoui:
3322 ; P8BE: # %bb.0: # %entry
3323 ; P8BE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3324 ; P8BE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3325 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3326 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3327 ; P8BE-NEXT: xxmrghd vs0, vs2, vs4
3328 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
3329 ; P8BE-NEXT: xvcvdpuxws v2, vs0
3330 ; P8BE-NEXT: xvcvdpuxws v3, vs1
3331 ; P8BE-NEXT: vmrgew v2, v3, v2
3332 ; P8BE-NEXT: blr
3333 ;
3334 ; P8LE-LABEL: fromRegsConvdtoui:
3335 ; P8LE: # %bb.0: # %entry
3336 ; P8LE-NEXT: # kill: def $f4 killed $f4 def $vsl4
3337 ; P8LE-NEXT: # kill: def $f3 killed $f3 def $vsl3
3338 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
3339 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
3340 ; P8LE-NEXT: xxmrghd vs0, vs3, vs1
3341 ; P8LE-NEXT: xxmrghd vs1, vs4, vs2
3342 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3343 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3344 ; P8LE-NEXT: vmrgew v2, v3, v2
3345 ; P8LE-NEXT: blr
3346 entry:
3347 %conv = fptoui double %a to i32
3348 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3349 %conv1 = fptoui double %b to i32
3350 %vecinit2 = insertelement <4 x i32> %vecinit, i32 %conv1, i32 1
3351 %conv3 = fptoui double %c to i32
3352 %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %conv3, i32 2
3353 %conv5 = fptoui double %d to i32
3354 %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %conv5, i32 3
3355 ret <4 x i32> %vecinit6
3356 }
3358 define <4 x i32> @fromDiffConstsConvdtoui() {
3359 ; P9BE-LABEL: fromDiffConstsConvdtoui:
3360 ; P9BE: # %bb.0: # %entry
3361 ; P9BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
3362 ; P9BE-NEXT: addi r3, r3, .LCPI57_0@toc@l
3363 ; P9BE-NEXT: lxv v2, 0(r3)
3364 ; P9BE-NEXT: blr
3365 ;
3366 ; P9LE-LABEL: fromDiffConstsConvdtoui:
3367 ; P9LE: # %bb.0: # %entry
3368 ; P9LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
3369 ; P9LE-NEXT: addi r3, r3, .LCPI57_0@toc@l
3370 ; P9LE-NEXT: lxv v2, 0(r3)
3371 ; P9LE-NEXT: blr
3372 ;
3373 ; P8BE-LABEL: fromDiffConstsConvdtoui:
3374 ; P8BE: # %bb.0: # %entry
3375 ; P8BE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
3376 ; P8BE-NEXT: addi r3, r3, .LCPI57_0@toc@l
3377 ; P8BE-NEXT: lxvw4x v2, 0, r3
3378 ; P8BE-NEXT: blr
3379 ;
3380 ; P8LE-LABEL: fromDiffConstsConvdtoui:
3381 ; P8LE: # %bb.0: # %entry
3382 ; P8LE-NEXT: addis r3, r2, .LCPI57_0@toc@ha
3383 ; P8LE-NEXT: addi r3, r3, .LCPI57_0@toc@l
3384 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3385 ; P8LE-NEXT: xxswapd v2, vs0
3386 ; P8LE-NEXT: blr
3387 entry:
3388 ret <4 x i32> <i32 24, i32 234, i32 988, i32 422>
3389 }
3391 define <4 x i32> @fromDiffMemConsAConvdtoui(ptr nocapture readonly %ptr) {
3392 ; P9BE-LABEL: fromDiffMemConsAConvdtoui:
3393 ; P9BE: # %bb.0: # %entry
3394 ; P9BE-NEXT: lxv vs0, 0(r3)
3395 ; P9BE-NEXT: lxv vs1, 16(r3)
3396 ; P9BE-NEXT: xxmrgld vs2, vs0, vs1
3397 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
3398 ; P9BE-NEXT: xvcvdpuxws v2, vs2
3399 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3400 ; P9BE-NEXT: vmrgew v2, v3, v2
3401 ; P9BE-NEXT: blr
3402 ;
3403 ; P9LE-LABEL: fromDiffMemConsAConvdtoui:
3404 ; P9LE: # %bb.0: # %entry
3405 ; P9LE-NEXT: lxv vs0, 0(r3)
3406 ; P9LE-NEXT: lxv vs1, 16(r3)
3407 ; P9LE-NEXT: xxmrgld vs2, vs1, vs0
3408 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
3409 ; P9LE-NEXT: xvcvdpuxws v2, vs2
3410 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3411 ; P9LE-NEXT: vmrgew v2, v3, v2
3412 ; P9LE-NEXT: blr
3413 ;
3414 ; P8BE-LABEL: fromDiffMemConsAConvdtoui:
3415 ; P8BE: # %bb.0: # %entry
3416 ; P8BE-NEXT: li r4, 16
3417 ; P8BE-NEXT: lxvd2x vs0, 0, r3
3418 ; P8BE-NEXT: lxvd2x vs1, r3, r4
3419 ; P8BE-NEXT: xxmrgld vs2, vs0, vs1
3420 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
3421 ; P8BE-NEXT: xvcvdpuxws v2, vs2
3422 ; P8BE-NEXT: xvcvdpuxws v3, vs0
3423 ; P8BE-NEXT: vmrgew v2, v3, v2
3424 ; P8BE-NEXT: blr
3425 ;
3426 ; P8LE-LABEL: fromDiffMemConsAConvdtoui:
3427 ; P8LE: # %bb.0: # %entry
3428 ; P8LE-NEXT: li r4, 16
3429 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3430 ; P8LE-NEXT: lxvd2x vs1, r3, r4
3431 ; P8LE-NEXT: xxswapd vs0, vs0
3432 ; P8LE-NEXT: xxswapd vs1, vs1
3433 ; P8LE-NEXT: xxmrgld vs2, vs1, vs0
3434 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
3435 ; P8LE-NEXT: xvcvdpuxws v2, vs2
3436 ; P8LE-NEXT: xvcvdpuxws v3, vs0
3437 ; P8LE-NEXT: vmrgew v2, v3, v2
3438 ; P8LE-NEXT: blr
3439 entry:
3440 %0 = load <2 x double>, ptr %ptr, align 8
3441 %1 = fptoui <2 x double> %0 to <2 x i32>
3442 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 2
3443 %2 = load <2 x double>, ptr %arrayidx4, align 8
3444 %3 = fptoui <2 x double> %2 to <2 x i32>
3445 %vecinit9 = shufflevector <2 x i32> %1, <2 x i32> %3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
3446 ret <4 x i32> %vecinit9
3447 }
3449 define <4 x i32> @fromDiffMemConsDConvdtoui(ptr nocapture readonly %ptr) {
3450 ; P9BE-LABEL: fromDiffMemConsDConvdtoui:
3451 ; P9BE: # %bb.0: # %entry
3452 ; P9BE-NEXT: lfd f0, 24(r3)
3453 ; P9BE-NEXT: lfd f1, 16(r3)
3454 ; P9BE-NEXT: lfd f2, 8(r3)
3455 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
3456 ; P9BE-NEXT: lfd f3, 0(r3)
3457 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
3458 ; P9BE-NEXT: xvcvdpuxws v2, vs1
3459 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3460 ; P9BE-NEXT: vmrgew v2, v3, v2
3461 ; P9BE-NEXT: blr
3462 ;
3463 ; P9LE-LABEL: fromDiffMemConsDConvdtoui:
3464 ; P9LE: # %bb.0: # %entry
3465 ; P9LE-NEXT: lfd f0, 24(r3)
3466 ; P9LE-NEXT: lfd f2, 8(r3)
3467 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
3468 ; P9LE-NEXT: lfd f1, 16(r3)
3469 ; P9LE-NEXT: lfd f3, 0(r3)
3470 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3471 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3472 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3473 ; P9LE-NEXT: vmrgew v2, v3, v2
3474 ; P9LE-NEXT: blr
3475 ;
3476 ; P8BE-LABEL: fromDiffMemConsDConvdtoui:
3477 ; P8BE: # %bb.0: # %entry
3478 ; P8BE-NEXT: lfd f0, 24(r3)
3479 ; P8BE-NEXT: lfd f1, 16(r3)
3480 ; P8BE-NEXT: lfd f2, 8(r3)
3481 ; P8BE-NEXT: lfd f3, 0(r3)
3482 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
3483 ; P8BE-NEXT: xxmrghd vs0, vs0, vs2
3484 ; P8BE-NEXT: xvcvdpuxws v2, vs1
3485 ; P8BE-NEXT: xvcvdpuxws v3, vs0
3486 ; P8BE-NEXT: vmrgew v2, v3, v2
3487 ; P8BE-NEXT: blr
3488 ;
3489 ; P8LE-LABEL: fromDiffMemConsDConvdtoui:
3490 ; P8LE: # %bb.0: # %entry
3491 ; P8LE-NEXT: lfd f0, 24(r3)
3492 ; P8LE-NEXT: lfd f1, 16(r3)
3493 ; P8LE-NEXT: lfd f2, 8(r3)
3494 ; P8LE-NEXT: lfd f3, 0(r3)
3495 ; P8LE-NEXT: xxmrghd vs0, vs2, vs0
3496 ; P8LE-NEXT: xxmrghd vs1, vs3, vs1
3497 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3498 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3499 ; P8LE-NEXT: vmrgew v2, v3, v2
3500 ; P8LE-NEXT: blr
3501 entry:
3502 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3
3503 %0 = load double, ptr %arrayidx, align 8
3504 %conv = fptoui double %0 to i32
3505 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3506 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2
3507 %1 = load double, ptr %arrayidx1, align 8
3508 %conv2 = fptoui double %1 to i32
3509 %vecinit3 = insertelement <4 x i32> %vecinit, i32 %conv2, i32 1
3510 %arrayidx4 = getelementptr inbounds double, ptr %ptr, i64 1
3511 %2 = load double, ptr %arrayidx4, align 8
3512 %conv5 = fptoui double %2 to i32
3513 %vecinit6 = insertelement <4 x i32> %vecinit3, i32 %conv5, i32 2
3514 %3 = load double, ptr %ptr, align 8
3515 %conv8 = fptoui double %3 to i32
3516 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
3517 ret <4 x i32> %vecinit9
3518 }
3520 define <4 x i32> @fromDiffMemVarAConvdtoui(ptr nocapture readonly %arr, i32 signext %elem) {
3521 ; P9BE-LABEL: fromDiffMemVarAConvdtoui:
3522 ; P9BE: # %bb.0: # %entry
3523 ; P9BE-NEXT: sldi r4, r4, 3
3524 ; P9BE-NEXT: lfdux f0, r3, r4
3525 ; P9BE-NEXT: lfd f1, 8(r3)
3526 ; P9BE-NEXT: lfd f2, 16(r3)
3527 ; P9BE-NEXT: lfd f3, 24(r3)
3528 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
3529 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
3530 ; P9BE-NEXT: xvcvdpuxws v2, vs1
3531 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3532 ; P9BE-NEXT: vmrgew v2, v3, v2
3533 ; P9BE-NEXT: blr
3534 ;
3535 ; P9LE-LABEL: fromDiffMemVarAConvdtoui:
3536 ; P9LE: # %bb.0: # %entry
3537 ; P9LE-NEXT: sldi r4, r4, 3
3538 ; P9LE-NEXT: lfdux f0, r3, r4
3539 ; P9LE-NEXT: lfd f2, 16(r3)
3540 ; P9LE-NEXT: lfd f1, 8(r3)
3541 ; P9LE-NEXT: lfd f3, 24(r3)
3542 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
3543 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3544 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3545 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3546 ; P9LE-NEXT: vmrgew v2, v3, v2
3547 ; P9LE-NEXT: blr
3548 ;
3549 ; P8BE-LABEL: fromDiffMemVarAConvdtoui:
3550 ; P8BE: # %bb.0: # %entry
3551 ; P8BE-NEXT: sldi r4, r4, 3
3552 ; P8BE-NEXT: lfdux f0, r3, r4
3553 ; P8BE-NEXT: lfd f1, 8(r3)
3554 ; P8BE-NEXT: lfd f2, 16(r3)
3555 ; P8BE-NEXT: lfd f3, 24(r3)
3556 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
3557 ; P8BE-NEXT: xxmrghd vs0, vs0, vs2
3558 ; P8BE-NEXT: xvcvdpuxws v2, vs1
3559 ; P8BE-NEXT: xvcvdpuxws v3, vs0
3560 ; P8BE-NEXT: vmrgew v2, v3, v2
3561 ; P8BE-NEXT: blr
3562 ;
3563 ; P8LE-LABEL: fromDiffMemVarAConvdtoui:
3564 ; P8LE: # %bb.0: # %entry
3565 ; P8LE-NEXT: sldi r4, r4, 3
3566 ; P8LE-NEXT: lfdux f0, r3, r4
3567 ; P8LE-NEXT: lfd f1, 8(r3)
3568 ; P8LE-NEXT: lfd f2, 16(r3)
3569 ; P8LE-NEXT: lfd f3, 24(r3)
3570 ; P8LE-NEXT: xxmrghd vs0, vs2, vs0
3571 ; P8LE-NEXT: xxmrghd vs1, vs3, vs1
3572 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3573 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3574 ; P8LE-NEXT: vmrgew v2, v3, v2
3575 ; P8LE-NEXT: blr
3576 entry:
3577 %idxprom = sext i32 %elem to i64
3578 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
3579 %0 = load double, ptr %arrayidx, align 8
3580 %conv = fptoui double %0 to i32
3581 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3582 %add = add nsw i32 %elem, 1
3583 %idxprom1 = sext i32 %add to i64
3584 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
3585 %1 = load double, ptr %arrayidx2, align 8
3586 %conv3 = fptoui double %1 to i32
3587 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3588 %add5 = add nsw i32 %elem, 2
3589 %idxprom6 = sext i32 %add5 to i64
3590 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6
3591 %2 = load double, ptr %arrayidx7, align 8
3592 %conv8 = fptoui double %2 to i32
3593 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3594 %add10 = add nsw i32 %elem, 3
3595 %idxprom11 = sext i32 %add10 to i64
3596 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11
3597 %3 = load double, ptr %arrayidx12, align 8
3598 %conv13 = fptoui double %3 to i32
3599 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3600 ret <4 x i32> %vecinit14
3601 }
3603 define <4 x i32> @fromDiffMemVarDConvdtoui(ptr nocapture readonly %arr, i32 signext %elem) {
3604 ; P9BE-LABEL: fromDiffMemVarDConvdtoui:
3605 ; P9BE: # %bb.0: # %entry
3606 ; P9BE-NEXT: sldi r4, r4, 3
3607 ; P9BE-NEXT: lfdux f0, r3, r4
3608 ; P9BE-NEXT: lfd f1, -8(r3)
3609 ; P9BE-NEXT: lfd f2, -16(r3)
3610 ; P9BE-NEXT: lfd f3, -24(r3)
3611 ; P9BE-NEXT: xxmrghd vs1, vs1, vs3
3612 ; P9BE-NEXT: xxmrghd vs0, vs0, vs2
3613 ; P9BE-NEXT: xvcvdpuxws v2, vs1
3614 ; P9BE-NEXT: xvcvdpuxws v3, vs0
3615 ; P9BE-NEXT: vmrgew v2, v3, v2
3616 ; P9BE-NEXT: blr
3617 ;
3618 ; P9LE-LABEL: fromDiffMemVarDConvdtoui:
3619 ; P9LE: # %bb.0: # %entry
3620 ; P9LE-NEXT: sldi r4, r4, 3
3621 ; P9LE-NEXT: lfdux f0, r3, r4
3622 ; P9LE-NEXT: lfd f2, -16(r3)
3623 ; P9LE-NEXT: lfd f1, -8(r3)
3624 ; P9LE-NEXT: lfd f3, -24(r3)
3625 ; P9LE-NEXT: xxmrghd vs0, vs2, vs0
3626 ; P9LE-NEXT: xvcvdpuxws v2, vs0
3627 ; P9LE-NEXT: xxmrghd vs0, vs3, vs1
3628 ; P9LE-NEXT: xvcvdpuxws v3, vs0
3629 ; P9LE-NEXT: vmrgew v2, v3, v2
3630 ; P9LE-NEXT: blr
3631 ;
3632 ; P8BE-LABEL: fromDiffMemVarDConvdtoui:
3633 ; P8BE: # %bb.0: # %entry
3634 ; P8BE-NEXT: sldi r4, r4, 3
3635 ; P8BE-NEXT: lfdux f0, r3, r4
3636 ; P8BE-NEXT: lfd f1, -8(r3)
3637 ; P8BE-NEXT: lfd f2, -16(r3)
3638 ; P8BE-NEXT: lfd f3, -24(r3)
3639 ; P8BE-NEXT: xxmrghd vs1, vs1, vs3
3640 ; P8BE-NEXT: xxmrghd vs0, vs0, vs2
3641 ; P8BE-NEXT: xvcvdpuxws v2, vs1
3642 ; P8BE-NEXT: xvcvdpuxws v3, vs0
3643 ; P8BE-NEXT: vmrgew v2, v3, v2
3644 ; P8BE-NEXT: blr
3645 ;
3646 ; P8LE-LABEL: fromDiffMemVarDConvdtoui:
3647 ; P8LE: # %bb.0: # %entry
3648 ; P8LE-NEXT: sldi r4, r4, 3
3649 ; P8LE-NEXT: lfdux f0, r3, r4
3650 ; P8LE-NEXT: lfd f1, -8(r3)
3651 ; P8LE-NEXT: lfd f2, -16(r3)
3652 ; P8LE-NEXT: lfd f3, -24(r3)
3653 ; P8LE-NEXT: xxmrghd vs0, vs2, vs0
3654 ; P8LE-NEXT: xxmrghd vs1, vs3, vs1
3655 ; P8LE-NEXT: xvcvdpuxws v2, vs0
3656 ; P8LE-NEXT: xvcvdpuxws v3, vs1
3657 ; P8LE-NEXT: vmrgew v2, v3, v2
3658 ; P8LE-NEXT: blr
3659 entry:
3660 %idxprom = sext i32 %elem to i64
3661 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
3662 %0 = load double, ptr %arrayidx, align 8
3663 %conv = fptoui double %0 to i32
3664 %vecinit = insertelement <4 x i32> undef, i32 %conv, i32 0
3665 %sub = add nsw i32 %elem, -1
3666 %idxprom1 = sext i32 %sub to i64
3667 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
3668 %1 = load double, ptr %arrayidx2, align 8
3669 %conv3 = fptoui double %1 to i32
3670 %vecinit4 = insertelement <4 x i32> %vecinit, i32 %conv3, i32 1
3671 %sub5 = add nsw i32 %elem, -2
3672 %idxprom6 = sext i32 %sub5 to i64
3673 %arrayidx7 = getelementptr inbounds double, ptr %arr, i64 %idxprom6
3674 %2 = load double, ptr %arrayidx7, align 8
3675 %conv8 = fptoui double %2 to i32
3676 %vecinit9 = insertelement <4 x i32> %vecinit4, i32 %conv8, i32 2
3677 %sub10 = add nsw i32 %elem, -3
3678 %idxprom11 = sext i32 %sub10 to i64
3679 %arrayidx12 = getelementptr inbounds double, ptr %arr, i64 %idxprom11
3680 %3 = load double, ptr %arrayidx12, align 8
3681 %conv13 = fptoui double %3 to i32
3682 %vecinit14 = insertelement <4 x i32> %vecinit9, i32 %conv13, i32 3
3683 ret <4 x i32> %vecinit14
3684 }
3686 define <4 x i32> @spltRegValConvdtoui(double %val) {
3687 ; P9BE-LABEL: spltRegValConvdtoui:
3688 ; P9BE: # %bb.0: # %entry
3689 ; P9BE-NEXT: xscvdpuxws f0, f1
3690 ; P9BE-NEXT: xxspltw v2, vs0, 1
3691 ; P9BE-NEXT: blr
3692 ;
3693 ; P9LE-LABEL: spltRegValConvdtoui:
3694 ; P9LE: # %bb.0: # %entry
3695 ; P9LE-NEXT: xscvdpuxws f0, f1
3696 ; P9LE-NEXT: xxspltw v2, vs0, 1
3697 ; P9LE-NEXT: blr
3698 ;
3699 ; P8BE-LABEL: spltRegValConvdtoui:
3700 ; P8BE: # %bb.0: # %entry
3701 ; P8BE-NEXT: xscvdpuxws f0, f1
3702 ; P8BE-NEXT: xxspltw v2, vs0, 1
3703 ; P8BE-NEXT: blr
3704 ;
3705 ; P8LE-LABEL: spltRegValConvdtoui:
3706 ; P8LE: # %bb.0: # %entry
3707 ; P8LE-NEXT: xscvdpuxws f0, f1
3708 ; P8LE-NEXT: xxspltw v2, vs0, 1
3709 ; P8LE-NEXT: blr
3710 entry:
3711 %conv = fptoui double %val to i32
3712 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3713 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3714 ret <4 x i32> %splat.splat
3715 }
3717 define <4 x i32> @spltMemValConvdtoui(ptr nocapture readonly %ptr) {
3718 ; P9BE-LABEL: spltMemValConvdtoui:
3719 ; P9BE: # %bb.0: # %entry
3720 ; P9BE-NEXT: lfd f0, 0(r3)
3721 ; P9BE-NEXT: xscvdpuxws f0, f0
3722 ; P9BE-NEXT: xxspltw v2, vs0, 1
3723 ; P9BE-NEXT: blr
3724 ;
3725 ; P9LE-LABEL: spltMemValConvdtoui:
3726 ; P9LE: # %bb.0: # %entry
3727 ; P9LE-NEXT: lfd f0, 0(r3)
3728 ; P9LE-NEXT: xscvdpuxws f0, f0
3729 ; P9LE-NEXT: xxspltw v2, vs0, 1
3730 ; P9LE-NEXT: blr
3731 ;
3732 ; P8BE-LABEL: spltMemValConvdtoui:
3733 ; P8BE: # %bb.0: # %entry
3734 ; P8BE-NEXT: lfdx f0, 0, r3
3735 ; P8BE-NEXT: xscvdpuxws f0, f0
3736 ; P8BE-NEXT: xxspltw v2, vs0, 1
3737 ; P8BE-NEXT: blr
3738 ;
3739 ; P8LE-LABEL: spltMemValConvdtoui:
3740 ; P8LE: # %bb.0: # %entry
3741 ; P8LE-NEXT: lfdx f0, 0, r3
3742 ; P8LE-NEXT: xscvdpuxws f0, f0
3743 ; P8LE-NEXT: xxspltw v2, vs0, 1
3744 ; P8LE-NEXT: blr
3745 entry:
3746 %0 = load double, ptr %ptr, align 8
3747 %conv = fptoui double %0 to i32
3748 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0
3749 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
3750 ret <4 x i32> %splat.splat
3751 }
3753 define <2 x i64> @allZeroll() {
3754 ; P9BE-LABEL: allZeroll:
3755 ; P9BE: # %bb.0: # %entry
3756 ; P9BE-NEXT: xxlxor v2, v2, v2
3757 ; P9BE-NEXT: blr
3758 ;
3759 ; P9LE-LABEL: allZeroll:
3760 ; P9LE: # %bb.0: # %entry
3761 ; P9LE-NEXT: xxlxor v2, v2, v2
3762 ; P9LE-NEXT: blr
3763 ;
3764 ; P8BE-LABEL: allZeroll:
3765 ; P8BE: # %bb.0: # %entry
3766 ; P8BE-NEXT: xxlxor v2, v2, v2
3767 ; P8BE-NEXT: blr
3768 ;
3769 ; P8LE-LABEL: allZeroll:
3770 ; P8LE: # %bb.0: # %entry
3771 ; P8LE-NEXT: xxlxor v2, v2, v2
3772 ; P8LE-NEXT: blr
3773 entry:
3774 ret <2 x i64> zeroinitializer
3775 }
3777 define <2 x i64> @spltConst1ll() {
3778 ; P9BE-LABEL: spltConst1ll:
3779 ; P9BE: # %bb.0: # %entry
3780 ; P9BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
3781 ; P9BE-NEXT: addi r3, r3, .LCPI65_0@toc@l
3782 ; P9BE-NEXT: lxv v2, 0(r3)
3783 ; P9BE-NEXT: blr
3784 ;
3785 ; P9LE-LABEL: spltConst1ll:
3786 ; P9LE: # %bb.0: # %entry
3787 ; P9LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
3788 ; P9LE-NEXT: addi r3, r3, .LCPI65_0@toc@l
3789 ; P9LE-NEXT: lxv v2, 0(r3)
3790 ; P9LE-NEXT: blr
3791 ;
3792 ; P8BE-LABEL: spltConst1ll:
3793 ; P8BE: # %bb.0: # %entry
3794 ; P8BE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
3795 ; P8BE-NEXT: addi r3, r3, .LCPI65_0@toc@l
3796 ; P8BE-NEXT: lxvd2x v2, 0, r3
3797 ; P8BE-NEXT: blr
3798 ;
3799 ; P8LE-LABEL: spltConst1ll:
3800 ; P8LE: # %bb.0: # %entry
3801 ; P8LE-NEXT: addis r3, r2, .LCPI65_0@toc@ha
3802 ; P8LE-NEXT: addi r3, r3, .LCPI65_0@toc@l
3803 ; P8LE-NEXT: lxvd2x v2, 0, r3
3804 ; P8LE-NEXT: blr
3805 entry:
3806 ret <2 x i64> <i64 1, i64 1>
3807 }
3809 define <2 x i64> @spltConst16kll() {
3810 ; P9BE-LABEL: spltConst16kll:
3811 ; P9BE: # %bb.0: # %entry
3812 ; P9BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
3813 ; P9BE-NEXT: addi r3, r3, .LCPI66_0@toc@l
3814 ; P9BE-NEXT: lxv v2, 0(r3)
3815 ; P9BE-NEXT: blr
3816 ;
3817 ; P9LE-LABEL: spltConst16kll:
3818 ; P9LE: # %bb.0: # %entry
3819 ; P9LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
3820 ; P9LE-NEXT: addi r3, r3, .LCPI66_0@toc@l
3821 ; P9LE-NEXT: lxv v2, 0(r3)
3822 ; P9LE-NEXT: blr
3823 ;
3824 ; P8BE-LABEL: spltConst16kll:
3825 ; P8BE: # %bb.0: # %entry
3826 ; P8BE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
3827 ; P8BE-NEXT: addi r3, r3, .LCPI66_0@toc@l
3828 ; P8BE-NEXT: lxvd2x v2, 0, r3
3829 ; P8BE-NEXT: blr
3830 ;
3831 ; P8LE-LABEL: spltConst16kll:
3832 ; P8LE: # %bb.0: # %entry
3833 ; P8LE-NEXT: addis r3, r2, .LCPI66_0@toc@ha
3834 ; P8LE-NEXT: addi r3, r3, .LCPI66_0@toc@l
3835 ; P8LE-NEXT: lxvd2x v2, 0, r3
3836 ; P8LE-NEXT: blr
3837 entry:
3838 ret <2 x i64> <i64 32767, i64 32767>
3839 }
3841 define <2 x i64> @spltConst32kll() {
3842 ; P9BE-LABEL: spltConst32kll:
3843 ; P9BE: # %bb.0: # %entry
3844 ; P9BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
3845 ; P9BE-NEXT: addi r3, r3, .LCPI67_0@toc@l
3846 ; P9BE-NEXT: lxv v2, 0(r3)
3847 ; P9BE-NEXT: blr
3848 ;
3849 ; P9LE-LABEL: spltConst32kll:
3850 ; P9LE: # %bb.0: # %entry
3851 ; P9LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
3852 ; P9LE-NEXT: addi r3, r3, .LCPI67_0@toc@l
3853 ; P9LE-NEXT: lxv v2, 0(r3)
3854 ; P9LE-NEXT: blr
3855 ;
3856 ; P8BE-LABEL: spltConst32kll:
3857 ; P8BE: # %bb.0: # %entry
3858 ; P8BE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
3859 ; P8BE-NEXT: addi r3, r3, .LCPI67_0@toc@l
3860 ; P8BE-NEXT: lxvd2x v2, 0, r3
3861 ; P8BE-NEXT: blr
3862 ;
3863 ; P8LE-LABEL: spltConst32kll:
3864 ; P8LE: # %bb.0: # %entry
3865 ; P8LE-NEXT: addis r3, r2, .LCPI67_0@toc@ha
3866 ; P8LE-NEXT: addi r3, r3, .LCPI67_0@toc@l
3867 ; P8LE-NEXT: lxvd2x v2, 0, r3
3868 ; P8LE-NEXT: blr
3869 entry:
3870 ret <2 x i64> <i64 65535, i64 65535>
3871 }
3873 define <2 x i64> @fromRegsll(i64 %a, i64 %b) {
3874 ; P9BE-LABEL: fromRegsll:
3875 ; P9BE: # %bb.0: # %entry
3876 ; P9BE-NEXT: mtvsrdd v2, r3, r4
3877 ; P9BE-NEXT: blr
3878 ;
3879 ; P9LE-LABEL: fromRegsll:
3880 ; P9LE: # %bb.0: # %entry
3881 ; P9LE-NEXT: mtvsrdd v2, r4, r3
3882 ; P9LE-NEXT: blr
3883 ;
3884 ; P8BE-LABEL: fromRegsll:
3885 ; P8BE: # %bb.0: # %entry
3886 ; P8BE-NEXT: mtfprd f0, r4
3887 ; P8BE-NEXT: mtfprd f1, r3
3888 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
3889 ; P8BE-NEXT: blr
3890 ;
3891 ; P8LE-LABEL: fromRegsll:
3892 ; P8LE: # %bb.0: # %entry
3893 ; P8LE-NEXT: mtfprd f0, r3
3894 ; P8LE-NEXT: mtfprd f1, r4
3895 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
3896 ; P8LE-NEXT: blr
3897 entry:
3898 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
3899 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
3900 ret <2 x i64> %vecinit1
3901 }
3903 define <2 x i64> @fromDiffConstsll() {
3904 ; P9BE-LABEL: fromDiffConstsll:
3905 ; P9BE: # %bb.0: # %entry
3906 ; P9BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
3907 ; P9BE-NEXT: addi r3, r3, .LCPI69_0@toc@l
3908 ; P9BE-NEXT: lxv v2, 0(r3)
3909 ; P9BE-NEXT: blr
3910 ;
3911 ; P9LE-LABEL: fromDiffConstsll:
3912 ; P9LE: # %bb.0: # %entry
3913 ; P9LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
3914 ; P9LE-NEXT: addi r3, r3, .LCPI69_0@toc@l
3915 ; P9LE-NEXT: lxv v2, 0(r3)
3916 ; P9LE-NEXT: blr
3917 ;
3918 ; P8BE-LABEL: fromDiffConstsll:
3919 ; P8BE: # %bb.0: # %entry
3920 ; P8BE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
3921 ; P8BE-NEXT: addi r3, r3, .LCPI69_0@toc@l
3922 ; P8BE-NEXT: lxvd2x v2, 0, r3
3923 ; P8BE-NEXT: blr
3924 ;
3925 ; P8LE-LABEL: fromDiffConstsll:
3926 ; P8LE: # %bb.0: # %entry
3927 ; P8LE-NEXT: addis r3, r2, .LCPI69_0@toc@ha
3928 ; P8LE-NEXT: addi r3, r3, .LCPI69_0@toc@l
3929 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3930 ; P8LE-NEXT: xxswapd v2, vs0
3931 ; P8LE-NEXT: blr
3932 entry:
3933 ret <2 x i64> <i64 242, i64 -113>
3934 }
3936 define <2 x i64> @fromDiffMemConsAll(ptr nocapture readonly %arr) {
3937 ; P9BE-LABEL: fromDiffMemConsAll:
3938 ; P9BE: # %bb.0: # %entry
3939 ; P9BE-NEXT: lxv v2, 0(r3)
3940 ; P9BE-NEXT: blr
3941 ;
3942 ; P9LE-LABEL: fromDiffMemConsAll:
3943 ; P9LE: # %bb.0: # %entry
3944 ; P9LE-NEXT: lxv v2, 0(r3)
3945 ; P9LE-NEXT: blr
3946 ;
3947 ; P8BE-LABEL: fromDiffMemConsAll:
3948 ; P8BE: # %bb.0: # %entry
3949 ; P8BE-NEXT: lxvd2x v2, 0, r3
3950 ; P8BE-NEXT: blr
3951 ;
3952 ; P8LE-LABEL: fromDiffMemConsAll:
3953 ; P8LE: # %bb.0: # %entry
3954 ; P8LE-NEXT: lxvd2x vs0, 0, r3
3955 ; P8LE-NEXT: xxswapd v2, vs0
3956 ; P8LE-NEXT: blr
3957 entry:
3958 %0 = load i64, ptr %arr, align 8
3959 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
3960 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 1
3961 %1 = load i64, ptr %arrayidx1, align 8
3962 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
3963 ret <2 x i64> %vecinit2
3964 }
3966 define <2 x i64> @fromDiffMemConsDll(ptr nocapture readonly %arr) {
3967 ; P9BE-LABEL: fromDiffMemConsDll:
3968 ; P9BE: # %bb.0: # %entry
3969 ; P9BE-NEXT: lxv v2, 16(r3)
3970 ; P9BE-NEXT: xxswapd v2, v2
3971 ; P9BE-NEXT: blr
3972 ;
3973 ; P9LE-LABEL: fromDiffMemConsDll:
3974 ; P9LE: # %bb.0: # %entry
3975 ; P9LE-NEXT: addi r3, r3, 16
3976 ; P9LE-NEXT: lxvd2x v2, 0, r3
3977 ; P9LE-NEXT: blr
3978 ;
3979 ; P8BE-LABEL: fromDiffMemConsDll:
3980 ; P8BE: # %bb.0: # %entry
3981 ; P8BE-NEXT: addi r3, r3, 16
3982 ; P8BE-NEXT: lxvd2x v2, 0, r3
3983 ; P8BE-NEXT: xxswapd v2, v2
3984 ; P8BE-NEXT: blr
3985 ;
3986 ; P8LE-LABEL: fromDiffMemConsDll:
3987 ; P8LE: # %bb.0: # %entry
3988 ; P8LE-NEXT: addi r3, r3, 16
3989 ; P8LE-NEXT: lxvd2x v2, 0, r3
3990 ; P8LE-NEXT: blr
3991 entry:
3992 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 3
3993 %0 = load i64, ptr %arrayidx, align 8
3994 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
3995 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 2
3996 %1 = load i64, ptr %arrayidx1, align 8
3997 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
3998 ret <2 x i64> %vecinit2
3999 }
4001 define <2 x i64> @fromDiffMemVarAll(ptr nocapture readonly %arr, i32 signext %elem) {
4002 ; P9BE-LABEL: fromDiffMemVarAll:
4003 ; P9BE: # %bb.0: # %entry
4004 ; P9BE-NEXT: sldi r4, r4, 3
4005 ; P9BE-NEXT: lxvx v2, r3, r4
4006 ; P9BE-NEXT: blr
4007 ;
4008 ; P9LE-LABEL: fromDiffMemVarAll:
4009 ; P9LE: # %bb.0: # %entry
4010 ; P9LE-NEXT: sldi r4, r4, 3
4011 ; P9LE-NEXT: lxvx v2, r3, r4
4012 ; P9LE-NEXT: blr
4013 ;
4014 ; P8BE-LABEL: fromDiffMemVarAll:
4015 ; P8BE: # %bb.0: # %entry
4016 ; P8BE-NEXT: sldi r4, r4, 3
4017 ; P8BE-NEXT: lxvd2x v2, r3, r4
4018 ; P8BE-NEXT: blr
4019 ;
4020 ; P8LE-LABEL: fromDiffMemVarAll:
4021 ; P8LE: # %bb.0: # %entry
4022 ; P8LE-NEXT: sldi r4, r4, 3
4023 ; P8LE-NEXT: lxvd2x vs0, r3, r4
4024 ; P8LE-NEXT: xxswapd v2, vs0
4025 ; P8LE-NEXT: blr
4026 entry:
4027 %idxprom = sext i32 %elem to i64
4028 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
4029 %0 = load i64, ptr %arrayidx, align 8
4030 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4031 %add = add nsw i32 %elem, 1
4032 %idxprom1 = sext i32 %add to i64
4033 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1
4034 %1 = load i64, ptr %arrayidx2, align 8
4035 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4036 ret <2 x i64> %vecinit3
4037 }
4039 define <2 x i64> @fromDiffMemVarDll(ptr nocapture readonly %arr, i32 signext %elem) {
4040 ; P9BE-LABEL: fromDiffMemVarDll:
4041 ; P9BE: # %bb.0: # %entry
4042 ; P9BE-NEXT: sldi r4, r4, 3
4043 ; P9BE-NEXT: add r3, r3, r4
4044 ; P9BE-NEXT: li r4, -8
4045 ; P9BE-NEXT: lxvx v2, r3, r4
4046 ; P9BE-NEXT: xxswapd v2, v2
4047 ; P9BE-NEXT: blr
4048 ;
4049 ; P9LE-LABEL: fromDiffMemVarDll:
4050 ; P9LE: # %bb.0: # %entry
4051 ; P9LE-NEXT: sldi r4, r4, 3
4052 ; P9LE-NEXT: add r3, r3, r4
4053 ; P9LE-NEXT: addi r3, r3, -8
4054 ; P9LE-NEXT: lxvd2x v2, 0, r3
4055 ; P9LE-NEXT: blr
4056 ;
4057 ; P8BE-LABEL: fromDiffMemVarDll:
4058 ; P8BE: # %bb.0: # %entry
4059 ; P8BE-NEXT: sldi r4, r4, 3
4060 ; P8BE-NEXT: add r3, r3, r4
4061 ; P8BE-NEXT: addi r3, r3, -8
4062 ; P8BE-NEXT: lxvd2x v2, 0, r3
4063 ; P8BE-NEXT: xxswapd v2, v2
4064 ; P8BE-NEXT: blr
4065 ;
4066 ; P8LE-LABEL: fromDiffMemVarDll:
4067 ; P8LE: # %bb.0: # %entry
4068 ; P8LE-NEXT: sldi r4, r4, 3
4069 ; P8LE-NEXT: add r3, r3, r4
4070 ; P8LE-NEXT: addi r3, r3, -8
4071 ; P8LE-NEXT: lxvd2x v2, 0, r3
4072 ; P8LE-NEXT: blr
4073 entry:
4074 %idxprom = sext i32 %elem to i64
4075 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
4076 %0 = load i64, ptr %arrayidx, align 8
4077 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4078 %sub = add nsw i32 %elem, -1
4079 %idxprom1 = sext i32 %sub to i64
4080 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1
4081 %1 = load i64, ptr %arrayidx2, align 8
4082 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4083 ret <2 x i64> %vecinit3
4084 }
4086 define <2 x i64> @fromRandMemConsll(ptr nocapture readonly %arr) {
4087 ; P9BE-LABEL: fromRandMemConsll:
4088 ; P9BE: # %bb.0: # %entry
4089 ; P9BE-NEXT: ld r4, 32(r3)
4090 ; P9BE-NEXT: ld r3, 144(r3)
4091 ; P9BE-NEXT: mtvsrdd v2, r4, r3
4092 ; P9BE-NEXT: blr
4093 ;
4094 ; P9LE-LABEL: fromRandMemConsll:
4095 ; P9LE: # %bb.0: # %entry
4096 ; P9LE-NEXT: ld r4, 32(r3)
4097 ; P9LE-NEXT: ld r3, 144(r3)
4098 ; P9LE-NEXT: mtvsrdd v2, r3, r4
4099 ; P9LE-NEXT: blr
4100 ;
4101 ; P8BE-LABEL: fromRandMemConsll:
4102 ; P8BE: # %bb.0: # %entry
4103 ; P8BE-NEXT: ld r4, 32(r3)
4104 ; P8BE-NEXT: ld r3, 144(r3)
4105 ; P8BE-NEXT: mtfprd f0, r3
4106 ; P8BE-NEXT: mtfprd f1, r4
4107 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
4108 ; P8BE-NEXT: blr
4109 ;
4110 ; P8LE-LABEL: fromRandMemConsll:
4111 ; P8LE: # %bb.0: # %entry
4112 ; P8LE-NEXT: ld r4, 32(r3)
4113 ; P8LE-NEXT: ld r3, 144(r3)
4114 ; P8LE-NEXT: mtfprd f0, r4
4115 ; P8LE-NEXT: mtfprd f1, r3
4116 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
4117 ; P8LE-NEXT: blr
4118 entry:
4119 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 4
4120 %0 = load i64, ptr %arrayidx, align 8
4121 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4122 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 18
4123 %1 = load i64, ptr %arrayidx1, align 8
4124 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4125 ret <2 x i64> %vecinit2
4126 }
4128 define <2 x i64> @fromRandMemVarll(ptr nocapture readonly %arr, i32 signext %elem) {
4129 ; P9BE-LABEL: fromRandMemVarll:
4130 ; P9BE: # %bb.0: # %entry
4131 ; P9BE-NEXT: sldi r4, r4, 3
4132 ; P9BE-NEXT: add r3, r3, r4
4133 ; P9BE-NEXT: ld r4, 32(r3)
4134 ; P9BE-NEXT: ld r3, 8(r3)
4135 ; P9BE-NEXT: mtvsrdd v2, r4, r3
4136 ; P9BE-NEXT: blr
4137 ;
4138 ; P9LE-LABEL: fromRandMemVarll:
4139 ; P9LE: # %bb.0: # %entry
4140 ; P9LE-NEXT: sldi r4, r4, 3
4141 ; P9LE-NEXT: add r3, r3, r4
4142 ; P9LE-NEXT: ld r4, 32(r3)
4143 ; P9LE-NEXT: ld r3, 8(r3)
4144 ; P9LE-NEXT: mtvsrdd v2, r3, r4
4145 ; P9LE-NEXT: blr
4146 ;
4147 ; P8BE-LABEL: fromRandMemVarll:
4148 ; P8BE: # %bb.0: # %entry
4149 ; P8BE-NEXT: sldi r4, r4, 3
4150 ; P8BE-NEXT: add r3, r3, r4
4151 ; P8BE-NEXT: ld r4, 32(r3)
4152 ; P8BE-NEXT: ld r3, 8(r3)
4153 ; P8BE-NEXT: mtfprd f0, r3
4154 ; P8BE-NEXT: mtfprd f1, r4
4155 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
4156 ; P8BE-NEXT: blr
4157 ;
4158 ; P8LE-LABEL: fromRandMemVarll:
4159 ; P8LE: # %bb.0: # %entry
4160 ; P8LE-NEXT: sldi r4, r4, 3
4161 ; P8LE-NEXT: add r3, r3, r4
4162 ; P8LE-NEXT: ld r4, 32(r3)
4163 ; P8LE-NEXT: ld r3, 8(r3)
4164 ; P8LE-NEXT: mtfprd f0, r4
4165 ; P8LE-NEXT: mtfprd f1, r3
4166 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
4167 ; P8LE-NEXT: blr
4168 entry:
4169 %add = add nsw i32 %elem, 4
4170 %idxprom = sext i32 %add to i64
4171 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
4172 %0 = load i64, ptr %arrayidx, align 8
4173 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
4174 %add1 = add nsw i32 %elem, 1
4175 %idxprom2 = sext i32 %add1 to i64
4176 %arrayidx3 = getelementptr inbounds i64, ptr %arr, i64 %idxprom2
4177 %1 = load i64, ptr %arrayidx3, align 8
4178 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
4179 ret <2 x i64> %vecinit4
4180 }
4182 define <2 x i64> @spltRegValll(i64 %val) {
4183 ; P9BE-LABEL: spltRegValll:
4184 ; P9BE: # %bb.0: # %entry
4185 ; P9BE-NEXT: mtvsrdd v2, r3, r3
4186 ; P9BE-NEXT: blr
4187 ;
4188 ; P9LE-LABEL: spltRegValll:
4189 ; P9LE: # %bb.0: # %entry
4190 ; P9LE-NEXT: mtvsrdd v2, r3, r3
4191 ; P9LE-NEXT: blr
4192 ;
4193 ; P8BE-LABEL: spltRegValll:
4194 ; P8BE: # %bb.0: # %entry
4195 ; P8BE-NEXT: mtfprd f0, r3
4196 ; P8BE-NEXT: xxspltd v2, vs0, 0
4197 ; P8BE-NEXT: blr
4198 ;
4199 ; P8LE-LABEL: spltRegValll:
4200 ; P8LE: # %bb.0: # %entry
4201 ; P8LE-NEXT: mtfprd f0, r3
4202 ; P8LE-NEXT: xxspltd v2, vs0, 0
4203 ; P8LE-NEXT: blr
4204 entry:
4205 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0
4206 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4207 ret <2 x i64> %splat.splat
4208 }
4210 define <2 x i64> @spltMemValll(ptr nocapture readonly %ptr) {
4211 ; P9BE-LABEL: spltMemValll:
4212 ; P9BE: # %bb.0: # %entry
4213 ; P9BE-NEXT: lxvdsx v2, 0, r3
4214 ; P9BE-NEXT: blr
4215 ;
4216 ; P9LE-LABEL: spltMemValll:
4217 ; P9LE: # %bb.0: # %entry
4218 ; P9LE-NEXT: lxvdsx v2, 0, r3
4219 ; P9LE-NEXT: blr
4220 ;
4221 ; P8BE-LABEL: spltMemValll:
4222 ; P8BE: # %bb.0: # %entry
4223 ; P8BE-NEXT: lxvdsx v2, 0, r3
4224 ; P8BE-NEXT: blr
4225 ;
4226 ; P8LE-LABEL: spltMemValll:
4227 ; P8LE: # %bb.0: # %entry
4228 ; P8LE-NEXT: lxvdsx v2, 0, r3
4229 ; P8LE-NEXT: blr
4230 entry:
4231 %0 = load i64, ptr %ptr, align 8
4232 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
4233 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4234 ret <2 x i64> %splat.splat
4235 }
4237 define <2 x i64> @spltCnstConvftoll() {
4238 ; P9BE-LABEL: spltCnstConvftoll:
4239 ; P9BE: # %bb.0: # %entry
4240 ; P9BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
4241 ; P9BE-NEXT: addi r3, r3, .LCPI78_0@toc@l
4242 ; P9BE-NEXT: lxv v2, 0(r3)
4243 ; P9BE-NEXT: blr
4244 ;
4245 ; P9LE-LABEL: spltCnstConvftoll:
4246 ; P9LE: # %bb.0: # %entry
4247 ; P9LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
4248 ; P9LE-NEXT: addi r3, r3, .LCPI78_0@toc@l
4249 ; P9LE-NEXT: lxv v2, 0(r3)
4250 ; P9LE-NEXT: blr
4251 ;
4252 ; P8BE-LABEL: spltCnstConvftoll:
4253 ; P8BE: # %bb.0: # %entry
4254 ; P8BE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
4255 ; P8BE-NEXT: addi r3, r3, .LCPI78_0@toc@l
4256 ; P8BE-NEXT: lxvd2x v2, 0, r3
4257 ; P8BE-NEXT: blr
4258 ;
4259 ; P8LE-LABEL: spltCnstConvftoll:
4260 ; P8LE: # %bb.0: # %entry
4261 ; P8LE-NEXT: addis r3, r2, .LCPI78_0@toc@ha
4262 ; P8LE-NEXT: addi r3, r3, .LCPI78_0@toc@l
4263 ; P8LE-NEXT: lxvd2x v2, 0, r3
4264 ; P8LE-NEXT: blr
4265 entry:
4266 ret <2 x i64> <i64 4, i64 4>
4267 }
4269 define <2 x i64> @fromRegsConvftoll(float %a, float %b) {
4270 ; P9BE-LABEL: fromRegsConvftoll:
4271 ; P9BE: # %bb.0: # %entry
4272 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4273 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4274 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
4275 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4276 ; P9BE-NEXT: blr
4277 ;
4278 ; P9LE-LABEL: fromRegsConvftoll:
4279 ; P9LE: # %bb.0: # %entry
4280 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4281 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4282 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
4283 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4284 ; P9LE-NEXT: blr
4285 ;
4286 ; P8BE-LABEL: fromRegsConvftoll:
4287 ; P8BE: # %bb.0: # %entry
4288 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4289 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4290 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
4291 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4292 ; P8BE-NEXT: blr
4293 ;
4294 ; P8LE-LABEL: fromRegsConvftoll:
4295 ; P8LE: # %bb.0: # %entry
4296 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4297 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4298 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
4299 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4300 ; P8LE-NEXT: blr
4301 entry:
4302 %conv = fptosi float %a to i64
4303 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4304 %conv1 = fptosi float %b to i64
4305 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
4306 ret <2 x i64> %vecinit2
4307 }
4309 define <2 x i64> @fromDiffConstsConvftoll() {
4310 ; P9BE-LABEL: fromDiffConstsConvftoll:
4311 ; P9BE: # %bb.0: # %entry
4312 ; P9BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
4313 ; P9BE-NEXT: addi r3, r3, .LCPI80_0@toc@l
4314 ; P9BE-NEXT: lxv v2, 0(r3)
4315 ; P9BE-NEXT: blr
4316 ;
4317 ; P9LE-LABEL: fromDiffConstsConvftoll:
4318 ; P9LE: # %bb.0: # %entry
4319 ; P9LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
4320 ; P9LE-NEXT: addi r3, r3, .LCPI80_0@toc@l
4321 ; P9LE-NEXT: lxv v2, 0(r3)
4322 ; P9LE-NEXT: blr
4323 ;
4324 ; P8BE-LABEL: fromDiffConstsConvftoll:
4325 ; P8BE: # %bb.0: # %entry
4326 ; P8BE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
4327 ; P8BE-NEXT: addi r3, r3, .LCPI80_0@toc@l
4328 ; P8BE-NEXT: lxvd2x v2, 0, r3
4329 ; P8BE-NEXT: blr
4330 ;
4331 ; P8LE-LABEL: fromDiffConstsConvftoll:
4332 ; P8LE: # %bb.0: # %entry
4333 ; P8LE-NEXT: addis r3, r2, .LCPI80_0@toc@ha
4334 ; P8LE-NEXT: addi r3, r3, .LCPI80_0@toc@l
4335 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4336 ; P8LE-NEXT: xxswapd v2, vs0
4337 ; P8LE-NEXT: blr
4338 entry:
4339 ret <2 x i64> <i64 24, i64 234>
4340 }
4342 define <2 x i64> @fromDiffMemConsAConvftoll(ptr nocapture readonly %ptr) {
4343 ; P9BE-LABEL: fromDiffMemConsAConvftoll:
4344 ; P9BE: # %bb.0: # %entry
4345 ; P9BE-NEXT: lfs f0, 0(r3)
4346 ; P9BE-NEXT: lfs f1, 4(r3)
4347 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4348 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4349 ; P9BE-NEXT: blr
4350 ;
4351 ; P9LE-LABEL: fromDiffMemConsAConvftoll:
4352 ; P9LE: # %bb.0: # %entry
4353 ; P9LE-NEXT: lfs f0, 0(r3)
4354 ; P9LE-NEXT: lfs f1, 4(r3)
4355 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4356 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4357 ; P9LE-NEXT: blr
4358 ;
4359 ; P8BE-LABEL: fromDiffMemConsAConvftoll:
4360 ; P8BE: # %bb.0: # %entry
4361 ; P8BE-NEXT: lfs f0, 0(r3)
4362 ; P8BE-NEXT: lfs f1, 4(r3)
4363 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4364 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4365 ; P8BE-NEXT: blr
4366 ;
4367 ; P8LE-LABEL: fromDiffMemConsAConvftoll:
4368 ; P8LE: # %bb.0: # %entry
4369 ; P8LE-NEXT: lfs f0, 0(r3)
4370 ; P8LE-NEXT: lfs f1, 4(r3)
4371 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4372 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4373 ; P8LE-NEXT: blr
4374 entry:
4375 %0 = load float, ptr %ptr, align 4
4376 %conv = fptosi float %0 to i64
4377 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4378 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 1
4379 %1 = load float, ptr %arrayidx1, align 4
4380 %conv2 = fptosi float %1 to i64
4381 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4382 ret <2 x i64> %vecinit3
4383 }
4385 define <2 x i64> @fromDiffMemConsDConvftoll(ptr nocapture readonly %ptr) {
4386 ; P9BE-LABEL: fromDiffMemConsDConvftoll:
4387 ; P9BE: # %bb.0: # %entry
4388 ; P9BE-NEXT: lfs f0, 12(r3)
4389 ; P9BE-NEXT: lfs f1, 8(r3)
4390 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4391 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4392 ; P9BE-NEXT: blr
4393 ;
4394 ; P9LE-LABEL: fromDiffMemConsDConvftoll:
4395 ; P9LE: # %bb.0: # %entry
4396 ; P9LE-NEXT: lfs f0, 12(r3)
4397 ; P9LE-NEXT: lfs f1, 8(r3)
4398 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4399 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4400 ; P9LE-NEXT: blr
4401 ;
4402 ; P8BE-LABEL: fromDiffMemConsDConvftoll:
4403 ; P8BE: # %bb.0: # %entry
4404 ; P8BE-NEXT: lfs f0, 12(r3)
4405 ; P8BE-NEXT: lfs f1, 8(r3)
4406 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4407 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4408 ; P8BE-NEXT: blr
4409 ;
4410 ; P8LE-LABEL: fromDiffMemConsDConvftoll:
4411 ; P8LE: # %bb.0: # %entry
4412 ; P8LE-NEXT: lfs f0, 12(r3)
4413 ; P8LE-NEXT: lfs f1, 8(r3)
4414 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4415 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4416 ; P8LE-NEXT: blr
4417 entry:
4418 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3
4419 %0 = load float, ptr %arrayidx, align 4
4420 %conv = fptosi float %0 to i64
4421 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4422 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2
4423 %1 = load float, ptr %arrayidx1, align 4
4424 %conv2 = fptosi float %1 to i64
4425 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4426 ret <2 x i64> %vecinit3
4427 }
4429 define <2 x i64> @fromDiffMemVarAConvftoll(ptr nocapture readonly %arr, i32 signext %elem) {
4430 ; P9BE-LABEL: fromDiffMemVarAConvftoll:
4431 ; P9BE: # %bb.0: # %entry
4432 ; P9BE-NEXT: sldi r4, r4, 2
4433 ; P9BE-NEXT: lfsux f0, r3, r4
4434 ; P9BE-NEXT: lfs f1, 4(r3)
4435 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4436 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4437 ; P9BE-NEXT: blr
4438 ;
4439 ; P9LE-LABEL: fromDiffMemVarAConvftoll:
4440 ; P9LE: # %bb.0: # %entry
4441 ; P9LE-NEXT: sldi r4, r4, 2
4442 ; P9LE-NEXT: lfsux f0, r3, r4
4443 ; P9LE-NEXT: lfs f1, 4(r3)
4444 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4445 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4446 ; P9LE-NEXT: blr
4447 ;
4448 ; P8BE-LABEL: fromDiffMemVarAConvftoll:
4449 ; P8BE: # %bb.0: # %entry
4450 ; P8BE-NEXT: sldi r4, r4, 2
4451 ; P8BE-NEXT: lfsux f0, r3, r4
4452 ; P8BE-NEXT: lfs f1, 4(r3)
4453 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4454 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4455 ; P8BE-NEXT: blr
4456 ;
4457 ; P8LE-LABEL: fromDiffMemVarAConvftoll:
4458 ; P8LE: # %bb.0: # %entry
4459 ; P8LE-NEXT: sldi r4, r4, 2
4460 ; P8LE-NEXT: lfsux f0, r3, r4
4461 ; P8LE-NEXT: lfs f1, 4(r3)
4462 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4463 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4464 ; P8LE-NEXT: blr
4465 entry:
4466 %idxprom = sext i32 %elem to i64
4467 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
4468 %0 = load float, ptr %arrayidx, align 4
4469 %conv = fptosi float %0 to i64
4470 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4471 %add = add nsw i32 %elem, 1
4472 %idxprom1 = sext i32 %add to i64
4473 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
4474 %1 = load float, ptr %arrayidx2, align 4
4475 %conv3 = fptosi float %1 to i64
4476 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4477 ret <2 x i64> %vecinit4
4478 }
4480 define <2 x i64> @fromDiffMemVarDConvftoll(ptr nocapture readonly %arr, i32 signext %elem) {
4481 ; P9BE-LABEL: fromDiffMemVarDConvftoll:
4482 ; P9BE: # %bb.0: # %entry
4483 ; P9BE-NEXT: sldi r4, r4, 2
4484 ; P9BE-NEXT: lfsux f0, r3, r4
4485 ; P9BE-NEXT: lfs f1, -4(r3)
4486 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
4487 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4488 ; P9BE-NEXT: blr
4489 ;
4490 ; P9LE-LABEL: fromDiffMemVarDConvftoll:
4491 ; P9LE: # %bb.0: # %entry
4492 ; P9LE-NEXT: sldi r4, r4, 2
4493 ; P9LE-NEXT: lfsux f0, r3, r4
4494 ; P9LE-NEXT: lfs f1, -4(r3)
4495 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
4496 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4497 ; P9LE-NEXT: blr
4498 ;
4499 ; P8BE-LABEL: fromDiffMemVarDConvftoll:
4500 ; P8BE: # %bb.0: # %entry
4501 ; P8BE-NEXT: sldi r4, r4, 2
4502 ; P8BE-NEXT: lfsux f0, r3, r4
4503 ; P8BE-NEXT: lfs f1, -4(r3)
4504 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
4505 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4506 ; P8BE-NEXT: blr
4507 ;
4508 ; P8LE-LABEL: fromDiffMemVarDConvftoll:
4509 ; P8LE: # %bb.0: # %entry
4510 ; P8LE-NEXT: sldi r4, r4, 2
4511 ; P8LE-NEXT: lfsux f0, r3, r4
4512 ; P8LE-NEXT: lfs f1, -4(r3)
4513 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
4514 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4515 ; P8LE-NEXT: blr
4516 entry:
4517 %idxprom = sext i32 %elem to i64
4518 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
4519 %0 = load float, ptr %arrayidx, align 4
4520 %conv = fptosi float %0 to i64
4521 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4522 %sub = add nsw i32 %elem, -1
4523 %idxprom1 = sext i32 %sub to i64
4524 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
4525 %1 = load float, ptr %arrayidx2, align 4
4526 %conv3 = fptosi float %1 to i64
4527 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4528 ret <2 x i64> %vecinit4
4529 }
4531 define <2 x i64> @spltRegValConvftoll(float %val) {
4532 ; P9BE-LABEL: spltRegValConvftoll:
4533 ; P9BE: # %bb.0: # %entry
4534 ; P9BE-NEXT: xscvdpsxds f0, f1
4535 ; P9BE-NEXT: xxspltd v2, f0, 0
4536 ; P9BE-NEXT: blr
4537 ;
4538 ; P9LE-LABEL: spltRegValConvftoll:
4539 ; P9LE: # %bb.0: # %entry
4540 ; P9LE-NEXT: xscvdpsxds f0, f1
4541 ; P9LE-NEXT: xxspltd v2, f0, 0
4542 ; P9LE-NEXT: blr
4543 ;
4544 ; P8BE-LABEL: spltRegValConvftoll:
4545 ; P8BE: # %bb.0: # %entry
4546 ; P8BE-NEXT: xscvdpsxds f0, f1
4547 ; P8BE-NEXT: xxspltd v2, f0, 0
4548 ; P8BE-NEXT: blr
4549 ;
4550 ; P8LE-LABEL: spltRegValConvftoll:
4551 ; P8LE: # %bb.0: # %entry
4552 ; P8LE-NEXT: xscvdpsxds f0, f1
4553 ; P8LE-NEXT: xxspltd v2, f0, 0
4554 ; P8LE-NEXT: blr
4555 entry:
4556 %conv = fptosi float %val to i64
4557 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4558 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4559 ret <2 x i64> %splat.splat
4560 }
4562 define <2 x i64> @spltMemValConvftoll(ptr nocapture readonly %ptr) {
4563 ; P9BE-LABEL: spltMemValConvftoll:
4564 ; P9BE: # %bb.0: # %entry
4565 ; P9BE-NEXT: lfs f0, 0(r3)
4566 ; P9BE-NEXT: xscvdpsxds f0, f0
4567 ; P9BE-NEXT: xxspltd v2, f0, 0
4568 ; P9BE-NEXT: blr
4569 ;
4570 ; P9LE-LABEL: spltMemValConvftoll:
4571 ; P9LE: # %bb.0: # %entry
4572 ; P9LE-NEXT: lfs f0, 0(r3)
4573 ; P9LE-NEXT: xscvdpsxds f0, f0
4574 ; P9LE-NEXT: xxspltd v2, vs0, 0
4575 ; P9LE-NEXT: blr
4576 ;
4577 ; P8BE-LABEL: spltMemValConvftoll:
4578 ; P8BE: # %bb.0: # %entry
4579 ; P8BE-NEXT: lfsx f0, 0, r3
4580 ; P8BE-NEXT: xscvdpsxds f0, f0
4581 ; P8BE-NEXT: xxspltd v2, f0, 0
4582 ; P8BE-NEXT: blr
4583 ;
4584 ; P8LE-LABEL: spltMemValConvftoll:
4585 ; P8LE: # %bb.0: # %entry
4586 ; P8LE-NEXT: lfsx f0, 0, r3
4587 ; P8LE-NEXT: xscvdpsxds f0, f0
4588 ; P8LE-NEXT: xxspltd v2, vs0, 0
4589 ; P8LE-NEXT: blr
4590 entry:
4591 %0 = load float, ptr %ptr, align 4
4592 %conv = fptosi float %0 to i64
4593 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4594 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4595 ret <2 x i64> %splat.splat
4596 }
4598 define <2 x i64> @spltCnstConvdtoll() {
4599 ; P9BE-LABEL: spltCnstConvdtoll:
4600 ; P9BE: # %bb.0: # %entry
4601 ; P9BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
4602 ; P9BE-NEXT: addi r3, r3, .LCPI87_0@toc@l
4603 ; P9BE-NEXT: lxv v2, 0(r3)
4604 ; P9BE-NEXT: blr
4605 ;
4606 ; P9LE-LABEL: spltCnstConvdtoll:
4607 ; P9LE: # %bb.0: # %entry
4608 ; P9LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
4609 ; P9LE-NEXT: addi r3, r3, .LCPI87_0@toc@l
4610 ; P9LE-NEXT: lxv v2, 0(r3)
4611 ; P9LE-NEXT: blr
4612 ;
4613 ; P8BE-LABEL: spltCnstConvdtoll:
4614 ; P8BE: # %bb.0: # %entry
4615 ; P8BE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
4616 ; P8BE-NEXT: addi r3, r3, .LCPI87_0@toc@l
4617 ; P8BE-NEXT: lxvd2x v2, 0, r3
4618 ; P8BE-NEXT: blr
4619 ;
4620 ; P8LE-LABEL: spltCnstConvdtoll:
4621 ; P8LE: # %bb.0: # %entry
4622 ; P8LE-NEXT: addis r3, r2, .LCPI87_0@toc@ha
4623 ; P8LE-NEXT: addi r3, r3, .LCPI87_0@toc@l
4624 ; P8LE-NEXT: lxvd2x v2, 0, r3
4625 ; P8LE-NEXT: blr
4626 entry:
4627 ret <2 x i64> <i64 4, i64 4>
4628 }
4630 define <2 x i64> @fromRegsConvdtoll(double %a, double %b) {
4631 ; P9BE-LABEL: fromRegsConvdtoll:
4632 ; P9BE: # %bb.0: # %entry
4633 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4634 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4635 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
4636 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4637 ; P9BE-NEXT: blr
4638 ;
4639 ; P9LE-LABEL: fromRegsConvdtoll:
4640 ; P9LE: # %bb.0: # %entry
4641 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4642 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4643 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
4644 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4645 ; P9LE-NEXT: blr
4646 ;
4647 ; P8BE-LABEL: fromRegsConvdtoll:
4648 ; P8BE: # %bb.0: # %entry
4649 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4650 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4651 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
4652 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4653 ; P8BE-NEXT: blr
4654 ;
4655 ; P8LE-LABEL: fromRegsConvdtoll:
4656 ; P8LE: # %bb.0: # %entry
4657 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
4658 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
4659 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
4660 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4661 ; P8LE-NEXT: blr
4662 entry:
4663 %conv = fptosi double %a to i64
4664 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4665 %conv1 = fptosi double %b to i64
4666 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
4667 ret <2 x i64> %vecinit2
4668 }
4670 define <2 x i64> @fromDiffConstsConvdtoll() {
4671 ; P9BE-LABEL: fromDiffConstsConvdtoll:
4672 ; P9BE: # %bb.0: # %entry
4673 ; P9BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
4674 ; P9BE-NEXT: addi r3, r3, .LCPI89_0@toc@l
4675 ; P9BE-NEXT: lxv v2, 0(r3)
4676 ; P9BE-NEXT: blr
4677 ;
4678 ; P9LE-LABEL: fromDiffConstsConvdtoll:
4679 ; P9LE: # %bb.0: # %entry
4680 ; P9LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
4681 ; P9LE-NEXT: addi r3, r3, .LCPI89_0@toc@l
4682 ; P9LE-NEXT: lxv v2, 0(r3)
4683 ; P9LE-NEXT: blr
4684 ;
4685 ; P8BE-LABEL: fromDiffConstsConvdtoll:
4686 ; P8BE: # %bb.0: # %entry
4687 ; P8BE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
4688 ; P8BE-NEXT: addi r3, r3, .LCPI89_0@toc@l
4689 ; P8BE-NEXT: lxvd2x v2, 0, r3
4690 ; P8BE-NEXT: blr
4691 ;
4692 ; P8LE-LABEL: fromDiffConstsConvdtoll:
4693 ; P8LE: # %bb.0: # %entry
4694 ; P8LE-NEXT: addis r3, r2, .LCPI89_0@toc@ha
4695 ; P8LE-NEXT: addi r3, r3, .LCPI89_0@toc@l
4696 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4697 ; P8LE-NEXT: xxswapd v2, vs0
4698 ; P8LE-NEXT: blr
4699 entry:
4700 ret <2 x i64> <i64 24, i64 234>
4701 }
4703 define <2 x i64> @fromDiffMemConsAConvdtoll(ptr nocapture readonly %ptr) {
4704 ; P9BE-LABEL: fromDiffMemConsAConvdtoll:
4705 ; P9BE: # %bb.0: # %entry
4706 ; P9BE-NEXT: lxv vs0, 0(r3)
4707 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4708 ; P9BE-NEXT: blr
4709 ;
4710 ; P9LE-LABEL: fromDiffMemConsAConvdtoll:
4711 ; P9LE: # %bb.0: # %entry
4712 ; P9LE-NEXT: lxv vs0, 0(r3)
4713 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4714 ; P9LE-NEXT: blr
4715 ;
4716 ; P8BE-LABEL: fromDiffMemConsAConvdtoll:
4717 ; P8BE: # %bb.0: # %entry
4718 ; P8BE-NEXT: lxvd2x vs0, 0, r3
4719 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4720 ; P8BE-NEXT: blr
4721 ;
4722 ; P8LE-LABEL: fromDiffMemConsAConvdtoll:
4723 ; P8LE: # %bb.0: # %entry
4724 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4725 ; P8LE-NEXT: xxswapd vs0, vs0
4726 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4727 ; P8LE-NEXT: blr
4728 entry:
4729 %0 = load <2 x double>, ptr %ptr, align 8
4730 %1 = fptosi <2 x double> %0 to <2 x i64>
4731 ret <2 x i64> %1
4732 }
4734 define <2 x i64> @fromDiffMemConsDConvdtoll(ptr nocapture readonly %ptr) {
4735 ; P9BE-LABEL: fromDiffMemConsDConvdtoll:
4736 ; P9BE: # %bb.0: # %entry
4737 ; P9BE-NEXT: lxv vs0, 16(r3)
4738 ; P9BE-NEXT: xxswapd vs0, vs0
4739 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4740 ; P9BE-NEXT: blr
4741 ;
4742 ; P9LE-LABEL: fromDiffMemConsDConvdtoll:
4743 ; P9LE: # %bb.0: # %entry
4744 ; P9LE-NEXT: addi r3, r3, 16
4745 ; P9LE-NEXT: lxvd2x vs0, 0, r3
4746 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4747 ; P9LE-NEXT: blr
4748 ;
4749 ; P8BE-LABEL: fromDiffMemConsDConvdtoll:
4750 ; P8BE: # %bb.0: # %entry
4751 ; P8BE-NEXT: addi r3, r3, 16
4752 ; P8BE-NEXT: lxvd2x vs0, 0, r3
4753 ; P8BE-NEXT: xxswapd vs0, vs0
4754 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4755 ; P8BE-NEXT: blr
4756 ;
4757 ; P8LE-LABEL: fromDiffMemConsDConvdtoll:
4758 ; P8LE: # %bb.0: # %entry
4759 ; P8LE-NEXT: addi r3, r3, 16
4760 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4761 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4762 ; P8LE-NEXT: blr
4763 entry:
4764 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3
4765 %0 = load double, ptr %arrayidx, align 8
4766 %conv = fptosi double %0 to i64
4767 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4768 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2
4769 %1 = load double, ptr %arrayidx1, align 8
4770 %conv2 = fptosi double %1 to i64
4771 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
4772 ret <2 x i64> %vecinit3
4773 }
4775 define <2 x i64> @fromDiffMemVarAConvdtoll(ptr nocapture readonly %arr, i32 signext %elem) {
4776 ; P9BE-LABEL: fromDiffMemVarAConvdtoll:
4777 ; P9BE: # %bb.0: # %entry
4778 ; P9BE-NEXT: sldi r4, r4, 3
4779 ; P9BE-NEXT: lxvx vs0, r3, r4
4780 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4781 ; P9BE-NEXT: blr
4782 ;
4783 ; P9LE-LABEL: fromDiffMemVarAConvdtoll:
4784 ; P9LE: # %bb.0: # %entry
4785 ; P9LE-NEXT: sldi r4, r4, 3
4786 ; P9LE-NEXT: lxvx vs0, r3, r4
4787 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4788 ; P9LE-NEXT: blr
4789 ;
4790 ; P8BE-LABEL: fromDiffMemVarAConvdtoll:
4791 ; P8BE: # %bb.0: # %entry
4792 ; P8BE-NEXT: sldi r4, r4, 3
4793 ; P8BE-NEXT: lxvd2x vs0, r3, r4
4794 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4795 ; P8BE-NEXT: blr
4796 ;
4797 ; P8LE-LABEL: fromDiffMemVarAConvdtoll:
4798 ; P8LE: # %bb.0: # %entry
4799 ; P8LE-NEXT: sldi r4, r4, 3
4800 ; P8LE-NEXT: lxvd2x vs0, r3, r4
4801 ; P8LE-NEXT: xxswapd vs0, vs0
4802 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4803 ; P8LE-NEXT: blr
4804 entry:
4805 %idxprom = sext i32 %elem to i64
4806 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
4807 %0 = load double, ptr %arrayidx, align 8
4808 %conv = fptosi double %0 to i64
4809 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4810 %add = add nsw i32 %elem, 1
4811 %idxprom1 = sext i32 %add to i64
4812 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
4813 %1 = load double, ptr %arrayidx2, align 8
4814 %conv3 = fptosi double %1 to i64
4815 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4816 ret <2 x i64> %vecinit4
4817 }
4819 define <2 x i64> @fromDiffMemVarDConvdtoll(ptr nocapture readonly %arr, i32 signext %elem) {
4820 ; P9BE-LABEL: fromDiffMemVarDConvdtoll:
4821 ; P9BE: # %bb.0: # %entry
4822 ; P9BE-NEXT: sldi r4, r4, 3
4823 ; P9BE-NEXT: add r3, r3, r4
4824 ; P9BE-NEXT: li r4, -8
4825 ; P9BE-NEXT: lxvx vs0, r3, r4
4826 ; P9BE-NEXT: xxswapd vs0, vs0
4827 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4828 ; P9BE-NEXT: blr
4829 ;
4830 ; P9LE-LABEL: fromDiffMemVarDConvdtoll:
4831 ; P9LE: # %bb.0: # %entry
4832 ; P9LE-NEXT: sldi r4, r4, 3
4833 ; P9LE-NEXT: add r3, r3, r4
4834 ; P9LE-NEXT: addi r3, r3, -8
4835 ; P9LE-NEXT: lxvd2x vs0, 0, r3
4836 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4837 ; P9LE-NEXT: blr
4838 ;
4839 ; P8BE-LABEL: fromDiffMemVarDConvdtoll:
4840 ; P8BE: # %bb.0: # %entry
4841 ; P8BE-NEXT: sldi r4, r4, 3
4842 ; P8BE-NEXT: add r3, r3, r4
4843 ; P8BE-NEXT: addi r3, r3, -8
4844 ; P8BE-NEXT: lxvd2x vs0, 0, r3
4845 ; P8BE-NEXT: xxswapd vs0, vs0
4846 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4847 ; P8BE-NEXT: blr
4848 ;
4849 ; P8LE-LABEL: fromDiffMemVarDConvdtoll:
4850 ; P8LE: # %bb.0: # %entry
4851 ; P8LE-NEXT: sldi r4, r4, 3
4852 ; P8LE-NEXT: add r3, r3, r4
4853 ; P8LE-NEXT: addi r3, r3, -8
4854 ; P8LE-NEXT: lxvd2x vs0, 0, r3
4855 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4856 ; P8LE-NEXT: blr
4857 entry:
4858 %idxprom = sext i32 %elem to i64
4859 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
4860 %0 = load double, ptr %arrayidx, align 8
4861 %conv = fptosi double %0 to i64
4862 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
4863 %sub = add nsw i32 %elem, -1
4864 %idxprom1 = sext i32 %sub to i64
4865 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
4866 %1 = load double, ptr %arrayidx2, align 8
4867 %conv3 = fptosi double %1 to i64
4868 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
4869 ret <2 x i64> %vecinit4
4870 }
4872 define <2 x i64> @spltRegValConvdtoll(double %val) {
4873 ; P9BE-LABEL: spltRegValConvdtoll:
4874 ; P9BE: # %bb.0: # %entry
4875 ; P9BE-NEXT: xscvdpsxds f0, f1
4876 ; P9BE-NEXT: xxspltd v2, vs0, 0
4877 ; P9BE-NEXT: blr
4878 ;
4879 ; P9LE-LABEL: spltRegValConvdtoll:
4880 ; P9LE: # %bb.0: # %entry
4881 ; P9LE-NEXT: xscvdpsxds f0, f1
4882 ; P9LE-NEXT: xxspltd v2, vs0, 0
4883 ; P9LE-NEXT: blr
4884 ;
4885 ; P8BE-LABEL: spltRegValConvdtoll:
4886 ; P8BE: # %bb.0: # %entry
4887 ; P8BE-NEXT: xscvdpsxds f0, f1
4888 ; P8BE-NEXT: xxspltd v2, vs0, 0
4889 ; P8BE-NEXT: blr
4890 ;
4891 ; P8LE-LABEL: spltRegValConvdtoll:
4892 ; P8LE: # %bb.0: # %entry
4893 ; P8LE-NEXT: xscvdpsxds f0, f1
4894 ; P8LE-NEXT: xxspltd v2, vs0, 0
4895 ; P8LE-NEXT: blr
4896 entry:
4897 %conv = fptosi double %val to i64
4898 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4899 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4900 ret <2 x i64> %splat.splat
4901 }
4903 define <2 x i64> @spltMemValConvdtoll(ptr nocapture readonly %ptr) {
4904 ; P9BE-LABEL: spltMemValConvdtoll:
4905 ; P9BE: # %bb.0: # %entry
4906 ; P9BE-NEXT: lxvdsx vs0, 0, r3
4907 ; P9BE-NEXT: xvcvdpsxds v2, vs0
4908 ; P9BE-NEXT: blr
4909 ;
4910 ; P9LE-LABEL: spltMemValConvdtoll:
4911 ; P9LE: # %bb.0: # %entry
4912 ; P9LE-NEXT: lxvdsx vs0, 0, r3
4913 ; P9LE-NEXT: xvcvdpsxds v2, vs0
4914 ; P9LE-NEXT: blr
4915 ;
4916 ; P8BE-LABEL: spltMemValConvdtoll:
4917 ; P8BE: # %bb.0: # %entry
4918 ; P8BE-NEXT: lxvdsx vs0, 0, r3
4919 ; P8BE-NEXT: xvcvdpsxds v2, vs0
4920 ; P8BE-NEXT: blr
4921 ;
4922 ; P8LE-LABEL: spltMemValConvdtoll:
4923 ; P8LE: # %bb.0: # %entry
4924 ; P8LE-NEXT: lxvdsx vs0, 0, r3
4925 ; P8LE-NEXT: xvcvdpsxds v2, vs0
4926 ; P8LE-NEXT: blr
4927 entry:
4928 %0 = load double, ptr %ptr, align 8
4929 %conv = fptosi double %0 to i64
4930 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
4931 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
4932 ret <2 x i64> %splat.splat
4933 }
4935 define <2 x i64> @allZeroull() {
4936 ; P9BE-LABEL: allZeroull:
4937 ; P9BE: # %bb.0: # %entry
4938 ; P9BE-NEXT: xxlxor v2, v2, v2
4939 ; P9BE-NEXT: blr
4940 ;
4941 ; P9LE-LABEL: allZeroull:
4942 ; P9LE: # %bb.0: # %entry
4943 ; P9LE-NEXT: xxlxor v2, v2, v2
4944 ; P9LE-NEXT: blr
4945 ;
4946 ; P8BE-LABEL: allZeroull:
4947 ; P8BE: # %bb.0: # %entry
4948 ; P8BE-NEXT: xxlxor v2, v2, v2
4949 ; P8BE-NEXT: blr
4950 ;
4951 ; P8LE-LABEL: allZeroull:
4952 ; P8LE: # %bb.0: # %entry
4953 ; P8LE-NEXT: xxlxor v2, v2, v2
4954 ; P8LE-NEXT: blr
4955 entry:
4956 ret <2 x i64> zeroinitializer
4957 }
4959 define <2 x i64> @spltConst1ull() {
4960 ; P9BE-LABEL: spltConst1ull:
4961 ; P9BE: # %bb.0: # %entry
4962 ; P9BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
4963 ; P9BE-NEXT: addi r3, r3, .LCPI97_0@toc@l
4964 ; P9BE-NEXT: lxv v2, 0(r3)
4965 ; P9BE-NEXT: blr
4966 ;
4967 ; P9LE-LABEL: spltConst1ull:
4968 ; P9LE: # %bb.0: # %entry
4969 ; P9LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
4970 ; P9LE-NEXT: addi r3, r3, .LCPI97_0@toc@l
4971 ; P9LE-NEXT: lxv v2, 0(r3)
4972 ; P9LE-NEXT: blr
4973 ;
4974 ; P8BE-LABEL: spltConst1ull:
4975 ; P8BE: # %bb.0: # %entry
4976 ; P8BE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
4977 ; P8BE-NEXT: addi r3, r3, .LCPI97_0@toc@l
4978 ; P8BE-NEXT: lxvd2x v2, 0, r3
4979 ; P8BE-NEXT: blr
4980 ;
4981 ; P8LE-LABEL: spltConst1ull:
4982 ; P8LE: # %bb.0: # %entry
4983 ; P8LE-NEXT: addis r3, r2, .LCPI97_0@toc@ha
4984 ; P8LE-NEXT: addi r3, r3, .LCPI97_0@toc@l
4985 ; P8LE-NEXT: lxvd2x v2, 0, r3
4986 ; P8LE-NEXT: blr
4987 entry:
4988 ret <2 x i64> <i64 1, i64 1>
4989 }
4991 define <2 x i64> @spltConst16kull() {
4992 ; P9BE-LABEL: spltConst16kull:
4993 ; P9BE: # %bb.0: # %entry
4994 ; P9BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
4995 ; P9BE-NEXT: addi r3, r3, .LCPI98_0@toc@l
4996 ; P9BE-NEXT: lxv v2, 0(r3)
4997 ; P9BE-NEXT: blr
4998 ;
4999 ; P9LE-LABEL: spltConst16kull:
5000 ; P9LE: # %bb.0: # %entry
5001 ; P9LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
5002 ; P9LE-NEXT: addi r3, r3, .LCPI98_0@toc@l
5003 ; P9LE-NEXT: lxv v2, 0(r3)
5004 ; P9LE-NEXT: blr
5005 ;
5006 ; P8BE-LABEL: spltConst16kull:
5007 ; P8BE: # %bb.0: # %entry
5008 ; P8BE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
5009 ; P8BE-NEXT: addi r3, r3, .LCPI98_0@toc@l
5010 ; P8BE-NEXT: lxvd2x v2, 0, r3
5011 ; P8BE-NEXT: blr
5012 ;
5013 ; P8LE-LABEL: spltConst16kull:
5014 ; P8LE: # %bb.0: # %entry
5015 ; P8LE-NEXT: addis r3, r2, .LCPI98_0@toc@ha
5016 ; P8LE-NEXT: addi r3, r3, .LCPI98_0@toc@l
5017 ; P8LE-NEXT: lxvd2x v2, 0, r3
5018 ; P8LE-NEXT: blr
5019 entry:
5020 ret <2 x i64> <i64 32767, i64 32767>
5021 }
5023 define <2 x i64> @spltConst32kull() {
5024 ; P9BE-LABEL: spltConst32kull:
5025 ; P9BE: # %bb.0: # %entry
5026 ; P9BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
5027 ; P9BE-NEXT: addi r3, r3, .LCPI99_0@toc@l
5028 ; P9BE-NEXT: lxv v2, 0(r3)
5029 ; P9BE-NEXT: blr
5030 ;
5031 ; P9LE-LABEL: spltConst32kull:
5032 ; P9LE: # %bb.0: # %entry
5033 ; P9LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
5034 ; P9LE-NEXT: addi r3, r3, .LCPI99_0@toc@l
5035 ; P9LE-NEXT: lxv v2, 0(r3)
5036 ; P9LE-NEXT: blr
5037 ;
5038 ; P8BE-LABEL: spltConst32kull:
5039 ; P8BE: # %bb.0: # %entry
5040 ; P8BE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
5041 ; P8BE-NEXT: addi r3, r3, .LCPI99_0@toc@l
5042 ; P8BE-NEXT: lxvd2x v2, 0, r3
5043 ; P8BE-NEXT: blr
5044 ;
5045 ; P8LE-LABEL: spltConst32kull:
5046 ; P8LE: # %bb.0: # %entry
5047 ; P8LE-NEXT: addis r3, r2, .LCPI99_0@toc@ha
5048 ; P8LE-NEXT: addi r3, r3, .LCPI99_0@toc@l
5049 ; P8LE-NEXT: lxvd2x v2, 0, r3
5050 ; P8LE-NEXT: blr
5051 entry:
5052 ret <2 x i64> <i64 65535, i64 65535>
5053 }
5055 define <2 x i64> @fromRegsull(i64 %a, i64 %b) {
5056 ; P9BE-LABEL: fromRegsull:
5057 ; P9BE: # %bb.0: # %entry
5058 ; P9BE-NEXT: mtvsrdd v2, r3, r4
5059 ; P9BE-NEXT: blr
5060 ;
5061 ; P9LE-LABEL: fromRegsull:
5062 ; P9LE: # %bb.0: # %entry
5063 ; P9LE-NEXT: mtvsrdd v2, r4, r3
5064 ; P9LE-NEXT: blr
5065 ;
5066 ; P8BE-LABEL: fromRegsull:
5067 ; P8BE: # %bb.0: # %entry
5068 ; P8BE-NEXT: mtfprd f0, r4
5069 ; P8BE-NEXT: mtfprd f1, r3
5070 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
5071 ; P8BE-NEXT: blr
5072 ;
5073 ; P8LE-LABEL: fromRegsull:
5074 ; P8LE: # %bb.0: # %entry
5075 ; P8LE-NEXT: mtfprd f0, r3
5076 ; P8LE-NEXT: mtfprd f1, r4
5077 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
5078 ; P8LE-NEXT: blr
5079 entry:
5080 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
5081 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
5082 ret <2 x i64> %vecinit1
5083 }
5085 define <2 x i64> @fromDiffConstsull() {
5086 ; P9BE-LABEL: fromDiffConstsull:
5087 ; P9BE: # %bb.0: # %entry
5088 ; P9BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5089 ; P9BE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5090 ; P9BE-NEXT: lxv v2, 0(r3)
5091 ; P9BE-NEXT: blr
5092 ;
5093 ; P9LE-LABEL: fromDiffConstsull:
5094 ; P9LE: # %bb.0: # %entry
5095 ; P9LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5096 ; P9LE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5097 ; P9LE-NEXT: lxv v2, 0(r3)
5098 ; P9LE-NEXT: blr
5099 ;
5100 ; P8BE-LABEL: fromDiffConstsull:
5101 ; P8BE: # %bb.0: # %entry
5102 ; P8BE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5103 ; P8BE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5104 ; P8BE-NEXT: lxvd2x v2, 0, r3
5105 ; P8BE-NEXT: blr
5106 ;
5107 ; P8LE-LABEL: fromDiffConstsull:
5108 ; P8LE: # %bb.0: # %entry
5109 ; P8LE-NEXT: addis r3, r2, .LCPI101_0@toc@ha
5110 ; P8LE-NEXT: addi r3, r3, .LCPI101_0@toc@l
5111 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5112 ; P8LE-NEXT: xxswapd v2, vs0
5113 ; P8LE-NEXT: blr
5114 entry:
5115 ret <2 x i64> <i64 242, i64 -113>
5116 }
5118 define <2 x i64> @fromDiffMemConsAull(ptr nocapture readonly %arr) {
5119 ; P9BE-LABEL: fromDiffMemConsAull:
5120 ; P9BE: # %bb.0: # %entry
5121 ; P9BE-NEXT: lxv v2, 0(r3)
5122 ; P9BE-NEXT: blr
5123 ;
5124 ; P9LE-LABEL: fromDiffMemConsAull:
5125 ; P9LE: # %bb.0: # %entry
5126 ; P9LE-NEXT: lxv v2, 0(r3)
5127 ; P9LE-NEXT: blr
5128 ;
5129 ; P8BE-LABEL: fromDiffMemConsAull:
5130 ; P8BE: # %bb.0: # %entry
5131 ; P8BE-NEXT: lxvd2x v2, 0, r3
5132 ; P8BE-NEXT: blr
5133 ;
5134 ; P8LE-LABEL: fromDiffMemConsAull:
5135 ; P8LE: # %bb.0: # %entry
5136 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5137 ; P8LE-NEXT: xxswapd v2, vs0
5138 ; P8LE-NEXT: blr
5139 entry:
5140 %0 = load i64, ptr %arr, align 8
5141 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5142 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 1
5143 %1 = load i64, ptr %arrayidx1, align 8
5144 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5145 ret <2 x i64> %vecinit2
5146 }
5148 define <2 x i64> @fromDiffMemConsDull(ptr nocapture readonly %arr) {
5149 ; P9BE-LABEL: fromDiffMemConsDull:
5150 ; P9BE: # %bb.0: # %entry
5151 ; P9BE-NEXT: lxv v2, 16(r3)
5152 ; P9BE-NEXT: xxswapd v2, v2
5153 ; P9BE-NEXT: blr
5154 ;
5155 ; P9LE-LABEL: fromDiffMemConsDull:
5156 ; P9LE: # %bb.0: # %entry
5157 ; P9LE-NEXT: addi r3, r3, 16
5158 ; P9LE-NEXT: lxvd2x v2, 0, r3
5159 ; P9LE-NEXT: blr
5160 ;
5161 ; P8BE-LABEL: fromDiffMemConsDull:
5162 ; P8BE: # %bb.0: # %entry
5163 ; P8BE-NEXT: addi r3, r3, 16
5164 ; P8BE-NEXT: lxvd2x v2, 0, r3
5165 ; P8BE-NEXT: xxswapd v2, v2
5166 ; P8BE-NEXT: blr
5167 ;
5168 ; P8LE-LABEL: fromDiffMemConsDull:
5169 ; P8LE: # %bb.0: # %entry
5170 ; P8LE-NEXT: addi r3, r3, 16
5171 ; P8LE-NEXT: lxvd2x v2, 0, r3
5172 ; P8LE-NEXT: blr
5173 entry:
5174 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 3
5175 %0 = load i64, ptr %arrayidx, align 8
5176 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5177 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 2
5178 %1 = load i64, ptr %arrayidx1, align 8
5179 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5180 ret <2 x i64> %vecinit2
5181 }
5183 define <2 x i64> @fromDiffMemVarAull(ptr nocapture readonly %arr, i32 signext %elem) {
5184 ; P9BE-LABEL: fromDiffMemVarAull:
5185 ; P9BE: # %bb.0: # %entry
5186 ; P9BE-NEXT: sldi r4, r4, 3
5187 ; P9BE-NEXT: lxvx v2, r3, r4
5188 ; P9BE-NEXT: blr
5189 ;
5190 ; P9LE-LABEL: fromDiffMemVarAull:
5191 ; P9LE: # %bb.0: # %entry
5192 ; P9LE-NEXT: sldi r4, r4, 3
5193 ; P9LE-NEXT: lxvx v2, r3, r4
5194 ; P9LE-NEXT: blr
5195 ;
5196 ; P8BE-LABEL: fromDiffMemVarAull:
5197 ; P8BE: # %bb.0: # %entry
5198 ; P8BE-NEXT: sldi r4, r4, 3
5199 ; P8BE-NEXT: lxvd2x v2, r3, r4
5200 ; P8BE-NEXT: blr
5201 ;
5202 ; P8LE-LABEL: fromDiffMemVarAull:
5203 ; P8LE: # %bb.0: # %entry
5204 ; P8LE-NEXT: sldi r4, r4, 3
5205 ; P8LE-NEXT: lxvd2x vs0, r3, r4
5206 ; P8LE-NEXT: xxswapd v2, vs0
5207 ; P8LE-NEXT: blr
5208 entry:
5209 %idxprom = sext i32 %elem to i64
5210 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
5211 %0 = load i64, ptr %arrayidx, align 8
5212 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5213 %add = add nsw i32 %elem, 1
5214 %idxprom1 = sext i32 %add to i64
5215 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1
5216 %1 = load i64, ptr %arrayidx2, align 8
5217 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5218 ret <2 x i64> %vecinit3
5219 }
5221 define <2 x i64> @fromDiffMemVarDull(ptr nocapture readonly %arr, i32 signext %elem) {
5222 ; P9BE-LABEL: fromDiffMemVarDull:
5223 ; P9BE: # %bb.0: # %entry
5224 ; P9BE-NEXT: sldi r4, r4, 3
5225 ; P9BE-NEXT: add r3, r3, r4
5226 ; P9BE-NEXT: li r4, -8
5227 ; P9BE-NEXT: lxvx v2, r3, r4
5228 ; P9BE-NEXT: xxswapd v2, v2
5229 ; P9BE-NEXT: blr
5230 ;
5231 ; P9LE-LABEL: fromDiffMemVarDull:
5232 ; P9LE: # %bb.0: # %entry
5233 ; P9LE-NEXT: sldi r4, r4, 3
5234 ; P9LE-NEXT: add r3, r3, r4
5235 ; P9LE-NEXT: addi r3, r3, -8
5236 ; P9LE-NEXT: lxvd2x v2, 0, r3
5237 ; P9LE-NEXT: blr
5238 ;
5239 ; P8BE-LABEL: fromDiffMemVarDull:
5240 ; P8BE: # %bb.0: # %entry
5241 ; P8BE-NEXT: sldi r4, r4, 3
5242 ; P8BE-NEXT: add r3, r3, r4
5243 ; P8BE-NEXT: addi r3, r3, -8
5244 ; P8BE-NEXT: lxvd2x v2, 0, r3
5245 ; P8BE-NEXT: xxswapd v2, v2
5246 ; P8BE-NEXT: blr
5247 ;
5248 ; P8LE-LABEL: fromDiffMemVarDull:
5249 ; P8LE: # %bb.0: # %entry
5250 ; P8LE-NEXT: sldi r4, r4, 3
5251 ; P8LE-NEXT: add r3, r3, r4
5252 ; P8LE-NEXT: addi r3, r3, -8
5253 ; P8LE-NEXT: lxvd2x v2, 0, r3
5254 ; P8LE-NEXT: blr
5255 entry:
5256 %idxprom = sext i32 %elem to i64
5257 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
5258 %0 = load i64, ptr %arrayidx, align 8
5259 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5260 %sub = add nsw i32 %elem, -1
5261 %idxprom1 = sext i32 %sub to i64
5262 %arrayidx2 = getelementptr inbounds i64, ptr %arr, i64 %idxprom1
5263 %1 = load i64, ptr %arrayidx2, align 8
5264 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5265 ret <2 x i64> %vecinit3
5266 }
5268 define <2 x i64> @fromRandMemConsull(ptr nocapture readonly %arr) {
5269 ; P9BE-LABEL: fromRandMemConsull:
5270 ; P9BE: # %bb.0: # %entry
5271 ; P9BE-NEXT: ld r4, 32(r3)
5272 ; P9BE-NEXT: ld r3, 144(r3)
5273 ; P9BE-NEXT: mtvsrdd v2, r4, r3
5274 ; P9BE-NEXT: blr
5275 ;
5276 ; P9LE-LABEL: fromRandMemConsull:
5277 ; P9LE: # %bb.0: # %entry
5278 ; P9LE-NEXT: ld r4, 32(r3)
5279 ; P9LE-NEXT: ld r3, 144(r3)
5280 ; P9LE-NEXT: mtvsrdd v2, r3, r4
5281 ; P9LE-NEXT: blr
5282 ;
5283 ; P8BE-LABEL: fromRandMemConsull:
5284 ; P8BE: # %bb.0: # %entry
5285 ; P8BE-NEXT: ld r4, 32(r3)
5286 ; P8BE-NEXT: ld r3, 144(r3)
5287 ; P8BE-NEXT: mtfprd f0, r3
5288 ; P8BE-NEXT: mtfprd f1, r4
5289 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
5290 ; P8BE-NEXT: blr
5291 ;
5292 ; P8LE-LABEL: fromRandMemConsull:
5293 ; P8LE: # %bb.0: # %entry
5294 ; P8LE-NEXT: ld r4, 32(r3)
5295 ; P8LE-NEXT: ld r3, 144(r3)
5296 ; P8LE-NEXT: mtfprd f0, r4
5297 ; P8LE-NEXT: mtfprd f1, r3
5298 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
5299 ; P8LE-NEXT: blr
5300 entry:
5301 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 4
5302 %0 = load i64, ptr %arrayidx, align 8
5303 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5304 %arrayidx1 = getelementptr inbounds i64, ptr %arr, i64 18
5305 %1 = load i64, ptr %arrayidx1, align 8
5306 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5307 ret <2 x i64> %vecinit2
5308 }
5310 define <2 x i64> @fromRandMemVarull(ptr nocapture readonly %arr, i32 signext %elem) {
5311 ; P9BE-LABEL: fromRandMemVarull:
5312 ; P9BE: # %bb.0: # %entry
5313 ; P9BE-NEXT: sldi r4, r4, 3
5314 ; P9BE-NEXT: add r3, r3, r4
5315 ; P9BE-NEXT: ld r4, 32(r3)
5316 ; P9BE-NEXT: ld r3, 8(r3)
5317 ; P9BE-NEXT: mtvsrdd v2, r4, r3
5318 ; P9BE-NEXT: blr
5319 ;
5320 ; P9LE-LABEL: fromRandMemVarull:
5321 ; P9LE: # %bb.0: # %entry
5322 ; P9LE-NEXT: sldi r4, r4, 3
5323 ; P9LE-NEXT: add r3, r3, r4
5324 ; P9LE-NEXT: ld r4, 32(r3)
5325 ; P9LE-NEXT: ld r3, 8(r3)
5326 ; P9LE-NEXT: mtvsrdd v2, r3, r4
5327 ; P9LE-NEXT: blr
5328 ;
5329 ; P8BE-LABEL: fromRandMemVarull:
5330 ; P8BE: # %bb.0: # %entry
5331 ; P8BE-NEXT: sldi r4, r4, 3
5332 ; P8BE-NEXT: add r3, r3, r4
5333 ; P8BE-NEXT: ld r4, 32(r3)
5334 ; P8BE-NEXT: ld r3, 8(r3)
5335 ; P8BE-NEXT: mtfprd f0, r3
5336 ; P8BE-NEXT: mtfprd f1, r4
5337 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
5338 ; P8BE-NEXT: blr
5339 ;
5340 ; P8LE-LABEL: fromRandMemVarull:
5341 ; P8LE: # %bb.0: # %entry
5342 ; P8LE-NEXT: sldi r4, r4, 3
5343 ; P8LE-NEXT: add r3, r3, r4
5344 ; P8LE-NEXT: ld r4, 32(r3)
5345 ; P8LE-NEXT: ld r3, 8(r3)
5346 ; P8LE-NEXT: mtfprd f0, r4
5347 ; P8LE-NEXT: mtfprd f1, r3
5348 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
5349 ; P8LE-NEXT: blr
5350 entry:
5351 %add = add nsw i32 %elem, 4
5352 %idxprom = sext i32 %add to i64
5353 %arrayidx = getelementptr inbounds i64, ptr %arr, i64 %idxprom
5354 %0 = load i64, ptr %arrayidx, align 8
5355 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
5356 %add1 = add nsw i32 %elem, 1
5357 %idxprom2 = sext i32 %add1 to i64
5358 %arrayidx3 = getelementptr inbounds i64, ptr %arr, i64 %idxprom2
5359 %1 = load i64, ptr %arrayidx3, align 8
5360 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %1, i32 1
5361 ret <2 x i64> %vecinit4
5362 }
5364 define <2 x i64> @spltRegValull(i64 %val) {
5365 ; P9BE-LABEL: spltRegValull:
5366 ; P9BE: # %bb.0: # %entry
5367 ; P9BE-NEXT: mtvsrdd v2, r3, r3
5368 ; P9BE-NEXT: blr
5369 ;
5370 ; P9LE-LABEL: spltRegValull:
5371 ; P9LE: # %bb.0: # %entry
5372 ; P9LE-NEXT: mtvsrdd v2, r3, r3
5373 ; P9LE-NEXT: blr
5374 ;
5375 ; P8BE-LABEL: spltRegValull:
5376 ; P8BE: # %bb.0: # %entry
5377 ; P8BE-NEXT: mtfprd f0, r3
5378 ; P8BE-NEXT: xxspltd v2, vs0, 0
5379 ; P8BE-NEXT: blr
5380 ;
5381 ; P8LE-LABEL: spltRegValull:
5382 ; P8LE: # %bb.0: # %entry
5383 ; P8LE-NEXT: mtfprd f0, r3
5384 ; P8LE-NEXT: xxspltd v2, vs0, 0
5385 ; P8LE-NEXT: blr
5386 entry:
5387 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0
5388 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5389 ret <2 x i64> %splat.splat
5390 }
5392 define <2 x i64> @spltMemValull(ptr nocapture readonly %ptr) {
5393 ; P9BE-LABEL: spltMemValull:
5394 ; P9BE: # %bb.0: # %entry
5395 ; P9BE-NEXT: lxvdsx v2, 0, r3
5396 ; P9BE-NEXT: blr
5397 ;
5398 ; P9LE-LABEL: spltMemValull:
5399 ; P9LE: # %bb.0: # %entry
5400 ; P9LE-NEXT: lxvdsx v2, 0, r3
5401 ; P9LE-NEXT: blr
5402 ;
5403 ; P8BE-LABEL: spltMemValull:
5404 ; P8BE: # %bb.0: # %entry
5405 ; P8BE-NEXT: lxvdsx v2, 0, r3
5406 ; P8BE-NEXT: blr
5407 ;
5408 ; P8LE-LABEL: spltMemValull:
5409 ; P8LE: # %bb.0: # %entry
5410 ; P8LE-NEXT: lxvdsx v2, 0, r3
5411 ; P8LE-NEXT: blr
5412 entry:
5413 %0 = load i64, ptr %ptr, align 8
5414 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0
5415 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5416 ret <2 x i64> %splat.splat
5417 }
5419 define <2 x i64> @spltCnstConvftoull() {
5420 ; P9BE-LABEL: spltCnstConvftoull:
5421 ; P9BE: # %bb.0: # %entry
5422 ; P9BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
5423 ; P9BE-NEXT: addi r3, r3, .LCPI110_0@toc@l
5424 ; P9BE-NEXT: lxv v2, 0(r3)
5425 ; P9BE-NEXT: blr
5426 ;
5427 ; P9LE-LABEL: spltCnstConvftoull:
5428 ; P9LE: # %bb.0: # %entry
5429 ; P9LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
5430 ; P9LE-NEXT: addi r3, r3, .LCPI110_0@toc@l
5431 ; P9LE-NEXT: lxv v2, 0(r3)
5432 ; P9LE-NEXT: blr
5433 ;
5434 ; P8BE-LABEL: spltCnstConvftoull:
5435 ; P8BE: # %bb.0: # %entry
5436 ; P8BE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
5437 ; P8BE-NEXT: addi r3, r3, .LCPI110_0@toc@l
5438 ; P8BE-NEXT: lxvd2x v2, 0, r3
5439 ; P8BE-NEXT: blr
5440 ;
5441 ; P8LE-LABEL: spltCnstConvftoull:
5442 ; P8LE: # %bb.0: # %entry
5443 ; P8LE-NEXT: addis r3, r2, .LCPI110_0@toc@ha
5444 ; P8LE-NEXT: addi r3, r3, .LCPI110_0@toc@l
5445 ; P8LE-NEXT: lxvd2x v2, 0, r3
5446 ; P8LE-NEXT: blr
5447 entry:
5448 ret <2 x i64> <i64 4, i64 4>
5449 }
5451 define <2 x i64> @fromRegsConvftoull(float %a, float %b) {
5452 ; P9BE-LABEL: fromRegsConvftoull:
5453 ; P9BE: # %bb.0: # %entry
5454 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5455 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5456 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
5457 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5458 ; P9BE-NEXT: blr
5459 ;
5460 ; P9LE-LABEL: fromRegsConvftoull:
5461 ; P9LE: # %bb.0: # %entry
5462 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5463 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5464 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
5465 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5466 ; P9LE-NEXT: blr
5467 ;
5468 ; P8BE-LABEL: fromRegsConvftoull:
5469 ; P8BE: # %bb.0: # %entry
5470 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5471 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5472 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
5473 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5474 ; P8BE-NEXT: blr
5475 ;
5476 ; P8LE-LABEL: fromRegsConvftoull:
5477 ; P8LE: # %bb.0: # %entry
5478 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5479 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5480 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
5481 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5482 ; P8LE-NEXT: blr
5483 entry:
5484 %conv = fptoui float %a to i64
5485 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5486 %conv1 = fptoui float %b to i64
5487 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
5488 ret <2 x i64> %vecinit2
5489 }
5491 define <2 x i64> @fromDiffConstsConvftoull() {
5492 ; P9BE-LABEL: fromDiffConstsConvftoull:
5493 ; P9BE: # %bb.0: # %entry
5494 ; P9BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
5495 ; P9BE-NEXT: addi r3, r3, .LCPI112_0@toc@l
5496 ; P9BE-NEXT: lxv v2, 0(r3)
5497 ; P9BE-NEXT: blr
5498 ;
5499 ; P9LE-LABEL: fromDiffConstsConvftoull:
5500 ; P9LE: # %bb.0: # %entry
5501 ; P9LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
5502 ; P9LE-NEXT: addi r3, r3, .LCPI112_0@toc@l
5503 ; P9LE-NEXT: lxv v2, 0(r3)
5504 ; P9LE-NEXT: blr
5505 ;
5506 ; P8BE-LABEL: fromDiffConstsConvftoull:
5507 ; P8BE: # %bb.0: # %entry
5508 ; P8BE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
5509 ; P8BE-NEXT: addi r3, r3, .LCPI112_0@toc@l
5510 ; P8BE-NEXT: lxvd2x v2, 0, r3
5511 ; P8BE-NEXT: blr
5512 ;
5513 ; P8LE-LABEL: fromDiffConstsConvftoull:
5514 ; P8LE: # %bb.0: # %entry
5515 ; P8LE-NEXT: addis r3, r2, .LCPI112_0@toc@ha
5516 ; P8LE-NEXT: addi r3, r3, .LCPI112_0@toc@l
5517 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5518 ; P8LE-NEXT: xxswapd v2, vs0
5519 ; P8LE-NEXT: blr
5520 entry:
5521 ret <2 x i64> <i64 24, i64 234>
5522 }
5524 define <2 x i64> @fromDiffMemConsAConvftoull(ptr nocapture readonly %ptr) {
5525 ; P9BE-LABEL: fromDiffMemConsAConvftoull:
5526 ; P9BE: # %bb.0: # %entry
5527 ; P9BE-NEXT: lfs f0, 0(r3)
5528 ; P9BE-NEXT: lfs f1, 4(r3)
5529 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5530 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5531 ; P9BE-NEXT: blr
5532 ;
5533 ; P9LE-LABEL: fromDiffMemConsAConvftoull:
5534 ; P9LE: # %bb.0: # %entry
5535 ; P9LE-NEXT: lfs f0, 0(r3)
5536 ; P9LE-NEXT: lfs f1, 4(r3)
5537 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5538 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5539 ; P9LE-NEXT: blr
5540 ;
5541 ; P8BE-LABEL: fromDiffMemConsAConvftoull:
5542 ; P8BE: # %bb.0: # %entry
5543 ; P8BE-NEXT: lfs f0, 0(r3)
5544 ; P8BE-NEXT: lfs f1, 4(r3)
5545 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5546 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5547 ; P8BE-NEXT: blr
5548 ;
5549 ; P8LE-LABEL: fromDiffMemConsAConvftoull:
5550 ; P8LE: # %bb.0: # %entry
5551 ; P8LE-NEXT: lfs f0, 0(r3)
5552 ; P8LE-NEXT: lfs f1, 4(r3)
5553 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5554 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5555 ; P8LE-NEXT: blr
5556 entry:
5557 %0 = load float, ptr %ptr, align 4
5558 %conv = fptoui float %0 to i64
5559 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5560 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 1
5561 %1 = load float, ptr %arrayidx1, align 4
5562 %conv2 = fptoui float %1 to i64
5563 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
5564 ret <2 x i64> %vecinit3
5565 }
5567 define <2 x i64> @fromDiffMemConsDConvftoull(ptr nocapture readonly %ptr) {
5568 ; P9BE-LABEL: fromDiffMemConsDConvftoull:
5569 ; P9BE: # %bb.0: # %entry
5570 ; P9BE-NEXT: lfs f0, 12(r3)
5571 ; P9BE-NEXT: lfs f1, 8(r3)
5572 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5573 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5574 ; P9BE-NEXT: blr
5575 ;
5576 ; P9LE-LABEL: fromDiffMemConsDConvftoull:
5577 ; P9LE: # %bb.0: # %entry
5578 ; P9LE-NEXT: lfs f0, 12(r3)
5579 ; P9LE-NEXT: lfs f1, 8(r3)
5580 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5581 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5582 ; P9LE-NEXT: blr
5583 ;
5584 ; P8BE-LABEL: fromDiffMemConsDConvftoull:
5585 ; P8BE: # %bb.0: # %entry
5586 ; P8BE-NEXT: lfs f0, 12(r3)
5587 ; P8BE-NEXT: lfs f1, 8(r3)
5588 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5589 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5590 ; P8BE-NEXT: blr
5591 ;
5592 ; P8LE-LABEL: fromDiffMemConsDConvftoull:
5593 ; P8LE: # %bb.0: # %entry
5594 ; P8LE-NEXT: lfs f0, 12(r3)
5595 ; P8LE-NEXT: lfs f1, 8(r3)
5596 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5597 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5598 ; P8LE-NEXT: blr
5599 entry:
5600 %arrayidx = getelementptr inbounds float, ptr %ptr, i64 3
5601 %0 = load float, ptr %arrayidx, align 4
5602 %conv = fptoui float %0 to i64
5603 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5604 %arrayidx1 = getelementptr inbounds float, ptr %ptr, i64 2
5605 %1 = load float, ptr %arrayidx1, align 4
5606 %conv2 = fptoui float %1 to i64
5607 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
5608 ret <2 x i64> %vecinit3
5609 }
5611 define <2 x i64> @fromDiffMemVarAConvftoull(ptr nocapture readonly %arr, i32 signext %elem) {
5612 ; P9BE-LABEL: fromDiffMemVarAConvftoull:
5613 ; P9BE: # %bb.0: # %entry
5614 ; P9BE-NEXT: sldi r4, r4, 2
5615 ; P9BE-NEXT: lfsux f0, r3, r4
5616 ; P9BE-NEXT: lfs f1, 4(r3)
5617 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5618 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5619 ; P9BE-NEXT: blr
5620 ;
5621 ; P9LE-LABEL: fromDiffMemVarAConvftoull:
5622 ; P9LE: # %bb.0: # %entry
5623 ; P9LE-NEXT: sldi r4, r4, 2
5624 ; P9LE-NEXT: lfsux f0, r3, r4
5625 ; P9LE-NEXT: lfs f1, 4(r3)
5626 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5627 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5628 ; P9LE-NEXT: blr
5629 ;
5630 ; P8BE-LABEL: fromDiffMemVarAConvftoull:
5631 ; P8BE: # %bb.0: # %entry
5632 ; P8BE-NEXT: sldi r4, r4, 2
5633 ; P8BE-NEXT: lfsux f0, r3, r4
5634 ; P8BE-NEXT: lfs f1, 4(r3)
5635 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5636 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5637 ; P8BE-NEXT: blr
5638 ;
5639 ; P8LE-LABEL: fromDiffMemVarAConvftoull:
5640 ; P8LE: # %bb.0: # %entry
5641 ; P8LE-NEXT: sldi r4, r4, 2
5642 ; P8LE-NEXT: lfsux f0, r3, r4
5643 ; P8LE-NEXT: lfs f1, 4(r3)
5644 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5645 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5646 ; P8LE-NEXT: blr
5647 entry:
5648 %idxprom = sext i32 %elem to i64
5649 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
5650 %0 = load float, ptr %arrayidx, align 4
5651 %conv = fptoui float %0 to i64
5652 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5653 %add = add nsw i32 %elem, 1
5654 %idxprom1 = sext i32 %add to i64
5655 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
5656 %1 = load float, ptr %arrayidx2, align 4
5657 %conv3 = fptoui float %1 to i64
5658 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
5659 ret <2 x i64> %vecinit4
5660 }
5662 define <2 x i64> @fromDiffMemVarDConvftoull(ptr nocapture readonly %arr, i32 signext %elem) {
5663 ; P9BE-LABEL: fromDiffMemVarDConvftoull:
5664 ; P9BE: # %bb.0: # %entry
5665 ; P9BE-NEXT: sldi r4, r4, 2
5666 ; P9BE-NEXT: lfsux f0, r3, r4
5667 ; P9BE-NEXT: lfs f1, -4(r3)
5668 ; P9BE-NEXT: xxmrghd vs0, vs0, vs1
5669 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5670 ; P9BE-NEXT: blr
5671 ;
5672 ; P9LE-LABEL: fromDiffMemVarDConvftoull:
5673 ; P9LE: # %bb.0: # %entry
5674 ; P9LE-NEXT: sldi r4, r4, 2
5675 ; P9LE-NEXT: lfsux f0, r3, r4
5676 ; P9LE-NEXT: lfs f1, -4(r3)
5677 ; P9LE-NEXT: xxmrghd vs0, vs1, vs0
5678 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5679 ; P9LE-NEXT: blr
5680 ;
5681 ; P8BE-LABEL: fromDiffMemVarDConvftoull:
5682 ; P8BE: # %bb.0: # %entry
5683 ; P8BE-NEXT: sldi r4, r4, 2
5684 ; P8BE-NEXT: lfsux f0, r3, r4
5685 ; P8BE-NEXT: lfs f1, -4(r3)
5686 ; P8BE-NEXT: xxmrghd vs0, vs0, vs1
5687 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5688 ; P8BE-NEXT: blr
5689 ;
5690 ; P8LE-LABEL: fromDiffMemVarDConvftoull:
5691 ; P8LE: # %bb.0: # %entry
5692 ; P8LE-NEXT: sldi r4, r4, 2
5693 ; P8LE-NEXT: lfsux f0, r3, r4
5694 ; P8LE-NEXT: lfs f1, -4(r3)
5695 ; P8LE-NEXT: xxmrghd vs0, vs1, vs0
5696 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5697 ; P8LE-NEXT: blr
5698 entry:
5699 %idxprom = sext i32 %elem to i64
5700 %arrayidx = getelementptr inbounds float, ptr %arr, i64 %idxprom
5701 %0 = load float, ptr %arrayidx, align 4
5702 %conv = fptoui float %0 to i64
5703 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5704 %sub = add nsw i32 %elem, -1
5705 %idxprom1 = sext i32 %sub to i64
5706 %arrayidx2 = getelementptr inbounds float, ptr %arr, i64 %idxprom1
5707 %1 = load float, ptr %arrayidx2, align 4
5708 %conv3 = fptoui float %1 to i64
5709 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
5710 ret <2 x i64> %vecinit4
5711 }
5713 define <2 x i64> @spltRegValConvftoull(float %val) {
5714 ; P9BE-LABEL: spltRegValConvftoull:
5715 ; P9BE: # %bb.0: # %entry
5716 ; P9BE-NEXT: xscvdpuxds f0, f1
5717 ; P9BE-NEXT: xxspltd v2, f0, 0
5718 ; P9BE-NEXT: blr
5719 ;
5720 ; P9LE-LABEL: spltRegValConvftoull:
5721 ; P9LE: # %bb.0: # %entry
5722 ; P9LE-NEXT: xscvdpuxds f0, f1
5723 ; P9LE-NEXT: xxspltd v2, f0, 0
5724 ; P9LE-NEXT: blr
5725 ;
5726 ; P8BE-LABEL: spltRegValConvftoull:
5727 ; P8BE: # %bb.0: # %entry
5728 ; P8BE-NEXT: xscvdpuxds f0, f1
5729 ; P8BE-NEXT: xxspltd v2, f0, 0
5730 ; P8BE-NEXT: blr
5731 ;
5732 ; P8LE-LABEL: spltRegValConvftoull:
5733 ; P8LE: # %bb.0: # %entry
5734 ; P8LE-NEXT: xscvdpuxds f0, f1
5735 ; P8LE-NEXT: xxspltd v2, f0, 0
5736 ; P8LE-NEXT: blr
5737 entry:
5738 %conv = fptoui float %val to i64
5739 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
5740 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5741 ret <2 x i64> %splat.splat
5742 }
5744 define <2 x i64> @spltMemValConvftoull(ptr nocapture readonly %ptr) {
5745 ; P9BE-LABEL: spltMemValConvftoull:
5746 ; P9BE: # %bb.0: # %entry
5747 ; P9BE-NEXT: lfs f0, 0(r3)
5748 ; P9BE-NEXT: xscvdpuxds f0, f0
5749 ; P9BE-NEXT: xxspltd v2, f0, 0
5750 ; P9BE-NEXT: blr
5751 ;
5752 ; P9LE-LABEL: spltMemValConvftoull:
5753 ; P9LE: # %bb.0: # %entry
5754 ; P9LE-NEXT: lfs f0, 0(r3)
5755 ; P9LE-NEXT: xscvdpuxds f0, f0
5756 ; P9LE-NEXT: xxspltd v2, vs0, 0
5757 ; P9LE-NEXT: blr
5758 ;
5759 ; P8BE-LABEL: spltMemValConvftoull:
5760 ; P8BE: # %bb.0: # %entry
5761 ; P8BE-NEXT: lfsx f0, 0, r3
5762 ; P8BE-NEXT: xscvdpuxds f0, f0
5763 ; P8BE-NEXT: xxspltd v2, f0, 0
5764 ; P8BE-NEXT: blr
5765 ;
5766 ; P8LE-LABEL: spltMemValConvftoull:
5767 ; P8LE: # %bb.0: # %entry
5768 ; P8LE-NEXT: lfsx f0, 0, r3
5769 ; P8LE-NEXT: xscvdpuxds f0, f0
5770 ; P8LE-NEXT: xxspltd v2, vs0, 0
5771 ; P8LE-NEXT: blr
5772 entry:
5773 %0 = load float, ptr %ptr, align 4
5774 %conv = fptoui float %0 to i64
5775 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
5776 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
5777 ret <2 x i64> %splat.splat
5778 }
5780 define <2 x i64> @spltCnstConvdtoull() {
5781 ; P9BE-LABEL: spltCnstConvdtoull:
5782 ; P9BE: # %bb.0: # %entry
5783 ; P9BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
5784 ; P9BE-NEXT: addi r3, r3, .LCPI119_0@toc@l
5785 ; P9BE-NEXT: lxv v2, 0(r3)
5786 ; P9BE-NEXT: blr
5787 ;
5788 ; P9LE-LABEL: spltCnstConvdtoull:
5789 ; P9LE: # %bb.0: # %entry
5790 ; P9LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
5791 ; P9LE-NEXT: addi r3, r3, .LCPI119_0@toc@l
5792 ; P9LE-NEXT: lxv v2, 0(r3)
5793 ; P9LE-NEXT: blr
5794 ;
5795 ; P8BE-LABEL: spltCnstConvdtoull:
5796 ; P8BE: # %bb.0: # %entry
5797 ; P8BE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
5798 ; P8BE-NEXT: addi r3, r3, .LCPI119_0@toc@l
5799 ; P8BE-NEXT: lxvd2x v2, 0, r3
5800 ; P8BE-NEXT: blr
5801 ;
5802 ; P8LE-LABEL: spltCnstConvdtoull:
5803 ; P8LE: # %bb.0: # %entry
5804 ; P8LE-NEXT: addis r3, r2, .LCPI119_0@toc@ha
5805 ; P8LE-NEXT: addi r3, r3, .LCPI119_0@toc@l
5806 ; P8LE-NEXT: lxvd2x v2, 0, r3
5807 ; P8LE-NEXT: blr
5808 entry:
5809 ret <2 x i64> <i64 4, i64 4>
5810 }
5812 define <2 x i64> @fromRegsConvdtoull(double %a, double %b) {
5813 ; P9BE-LABEL: fromRegsConvdtoull:
5814 ; P9BE: # %bb.0: # %entry
5815 ; P9BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5816 ; P9BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5817 ; P9BE-NEXT: xxmrghd vs0, vs1, vs2
5818 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5819 ; P9BE-NEXT: blr
5820 ;
5821 ; P9LE-LABEL: fromRegsConvdtoull:
5822 ; P9LE: # %bb.0: # %entry
5823 ; P9LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5824 ; P9LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5825 ; P9LE-NEXT: xxmrghd vs0, vs2, vs1
5826 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5827 ; P9LE-NEXT: blr
5828 ;
5829 ; P8BE-LABEL: fromRegsConvdtoull:
5830 ; P8BE: # %bb.0: # %entry
5831 ; P8BE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5832 ; P8BE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5833 ; P8BE-NEXT: xxmrghd vs0, vs1, vs2
5834 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5835 ; P8BE-NEXT: blr
5836 ;
5837 ; P8LE-LABEL: fromRegsConvdtoull:
5838 ; P8LE: # %bb.0: # %entry
5839 ; P8LE-NEXT: # kill: def $f2 killed $f2 def $vsl2
5840 ; P8LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
5841 ; P8LE-NEXT: xxmrghd vs0, vs2, vs1
5842 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5843 ; P8LE-NEXT: blr
5844 entry:
5845 %conv = fptoui double %a to i64
5846 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5847 %conv1 = fptoui double %b to i64
5848 %vecinit2 = insertelement <2 x i64> %vecinit, i64 %conv1, i32 1
5849 ret <2 x i64> %vecinit2
5850 }
5852 define <2 x i64> @fromDiffConstsConvdtoull() {
5853 ; P9BE-LABEL: fromDiffConstsConvdtoull:
5854 ; P9BE: # %bb.0: # %entry
5855 ; P9BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
5856 ; P9BE-NEXT: addi r3, r3, .LCPI121_0@toc@l
5857 ; P9BE-NEXT: lxv v2, 0(r3)
5858 ; P9BE-NEXT: blr
5859 ;
5860 ; P9LE-LABEL: fromDiffConstsConvdtoull:
5861 ; P9LE: # %bb.0: # %entry
5862 ; P9LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
5863 ; P9LE-NEXT: addi r3, r3, .LCPI121_0@toc@l
5864 ; P9LE-NEXT: lxv v2, 0(r3)
5865 ; P9LE-NEXT: blr
5866 ;
5867 ; P8BE-LABEL: fromDiffConstsConvdtoull:
5868 ; P8BE: # %bb.0: # %entry
5869 ; P8BE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
5870 ; P8BE-NEXT: addi r3, r3, .LCPI121_0@toc@l
5871 ; P8BE-NEXT: lxvd2x v2, 0, r3
5872 ; P8BE-NEXT: blr
5873 ;
5874 ; P8LE-LABEL: fromDiffConstsConvdtoull:
5875 ; P8LE: # %bb.0: # %entry
5876 ; P8LE-NEXT: addis r3, r2, .LCPI121_0@toc@ha
5877 ; P8LE-NEXT: addi r3, r3, .LCPI121_0@toc@l
5878 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5879 ; P8LE-NEXT: xxswapd v2, vs0
5880 ; P8LE-NEXT: blr
5881 entry:
5882 ret <2 x i64> <i64 24, i64 234>
5883 }
5885 define <2 x i64> @fromDiffMemConsAConvdtoull(ptr nocapture readonly %ptr) {
5886 ; P9BE-LABEL: fromDiffMemConsAConvdtoull:
5887 ; P9BE: # %bb.0: # %entry
5888 ; P9BE-NEXT: lxv vs0, 0(r3)
5889 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5890 ; P9BE-NEXT: blr
5891 ;
5892 ; P9LE-LABEL: fromDiffMemConsAConvdtoull:
5893 ; P9LE: # %bb.0: # %entry
5894 ; P9LE-NEXT: lxv vs0, 0(r3)
5895 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5896 ; P9LE-NEXT: blr
5897 ;
5898 ; P8BE-LABEL: fromDiffMemConsAConvdtoull:
5899 ; P8BE: # %bb.0: # %entry
5900 ; P8BE-NEXT: lxvd2x vs0, 0, r3
5901 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5902 ; P8BE-NEXT: blr
5903 ;
5904 ; P8LE-LABEL: fromDiffMemConsAConvdtoull:
5905 ; P8LE: # %bb.0: # %entry
5906 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5907 ; P8LE-NEXT: xxswapd vs0, vs0
5908 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5909 ; P8LE-NEXT: blr
5910 entry:
5911 %0 = load <2 x double>, ptr %ptr, align 8
5912 %1 = fptoui <2 x double> %0 to <2 x i64>
5913 ret <2 x i64> %1
5914 }
5916 define <2 x i64> @fromDiffMemConsDConvdtoull(ptr nocapture readonly %ptr) {
5917 ; P9BE-LABEL: fromDiffMemConsDConvdtoull:
5918 ; P9BE: # %bb.0: # %entry
5919 ; P9BE-NEXT: lxv vs0, 16(r3)
5920 ; P9BE-NEXT: xxswapd vs0, vs0
5921 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5922 ; P9BE-NEXT: blr
5923 ;
5924 ; P9LE-LABEL: fromDiffMemConsDConvdtoull:
5925 ; P9LE: # %bb.0: # %entry
5926 ; P9LE-NEXT: addi r3, r3, 16
5927 ; P9LE-NEXT: lxvd2x vs0, 0, r3
5928 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5929 ; P9LE-NEXT: blr
5930 ;
5931 ; P8BE-LABEL: fromDiffMemConsDConvdtoull:
5932 ; P8BE: # %bb.0: # %entry
5933 ; P8BE-NEXT: addi r3, r3, 16
5934 ; P8BE-NEXT: lxvd2x vs0, 0, r3
5935 ; P8BE-NEXT: xxswapd vs0, vs0
5936 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5937 ; P8BE-NEXT: blr
5938 ;
5939 ; P8LE-LABEL: fromDiffMemConsDConvdtoull:
5940 ; P8LE: # %bb.0: # %entry
5941 ; P8LE-NEXT: addi r3, r3, 16
5942 ; P8LE-NEXT: lxvd2x vs0, 0, r3
5943 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5944 ; P8LE-NEXT: blr
5945 entry:
5946 %arrayidx = getelementptr inbounds double, ptr %ptr, i64 3
5947 %0 = load double, ptr %arrayidx, align 8
5948 %conv = fptoui double %0 to i64
5949 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5950 %arrayidx1 = getelementptr inbounds double, ptr %ptr, i64 2
5951 %1 = load double, ptr %arrayidx1, align 8
5952 %conv2 = fptoui double %1 to i64
5953 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
5954 ret <2 x i64> %vecinit3
5955 }
5957 define <2 x i64> @fromDiffMemVarAConvdtoull(ptr nocapture readonly %arr, i32 signext %elem) {
5958 ; P9BE-LABEL: fromDiffMemVarAConvdtoull:
5959 ; P9BE: # %bb.0: # %entry
5960 ; P9BE-NEXT: sldi r4, r4, 3
5961 ; P9BE-NEXT: lxvx vs0, r3, r4
5962 ; P9BE-NEXT: xvcvdpuxds v2, vs0
5963 ; P9BE-NEXT: blr
5964 ;
5965 ; P9LE-LABEL: fromDiffMemVarAConvdtoull:
5966 ; P9LE: # %bb.0: # %entry
5967 ; P9LE-NEXT: sldi r4, r4, 3
5968 ; P9LE-NEXT: lxvx vs0, r3, r4
5969 ; P9LE-NEXT: xvcvdpuxds v2, vs0
5970 ; P9LE-NEXT: blr
5971 ;
5972 ; P8BE-LABEL: fromDiffMemVarAConvdtoull:
5973 ; P8BE: # %bb.0: # %entry
5974 ; P8BE-NEXT: sldi r4, r4, 3
5975 ; P8BE-NEXT: lxvd2x vs0, r3, r4
5976 ; P8BE-NEXT: xvcvdpuxds v2, vs0
5977 ; P8BE-NEXT: blr
5978 ;
5979 ; P8LE-LABEL: fromDiffMemVarAConvdtoull:
5980 ; P8LE: # %bb.0: # %entry
5981 ; P8LE-NEXT: sldi r4, r4, 3
5982 ; P8LE-NEXT: lxvd2x vs0, r3, r4
5983 ; P8LE-NEXT: xxswapd vs0, vs0
5984 ; P8LE-NEXT: xvcvdpuxds v2, vs0
5985 ; P8LE-NEXT: blr
5986 entry:
5987 %idxprom = sext i32 %elem to i64
5988 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
5989 %0 = load double, ptr %arrayidx, align 8
5990 %conv = fptoui double %0 to i64
5991 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
5992 %add = add nsw i32 %elem, 1
5993 %idxprom1 = sext i32 %add to i64
5994 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
5995 %1 = load double, ptr %arrayidx2, align 8
5996 %conv3 = fptoui double %1 to i64
5997 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
5998 ret <2 x i64> %vecinit4
5999 }
6001 define <2 x i64> @fromDiffMemVarDConvdtoull(ptr nocapture readonly %arr, i32 signext %elem) {
6002 ; P9BE-LABEL: fromDiffMemVarDConvdtoull:
6003 ; P9BE: # %bb.0: # %entry
6004 ; P9BE-NEXT: sldi r4, r4, 3
6005 ; P9BE-NEXT: add r3, r3, r4
6006 ; P9BE-NEXT: li r4, -8
6007 ; P9BE-NEXT: lxvx vs0, r3, r4
6008 ; P9BE-NEXT: xxswapd vs0, vs0
6009 ; P9BE-NEXT: xvcvdpuxds v2, vs0
6010 ; P9BE-NEXT: blr
6011 ;
6012 ; P9LE-LABEL: fromDiffMemVarDConvdtoull:
6013 ; P9LE: # %bb.0: # %entry
6014 ; P9LE-NEXT: sldi r4, r4, 3
6015 ; P9LE-NEXT: add r3, r3, r4
6016 ; P9LE-NEXT: addi r3, r3, -8
6017 ; P9LE-NEXT: lxvd2x vs0, 0, r3
6018 ; P9LE-NEXT: xvcvdpuxds v2, vs0
6019 ; P9LE-NEXT: blr
6020 ;
6021 ; P8BE-LABEL: fromDiffMemVarDConvdtoull:
6022 ; P8BE: # %bb.0: # %entry
6023 ; P8BE-NEXT: sldi r4, r4, 3
6024 ; P8BE-NEXT: add r3, r3, r4
6025 ; P8BE-NEXT: addi r3, r3, -8
6026 ; P8BE-NEXT: lxvd2x vs0, 0, r3
6027 ; P8BE-NEXT: xxswapd vs0, vs0
6028 ; P8BE-NEXT: xvcvdpuxds v2, vs0
6029 ; P8BE-NEXT: blr
6030 ;
6031 ; P8LE-LABEL: fromDiffMemVarDConvdtoull:
6032 ; P8LE: # %bb.0: # %entry
6033 ; P8LE-NEXT: sldi r4, r4, 3
6034 ; P8LE-NEXT: add r3, r3, r4
6035 ; P8LE-NEXT: addi r3, r3, -8
6036 ; P8LE-NEXT: lxvd2x vs0, 0, r3
6037 ; P8LE-NEXT: xvcvdpuxds v2, vs0
6038 ; P8LE-NEXT: blr
6039 entry:
6040 %idxprom = sext i32 %elem to i64
6041 %arrayidx = getelementptr inbounds double, ptr %arr, i64 %idxprom
6042 %0 = load double, ptr %arrayidx, align 8
6043 %conv = fptoui double %0 to i64
6044 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6045 %sub = add nsw i32 %elem, -1
6046 %idxprom1 = sext i32 %sub to i64
6047 %arrayidx2 = getelementptr inbounds double, ptr %arr, i64 %idxprom1
6048 %1 = load double, ptr %arrayidx2, align 8
6049 %conv3 = fptoui double %1 to i64
6050 %vecinit4 = insertelement <2 x i64> %vecinit, i64 %conv3, i32 1
6051 ret <2 x i64> %vecinit4
6052 }
6054 define <2 x i64> @spltRegValConvdtoull(double %val) {
6055 ; P9BE-LABEL: spltRegValConvdtoull:
6056 ; P9BE: # %bb.0: # %entry
6057 ; P9BE-NEXT: xscvdpuxds f0, f1
6058 ; P9BE-NEXT: xxspltd v2, vs0, 0
6059 ; P9BE-NEXT: blr
6060 ;
6061 ; P9LE-LABEL: spltRegValConvdtoull:
6062 ; P9LE: # %bb.0: # %entry
6063 ; P9LE-NEXT: xscvdpuxds f0, f1
6064 ; P9LE-NEXT: xxspltd v2, vs0, 0
6065 ; P9LE-NEXT: blr
6066 ;
6067 ; P8BE-LABEL: spltRegValConvdtoull:
6068 ; P8BE: # %bb.0: # %entry
6069 ; P8BE-NEXT: xscvdpuxds f0, f1
6070 ; P8BE-NEXT: xxspltd v2, vs0, 0
6071 ; P8BE-NEXT: blr
6072 ;
6073 ; P8LE-LABEL: spltRegValConvdtoull:
6074 ; P8LE: # %bb.0: # %entry
6075 ; P8LE-NEXT: xscvdpuxds f0, f1
6076 ; P8LE-NEXT: xxspltd v2, vs0, 0
6077 ; P8LE-NEXT: blr
6078 entry:
6079 %conv = fptoui double %val to i64
6080 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
6081 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
6082 ret <2 x i64> %splat.splat
6083 }
6085 define <2 x i64> @spltMemValConvdtoull(ptr nocapture readonly %ptr) {
6086 ; P9BE-LABEL: spltMemValConvdtoull:
6087 ; P9BE: # %bb.0: # %entry
6088 ; P9BE-NEXT: lxvdsx vs0, 0, r3
6089 ; P9BE-NEXT: xvcvdpuxds v2, vs0
6090 ; P9BE-NEXT: blr
6091 ;
6092 ; P9LE-LABEL: spltMemValConvdtoull:
6093 ; P9LE: # %bb.0: # %entry
6094 ; P9LE-NEXT: lxvdsx vs0, 0, r3
6095 ; P9LE-NEXT: xvcvdpuxds v2, vs0
6096 ; P9LE-NEXT: blr
6097 ;
6098 ; P8BE-LABEL: spltMemValConvdtoull:
6099 ; P8BE: # %bb.0: # %entry
6100 ; P8BE-NEXT: lxvdsx vs0, 0, r3
6101 ; P8BE-NEXT: xvcvdpuxds v2, vs0
6102 ; P8BE-NEXT: blr
6103 ;
6104 ; P8LE-LABEL: spltMemValConvdtoull:
6105 ; P8LE: # %bb.0: # %entry
6106 ; P8LE-NEXT: lxvdsx vs0, 0, r3
6107 ; P8LE-NEXT: xvcvdpuxds v2, vs0
6108 ; P8LE-NEXT: blr
6109 entry:
6110 %0 = load double, ptr %ptr, align 8
6111 %conv = fptoui double %0 to i64
6112 %splat.splatinsert = insertelement <2 x i64> undef, i64 %conv, i32 0
6113 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
6114 ret <2 x i64> %splat.splat
6115 }
6117 ; Some additional patterns that come up in real code.
6118 define dso_local <2 x double> @sint_to_fp_widen02(<4 x i32> %a) {
6119 ; P9BE-LABEL: sint_to_fp_widen02:
6120 ; P9BE: # %bb.0: # %entry
6121 ; P9BE-NEXT: xvcvsxwdp v2, v2
6122 ; P9BE-NEXT: blr
6123 ;
6124 ; P9LE-LABEL: sint_to_fp_widen02:
6125 ; P9LE: # %bb.0: # %entry
6126 ; P9LE-NEXT: xxsldwi vs0, v2, v2, 1
6127 ; P9LE-NEXT: xvcvsxwdp v2, vs0
6128 ; P9LE-NEXT: blr
6129 ;
6130 ; P8BE-LABEL: sint_to_fp_widen02:
6131 ; P8BE: # %bb.0: # %entry
6132 ; P8BE-NEXT: xvcvsxwdp v2, v2
6133 ; P8BE-NEXT: blr
6134 ;
6135 ; P8LE-LABEL: sint_to_fp_widen02:
6136 ; P8LE: # %bb.0: # %entry
6137 ; P8LE-NEXT: xxsldwi vs0, v2, v2, 1
6138 ; P8LE-NEXT: xvcvsxwdp v2, vs0
6139 ; P8LE-NEXT: blr
6140 entry:
6141 %vecext = extractelement <4 x i32> %a, i32 0
6142 %conv = sitofp i32 %vecext to double
6143 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6144 %vecext1 = extractelement <4 x i32> %a, i32 2
6145 %conv2 = sitofp i32 %vecext1 to double
6146 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6147 ret <2 x double> %vecinit3
6148 }
6150 define dso_local <2 x double> @sint_to_fp_widen13(<4 x i32> %a) {
6151 ; P9BE-LABEL: sint_to_fp_widen13:
6152 ; P9BE: # %bb.0: # %entry
6153 ; P9BE-NEXT: xxsldwi vs0, v2, v2, 1
6154 ; P9BE-NEXT: xvcvsxwdp v2, vs0
6155 ; P9BE-NEXT: blr
6156 ;
6157 ; P9LE-LABEL: sint_to_fp_widen13:
6158 ; P9LE: # %bb.0: # %entry
6159 ; P9LE-NEXT: xvcvsxwdp v2, v2
6160 ; P9LE-NEXT: blr
6161 ;
6162 ; P8BE-LABEL: sint_to_fp_widen13:
6163 ; P8BE: # %bb.0: # %entry
6164 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 1
6165 ; P8BE-NEXT: xvcvsxwdp v2, vs0
6166 ; P8BE-NEXT: blr
6167 ;
6168 ; P8LE-LABEL: sint_to_fp_widen13:
6169 ; P8LE: # %bb.0: # %entry
6170 ; P8LE-NEXT: xvcvsxwdp v2, v2
6171 ; P8LE-NEXT: blr
6172 entry:
6173 %vecext = extractelement <4 x i32> %a, i32 1
6174 %conv = sitofp i32 %vecext to double
6175 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6176 %vecext1 = extractelement <4 x i32> %a, i32 3
6177 %conv2 = sitofp i32 %vecext1 to double
6178 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6179 ret <2 x double> %vecinit3
6180 }
6182 define dso_local <2 x double> @uint_to_fp_widen02(<4 x i32> %a) {
6183 ; P9BE-LABEL: uint_to_fp_widen02:
6184 ; P9BE: # %bb.0: # %entry
6185 ; P9BE-NEXT: xvcvuxwdp v2, v2
6186 ; P9BE-NEXT: blr
6187 ;
6188 ; P9LE-LABEL: uint_to_fp_widen02:
6189 ; P9LE: # %bb.0: # %entry
6190 ; P9LE-NEXT: xxsldwi vs0, v2, v2, 1
6191 ; P9LE-NEXT: xvcvuxwdp v2, vs0
6192 ; P9LE-NEXT: blr
6193 ;
6194 ; P8BE-LABEL: uint_to_fp_widen02:
6195 ; P8BE: # %bb.0: # %entry
6196 ; P8BE-NEXT: xvcvuxwdp v2, v2
6197 ; P8BE-NEXT: blr
6198 ;
6199 ; P8LE-LABEL: uint_to_fp_widen02:
6200 ; P8LE: # %bb.0: # %entry
6201 ; P8LE-NEXT: xxsldwi vs0, v2, v2, 1
6202 ; P8LE-NEXT: xvcvuxwdp v2, vs0
6203 ; P8LE-NEXT: blr
6204 entry:
6205 %vecext = extractelement <4 x i32> %a, i32 0
6206 %conv = uitofp i32 %vecext to double
6207 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6208 %vecext1 = extractelement <4 x i32> %a, i32 2
6209 %conv2 = uitofp i32 %vecext1 to double
6210 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6211 ret <2 x double> %vecinit3
6212 }
6214 define dso_local <2 x double> @uint_to_fp_widen13(<4 x i32> %a) {
6215 ; P9BE-LABEL: uint_to_fp_widen13:
6216 ; P9BE: # %bb.0: # %entry
6217 ; P9BE-NEXT: xxsldwi vs0, v2, v2, 1
6218 ; P9BE-NEXT: xvcvuxwdp v2, vs0
6219 ; P9BE-NEXT: blr
6220 ;
6221 ; P9LE-LABEL: uint_to_fp_widen13:
6222 ; P9LE: # %bb.0: # %entry
6223 ; P9LE-NEXT: xvcvuxwdp v2, v2
6224 ; P9LE-NEXT: blr
6225 ;
6226 ; P8BE-LABEL: uint_to_fp_widen13:
6227 ; P8BE: # %bb.0: # %entry
6228 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 1
6229 ; P8BE-NEXT: xvcvuxwdp v2, vs0
6230 ; P8BE-NEXT: blr
6231 ;
6232 ; P8LE-LABEL: uint_to_fp_widen13:
6233 ; P8LE: # %bb.0: # %entry
6234 ; P8LE-NEXT: xvcvuxwdp v2, v2
6235 ; P8LE-NEXT: blr
6236 entry:
6237 %vecext = extractelement <4 x i32> %a, i32 1
6238 %conv = uitofp i32 %vecext to double
6239 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6240 %vecext1 = extractelement <4 x i32> %a, i32 3
6241 %conv2 = uitofp i32 %vecext1 to double
6242 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6243 ret <2 x double> %vecinit3
6244 }
6246 define dso_local <2 x double> @fp_extend01(<4 x float> %a) {
6247 ; P9BE-LABEL: fp_extend01:
6248 ; P9BE: # %bb.0: # %entry
6249 ; P9BE-NEXT: xxmrghw vs0, v2, v2
6250 ; P9BE-NEXT: xvcvspdp v2, vs0
6251 ; P9BE-NEXT: blr
6252 ;
6253 ; P9LE-LABEL: fp_extend01:
6254 ; P9LE: # %bb.0: # %entry
6255 ; P9LE-NEXT: xxmrglw vs0, v2, v2
6256 ; P9LE-NEXT: xvcvspdp v2, vs0
6257 ; P9LE-NEXT: blr
6258 ;
6259 ; P8BE-LABEL: fp_extend01:
6260 ; P8BE: # %bb.0: # %entry
6261 ; P8BE-NEXT: xxmrghw vs0, v2, v2
6262 ; P8BE-NEXT: xvcvspdp v2, vs0
6263 ; P8BE-NEXT: blr
6264 ;
6265 ; P8LE-LABEL: fp_extend01:
6266 ; P8LE: # %bb.0: # %entry
6267 ; P8LE-NEXT: xxmrglw vs0, v2, v2
6268 ; P8LE-NEXT: xvcvspdp v2, vs0
6269 ; P8LE-NEXT: blr
6270 entry:
6271 %vecext = extractelement <4 x float> %a, i32 0
6272 %conv = fpext float %vecext to double
6273 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6274 %vecext1 = extractelement <4 x float> %a, i32 1
6275 %conv2 = fpext float %vecext1 to double
6276 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6277 ret <2 x double> %vecinit3
6278 }
6280 define dso_local <2 x double> @fp_extend10(<4 x float> %a) {
6281 ; P9BE-LABEL: fp_extend10:
6282 ; P9BE: # %bb.0: # %entry
6283 ; P9BE-NEXT: xxmrghw vs0, v2, v2
6284 ; P9BE-NEXT: xvcvspdp vs0, vs0
6285 ; P9BE-NEXT: xxswapd v2, vs0
6286 ; P9BE-NEXT: blr
6287 ;
6288 ; P9LE-LABEL: fp_extend10:
6289 ; P9LE: # %bb.0: # %entry
6290 ; P9LE-NEXT: xxmrglw vs0, v2, v2
6291 ; P9LE-NEXT: xvcvspdp vs0, vs0
6292 ; P9LE-NEXT: xxswapd v2, vs0
6293 ; P9LE-NEXT: blr
6294 ;
6295 ; P8BE-LABEL: fp_extend10:
6296 ; P8BE: # %bb.0: # %entry
6297 ; P8BE-NEXT: xxmrghw vs0, v2, v2
6298 ; P8BE-NEXT: xvcvspdp vs0, vs0
6299 ; P8BE-NEXT: xxswapd v2, vs0
6300 ; P8BE-NEXT: blr
6301 ;
6302 ; P8LE-LABEL: fp_extend10:
6303 ; P8LE: # %bb.0: # %entry
6304 ; P8LE-NEXT: xxmrglw vs0, v2, v2
6305 ; P8LE-NEXT: xvcvspdp vs0, vs0
6306 ; P8LE-NEXT: xxswapd v2, vs0
6307 ; P8LE-NEXT: blr
6308 entry:
6309 %vecext = extractelement <4 x float> %a, i32 1
6310 %conv = fpext float %vecext to double
6311 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6312 %vecext1 = extractelement <4 x float> %a, i32 0
6313 %conv2 = fpext float %vecext1 to double
6314 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6315 ret <2 x double> %vecinit3
6316 }
6318 define dso_local <2 x double> @fp_extend02(<4 x float> %a) {
6319 ; P9BE-LABEL: fp_extend02:
6320 ; P9BE: # %bb.0: # %entry
6321 ; P9BE-NEXT: xvcvspdp v2, v2
6322 ; P9BE-NEXT: blr
6323 ;
6324 ; P9LE-LABEL: fp_extend02:
6325 ; P9LE: # %bb.0: # %entry
6326 ; P9LE-NEXT: xxsldwi vs0, v2, v2, 1
6327 ; P9LE-NEXT: xvcvspdp v2, vs0
6328 ; P9LE-NEXT: blr
6329 ;
6330 ; P8BE-LABEL: fp_extend02:
6331 ; P8BE: # %bb.0: # %entry
6332 ; P8BE-NEXT: xvcvspdp v2, v2
6333 ; P8BE-NEXT: blr
6334 ;
6335 ; P8LE-LABEL: fp_extend02:
6336 ; P8LE: # %bb.0: # %entry
6337 ; P8LE-NEXT: xxsldwi vs0, v2, v2, 1
6338 ; P8LE-NEXT: xvcvspdp v2, vs0
6339 ; P8LE-NEXT: blr
6340 entry:
6341 %vecext = extractelement <4 x float> %a, i32 0
6342 %conv = fpext float %vecext to double
6343 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6344 %vecext1 = extractelement <4 x float> %a, i32 2
6345 %conv2 = fpext float %vecext1 to double
6346 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6347 ret <2 x double> %vecinit3
6348 }
6350 define dso_local <2 x double> @fp_extend13(<4 x float> %a) {
6351 ; P9BE-LABEL: fp_extend13:
6352 ; P9BE: # %bb.0: # %entry
6353 ; P9BE-NEXT: xxsldwi vs0, v2, v2, 1
6354 ; P9BE-NEXT: xvcvspdp v2, vs0
6355 ; P9BE-NEXT: blr
6356 ;
6357 ; P9LE-LABEL: fp_extend13:
6358 ; P9LE: # %bb.0: # %entry
6359 ; P9LE-NEXT: xvcvspdp v2, v2
6360 ; P9LE-NEXT: blr
6361 ;
6362 ; P8BE-LABEL: fp_extend13:
6363 ; P8BE: # %bb.0: # %entry
6364 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 1
6365 ; P8BE-NEXT: xvcvspdp v2, vs0
6366 ; P8BE-NEXT: blr
6367 ;
6368 ; P8LE-LABEL: fp_extend13:
6369 ; P8LE: # %bb.0: # %entry
6370 ; P8LE-NEXT: xvcvspdp v2, v2
6371 ; P8LE-NEXT: blr
6372 entry:
6373 %vecext = extractelement <4 x float> %a, i32 1
6374 %conv = fpext float %vecext to double
6375 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6376 %vecext1 = extractelement <4 x float> %a, i32 3
6377 %conv2 = fpext float %vecext1 to double
6378 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6379 ret <2 x double> %vecinit3
6380 }
6382 define dso_local <2 x double> @fp_extend23(<4 x float> %a) {
6383 ; P9BE-LABEL: fp_extend23:
6384 ; P9BE: # %bb.0: # %entry
6385 ; P9BE-NEXT: xxmrglw vs0, v2, v2
6386 ; P9BE-NEXT: xvcvspdp v2, vs0
6387 ; P9BE-NEXT: blr
6388 ;
6389 ; P9LE-LABEL: fp_extend23:
6390 ; P9LE: # %bb.0: # %entry
6391 ; P9LE-NEXT: xxmrghw vs0, v2, v2
6392 ; P9LE-NEXT: xvcvspdp v2, vs0
6393 ; P9LE-NEXT: blr
6394 ;
6395 ; P8BE-LABEL: fp_extend23:
6396 ; P8BE: # %bb.0: # %entry
6397 ; P8BE-NEXT: xxmrglw vs0, v2, v2
6398 ; P8BE-NEXT: xvcvspdp v2, vs0
6399 ; P8BE-NEXT: blr
6400 ;
6401 ; P8LE-LABEL: fp_extend23:
6402 ; P8LE: # %bb.0: # %entry
6403 ; P8LE-NEXT: xxmrghw vs0, v2, v2
6404 ; P8LE-NEXT: xvcvspdp v2, vs0
6405 ; P8LE-NEXT: blr
6406 entry:
6407 %vecext = extractelement <4 x float> %a, i32 2
6408 %conv = fpext float %vecext to double
6409 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6410 %vecext1 = extractelement <4 x float> %a, i32 3
6411 %conv2 = fpext float %vecext1 to double
6412 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6413 ret <2 x double> %vecinit3
6414 }
6416 define dso_local <2 x double> @fp_extend32(<4 x float> %a) {
6417 ; P9BE-LABEL: fp_extend32:
6418 ; P9BE: # %bb.0: # %entry
6419 ; P9BE-NEXT: xxmrglw vs0, v2, v2
6420 ; P9BE-NEXT: xvcvspdp vs0, vs0
6421 ; P9BE-NEXT: xxswapd v2, vs0
6422 ; P9BE-NEXT: blr
6423 ;
6424 ; P9LE-LABEL: fp_extend32:
6425 ; P9LE: # %bb.0: # %entry
6426 ; P9LE-NEXT: xxmrghw vs0, v2, v2
6427 ; P9LE-NEXT: xvcvspdp vs0, vs0
6428 ; P9LE-NEXT: xxswapd v2, vs0
6429 ; P9LE-NEXT: blr
6430 ;
6431 ; P8BE-LABEL: fp_extend32:
6432 ; P8BE: # %bb.0: # %entry
6433 ; P8BE-NEXT: xxmrglw vs0, v2, v2
6434 ; P8BE-NEXT: xvcvspdp vs0, vs0
6435 ; P8BE-NEXT: xxswapd v2, vs0
6436 ; P8BE-NEXT: blr
6437 ;
6438 ; P8LE-LABEL: fp_extend32:
6439 ; P8LE: # %bb.0: # %entry
6440 ; P8LE-NEXT: xxmrghw vs0, v2, v2
6441 ; P8LE-NEXT: xvcvspdp vs0, vs0
6442 ; P8LE-NEXT: xxswapd v2, vs0
6443 ; P8LE-NEXT: blr
6444 entry:
6445 %vecext = extractelement <4 x float> %a, i32 3
6446 %conv = fpext float %vecext to double
6447 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6448 %vecext1 = extractelement <4 x float> %a, i32 2
6449 %conv2 = fpext float %vecext1 to double
6450 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6451 ret <2 x double> %vecinit3
6452 }
6454 define dso_local <2 x double> @fp_extend_two00(<4 x float> %a, <4 x float> %b) {
6455 ; P9BE-LABEL: fp_extend_two00:
6456 ; P9BE: # %bb.0: # %entry
6457 ; P9BE-NEXT: xxmrghd vs0, v2, v3
6458 ; P9BE-NEXT: xvcvspdp v2, vs0
6459 ; P9BE-NEXT: blr
6460 ;
6461 ; P9LE-LABEL: fp_extend_two00:
6462 ; P9LE: # %bb.0: # %entry
6463 ; P9LE-NEXT: xxmrgld vs0, v3, v2
6464 ; P9LE-NEXT: xxsldwi vs0, vs0, vs0, 1
6465 ; P9LE-NEXT: xvcvspdp v2, vs0
6466 ; P9LE-NEXT: blr
6467 ;
6468 ; P8BE-LABEL: fp_extend_two00:
6469 ; P8BE: # %bb.0: # %entry
6470 ; P8BE-NEXT: xxmrghd vs0, v2, v3
6471 ; P8BE-NEXT: xvcvspdp v2, vs0
6472 ; P8BE-NEXT: blr
6473 ;
6474 ; P8LE-LABEL: fp_extend_two00:
6475 ; P8LE: # %bb.0: # %entry
6476 ; P8LE-NEXT: xxmrgld vs0, v3, v2
6477 ; P8LE-NEXT: xxsldwi vs0, vs0, vs0, 1
6478 ; P8LE-NEXT: xvcvspdp v2, vs0
6479 ; P8LE-NEXT: blr
6480 entry:
6481 %vecext = extractelement <4 x float> %a, i32 0
6482 %conv = fpext float %vecext to double
6483 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6484 %vecext1 = extractelement <4 x float> %b, i32 0
6485 %conv2 = fpext float %vecext1 to double
6486 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6487 ret <2 x double> %vecinit3
6488 }
6490 define dso_local <2 x double> @fp_extend_two33(<4 x float> %a, <4 x float> %b) {
6491 ; P9BE-LABEL: fp_extend_two33:
6492 ; P9BE: # %bb.0: # %entry
6493 ; P9BE-NEXT: xxmrgld vs0, v2, v3
6494 ; P9BE-NEXT: xxsldwi vs0, vs0, vs0, 1
6495 ; P9BE-NEXT: xvcvspdp v2, vs0
6496 ; P9BE-NEXT: blr
6497 ;
6498 ; P9LE-LABEL: fp_extend_two33:
6499 ; P9LE: # %bb.0: # %entry
6500 ; P9LE-NEXT: xxmrghd vs0, v3, v2
6501 ; P9LE-NEXT: xvcvspdp v2, vs0
6502 ; P9LE-NEXT: blr
6503 ;
6504 ; P8BE-LABEL: fp_extend_two33:
6505 ; P8BE: # %bb.0: # %entry
6506 ; P8BE-NEXT: xxmrgld vs0, v2, v3
6507 ; P8BE-NEXT: xxsldwi vs0, vs0, vs0, 1
6508 ; P8BE-NEXT: xvcvspdp v2, vs0
6509 ; P8BE-NEXT: blr
6510 ;
6511 ; P8LE-LABEL: fp_extend_two33:
6512 ; P8LE: # %bb.0: # %entry
6513 ; P8LE-NEXT: xxmrghd vs0, v3, v2
6514 ; P8LE-NEXT: xvcvspdp v2, vs0
6515 ; P8LE-NEXT: blr
6516 entry:
6517 %vecext = extractelement <4 x float> %a, i32 3
6518 %conv = fpext float %vecext to double
6519 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
6520 %vecext1 = extractelement <4 x float> %b, i32 3
6521 %conv2 = fpext float %vecext1 to double
6522 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
6523 ret <2 x double> %vecinit3
6524 }
6526 define dso_local <2 x i64> @test_xvcvspsxds13(<4 x float> %a) local_unnamed_addr {
6527 ; P9BE-LABEL: test_xvcvspsxds13:
6528 ; P9BE: # %bb.0: # %entry
6529 ; P9BE-NEXT: xxsldwi vs0, v2, v2, 1
6530 ; P9BE-NEXT: xvcvspsxds v2, vs0
6531 ; P9BE-NEXT: blr
6532 ;
6533 ; P9LE-LABEL: test_xvcvspsxds13:
6534 ; P9LE: # %bb.0: # %entry
6535 ; P9LE-NEXT: xvcvspsxds v2, v2
6536 ; P9LE-NEXT: blr
6537 ;
6538 ; P8BE-LABEL: test_xvcvspsxds13:
6539 ; P8BE: # %bb.0: # %entry
6540 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 1
6541 ; P8BE-NEXT: xvcvspsxds v2, vs0
6542 ; P8BE-NEXT: blr
6543 ;
6544 ; P8LE-LABEL: test_xvcvspsxds13:
6545 ; P8LE: # %bb.0: # %entry
6546 ; P8LE-NEXT: xvcvspsxds v2, v2
6547 ; P8LE-NEXT: blr
6548 entry:
6549 %vecext = extractelement <4 x float> %a, i32 1
6550 %conv = fptosi float %vecext to i64
6551 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6552 %vecext1 = extractelement <4 x float> %a, i32 3
6553 %conv2 = fptosi float %vecext1 to i64
6554 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
6555 ret <2 x i64> %vecinit3
6556 }
6558 define dso_local <2 x i64> @test_xvcvspuxds13(<4 x float> %a) local_unnamed_addr {
6559 ; P9BE-LABEL: test_xvcvspuxds13:
6560 ; P9BE: # %bb.0: # %entry
6561 ; P9BE-NEXT: xxsldwi vs0, v2, v2, 1
6562 ; P9BE-NEXT: xvcvspuxds v2, vs0
6563 ; P9BE-NEXT: blr
6564 ;
6565 ; P9LE-LABEL: test_xvcvspuxds13:
6566 ; P9LE: # %bb.0: # %entry
6567 ; P9LE-NEXT: xvcvspuxds v2, v2
6568 ; P9LE-NEXT: blr
6569 ;
6570 ; P8BE-LABEL: test_xvcvspuxds13:
6571 ; P8BE: # %bb.0: # %entry
6572 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 1
6573 ; P8BE-NEXT: xvcvspuxds v2, vs0
6574 ; P8BE-NEXT: blr
6575 ;
6576 ; P8LE-LABEL: test_xvcvspuxds13:
6577 ; P8LE: # %bb.0: # %entry
6578 ; P8LE-NEXT: xvcvspuxds v2, v2
6579 ; P8LE-NEXT: blr
6580 entry:
6581 %vecext = extractelement <4 x float> %a, i32 1
6582 %conv = fptoui float %vecext to i64
6583 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6584 %vecext1 = extractelement <4 x float> %a, i32 3
6585 %conv2 = fptoui float %vecext1 to i64
6586 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
6587 ret <2 x i64> %vecinit3
6588 }
6590 define dso_local <2 x i64> @test_xvcvspsxds02(<4 x float> %a) local_unnamed_addr {
6591 ; P9BE-LABEL: test_xvcvspsxds02:
6592 ; P9BE: # %bb.0: # %entry
6593 ; P9BE-NEXT: xvcvspsxds v2, v2
6594 ; P9BE-NEXT: blr
6595 ;
6596 ; P9LE-LABEL: test_xvcvspsxds02:
6597 ; P9LE: # %bb.0: # %entry
6598 ; P9LE-NEXT: xxsldwi vs0, v2, v2, 1
6599 ; P9LE-NEXT: xvcvspsxds v2, vs0
6600 ; P9LE-NEXT: blr
6601 ;
6602 ; P8BE-LABEL: test_xvcvspsxds02:
6603 ; P8BE: # %bb.0: # %entry
6604 ; P8BE-NEXT: xvcvspsxds v2, v2
6605 ; P8BE-NEXT: blr
6606 ;
6607 ; P8LE-LABEL: test_xvcvspsxds02:
6608 ; P8LE: # %bb.0: # %entry
6609 ; P8LE-NEXT: xxsldwi vs0, v2, v2, 1
6610 ; P8LE-NEXT: xvcvspsxds v2, vs0
6611 ; P8LE-NEXT: blr
6612 entry:
6613 %vecext = extractelement <4 x float> %a, i32 0
6614 %conv = fptosi float %vecext to i64
6615 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6616 %vecext1 = extractelement <4 x float> %a, i32 2
6617 %conv2 = fptosi float %vecext1 to i64
6618 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
6619 ret <2 x i64> %vecinit3
6620 }
6622 define dso_local <2 x i64> @test_xvcvspuxds02(<4 x float> %a) local_unnamed_addr {
6623 ; P9BE-LABEL: test_xvcvspuxds02:
6624 ; P9BE: # %bb.0: # %entry
6625 ; P9BE-NEXT: xvcvspuxds v2, v2
6626 ; P9BE-NEXT: blr
6627 ;
6628 ; P9LE-LABEL: test_xvcvspuxds02:
6629 ; P9LE: # %bb.0: # %entry
6630 ; P9LE-NEXT: xxsldwi vs0, v2, v2, 1
6631 ; P9LE-NEXT: xvcvspuxds v2, vs0
6632 ; P9LE-NEXT: blr
6633 ;
6634 ; P8BE-LABEL: test_xvcvspuxds02:
6635 ; P8BE: # %bb.0: # %entry
6636 ; P8BE-NEXT: xvcvspuxds v2, v2
6637 ; P8BE-NEXT: blr
6638 ;
6639 ; P8LE-LABEL: test_xvcvspuxds02:
6640 ; P8LE: # %bb.0: # %entry
6641 ; P8LE-NEXT: xxsldwi vs0, v2, v2, 1
6642 ; P8LE-NEXT: xvcvspuxds v2, vs0
6643 ; P8LE-NEXT: blr
6644 entry:
6645 %vecext = extractelement <4 x float> %a, i32 0
6646 %conv = fptoui float %vecext to i64
6647 %vecinit = insertelement <2 x i64> undef, i64 %conv, i32 0
6648 %vecext1 = extractelement <4 x float> %a, i32 2
6649 %conv2 = fptoui float %vecext1 to i64
6650 %vecinit3 = insertelement <2 x i64> %vecinit, i64 %conv2, i32 1
6651 ret <2 x i64> %vecinit3
6652 }