| blob | 8d03594fe1bfd2ad51ac195ec9deeff4bccc7d62 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \
4 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
5 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \
7 ; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
9 declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
10 declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
11 declare void @foo()
12 define void @intrinsics1(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4, ptr %ptr) {
13 ; CHECK-LABEL: intrinsics1:
14 ; CHECK: # %bb.0:
15 ; CHECK-NEXT: mflr r0
16 ; CHECK-NEXT: std r0, 16(r1)
17 ; CHECK-NEXT: stdu r1, -176(r1)
18 ; CHECK-NEXT: .cfi_def_cfa_offset 176
19 ; CHECK-NEXT: .cfi_offset lr, 16
20 ; CHECK-NEXT: .cfi_offset r30, -16
21 ; CHECK-NEXT: .cfi_offset v28, -80
22 ; CHECK-NEXT: .cfi_offset v29, -64
23 ; CHECK-NEXT: .cfi_offset v30, -48
24 ; CHECK-NEXT: .cfi_offset v31, -32
25 ; CHECK-NEXT: stxv v28, 96(r1) # 16-byte Folded Spill
26 ; CHECK-NEXT: stxv v29, 112(r1) # 16-byte Folded Spill
27 ; CHECK-NEXT: vmr v29, v3
28 ; CHECK-NEXT: vmr v28, v2
29 ; CHECK-NEXT: xxlor vs0, v28, v28
30 ; CHECK-NEXT: stxv v30, 128(r1) # 16-byte Folded Spill
31 ; CHECK-NEXT: stxv v31, 144(r1) # 16-byte Folded Spill
32 ; CHECK-NEXT: vmr v31, v5
33 ; CHECK-NEXT: vmr v30, v4
34 ; CHECK-NEXT: xxlor vs1, v29, v29
35 ; CHECK-NEXT: xxlor vs2, v30, v30
36 ; CHECK-NEXT: xxlor vs3, v31, v31
37 ; CHECK-NEXT: std r30, 160(r1) # 8-byte Folded Spill
38 ; CHECK-NEXT: ld r30, 272(r1)
39 ; CHECK-NEXT: xxmtacc acc0
40 ; CHECK-NEXT: xvf16ger2pp acc0, v2, v4
41 ; CHECK-NEXT: xxmfacc acc0
42 ; CHECK-NEXT: stxvp vsp0, 64(r1)
43 ; CHECK-NEXT: stxvp vsp2, 32(r1)
44 ; CHECK-NEXT: bl foo@notoc
45 ; CHECK-NEXT: lxvp vsp0, 64(r1)
46 ; CHECK-NEXT: lxvp vsp2, 32(r1)
47 ; CHECK-NEXT: xxmtacc acc0
48 ; CHECK-NEXT: xvf16ger2pp acc0, v28, v30
49 ; CHECK-NEXT: lxv v31, 144(r1) # 16-byte Folded Reload
50 ; CHECK-NEXT: lxv v30, 128(r1) # 16-byte Folded Reload
51 ; CHECK-NEXT: lxv v29, 112(r1) # 16-byte Folded Reload
52 ; CHECK-NEXT: lxv v28, 96(r1) # 16-byte Folded Reload
53 ; CHECK-NEXT: xxmfacc acc0
54 ; CHECK-NEXT: stxv vs0, 48(r30)
55 ; CHECK-NEXT: stxv vs1, 32(r30)
56 ; CHECK-NEXT: stxv vs2, 16(r30)
57 ; CHECK-NEXT: stxv vs3, 0(r30)
58 ; CHECK-NEXT: ld r30, 160(r1) # 8-byte Folded Reload
59 ; CHECK-NEXT: addi r1, r1, 176
60 ; CHECK-NEXT: ld r0, 16(r1)
61 ; CHECK-NEXT: mtlr r0
62 ; CHECK-NEXT: blr
63 ;
64 ; CHECK-BE-LABEL: intrinsics1:
65 ; CHECK-BE: # %bb.0:
66 ; CHECK-BE-NEXT: mflr r0
67 ; CHECK-BE-NEXT: std r0, 16(r1)
68 ; CHECK-BE-NEXT: stdu r1, -256(r1)
69 ; CHECK-BE-NEXT: .cfi_def_cfa_offset 256
70 ; CHECK-BE-NEXT: .cfi_offset lr, 16
71 ; CHECK-BE-NEXT: .cfi_offset r30, -16
72 ; CHECK-BE-NEXT: .cfi_offset v28, -80
73 ; CHECK-BE-NEXT: .cfi_offset v29, -64
74 ; CHECK-BE-NEXT: .cfi_offset v30, -48
75 ; CHECK-BE-NEXT: .cfi_offset v31, -32
76 ; CHECK-BE-NEXT: stxv v28, 176(r1) # 16-byte Folded Spill
77 ; CHECK-BE-NEXT: stxv v29, 192(r1) # 16-byte Folded Spill
78 ; CHECK-BE-NEXT: vmr v29, v3
79 ; CHECK-BE-NEXT: vmr v28, v2
80 ; CHECK-BE-NEXT: xxlor vs0, v28, v28
81 ; CHECK-BE-NEXT: stxv v30, 208(r1) # 16-byte Folded Spill
82 ; CHECK-BE-NEXT: stxv v31, 224(r1) # 16-byte Folded Spill
83 ; CHECK-BE-NEXT: vmr v31, v5
84 ; CHECK-BE-NEXT: vmr v30, v4
85 ; CHECK-BE-NEXT: xxlor vs1, v29, v29
86 ; CHECK-BE-NEXT: xxlor vs2, v30, v30
87 ; CHECK-BE-NEXT: xxlor vs3, v31, v31
88 ; CHECK-BE-NEXT: std r30, 240(r1) # 8-byte Folded Spill
89 ; CHECK-BE-NEXT: ld r30, 368(r1)
90 ; CHECK-BE-NEXT: xxmtacc acc0
91 ; CHECK-BE-NEXT: xvf16ger2pp acc0, v2, v4
92 ; CHECK-BE-NEXT: xxmfacc acc0
93 ; CHECK-BE-NEXT: stxvp vsp0, 112(r1)
94 ; CHECK-BE-NEXT: stxvp vsp2, 144(r1)
95 ; CHECK-BE-NEXT: bl foo
96 ; CHECK-BE-NEXT: nop
97 ; CHECK-BE-NEXT: lxvp vsp0, 112(r1)
98 ; CHECK-BE-NEXT: lxvp vsp2, 144(r1)
99 ; CHECK-BE-NEXT: xxmtacc acc0
100 ; CHECK-BE-NEXT: xvf16ger2pp acc0, v28, v30
101 ; CHECK-BE-NEXT: lxv v31, 224(r1) # 16-byte Folded Reload
102 ; CHECK-BE-NEXT: lxv v30, 208(r1) # 16-byte Folded Reload
103 ; CHECK-BE-NEXT: lxv v29, 192(r1) # 16-byte Folded Reload
104 ; CHECK-BE-NEXT: lxv v28, 176(r1) # 16-byte Folded Reload
105 ; CHECK-BE-NEXT: xxmfacc acc0
106 ; CHECK-BE-NEXT: stxv vs1, 16(r30)
107 ; CHECK-BE-NEXT: stxv vs0, 0(r30)
108 ; CHECK-BE-NEXT: stxv vs3, 48(r30)
109 ; CHECK-BE-NEXT: stxv vs2, 32(r30)
110 ; CHECK-BE-NEXT: ld r30, 240(r1) # 8-byte Folded Reload
111 ; CHECK-BE-NEXT: addi r1, r1, 256
112 ; CHECK-BE-NEXT: ld r0, 16(r1)
113 ; CHECK-BE-NEXT: mtlr r0
114 ; CHECK-BE-NEXT: blr
115 %1 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc1, <16 x i8> %vc2, <16 x i8> %vc3, <16 x i8> %vc4)
116 %2 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %1, <16 x i8> %vc1, <16 x i8> %vc3)
117 tail call void @foo()
118 %3 = tail call <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1> %2, <16 x i8> %vc1, <16 x i8> %vc3)
119 store <512 x i1> %3, ptr %ptr, align 64
120 ret void
121 }