[llvm-project.git] / llvm / test / CodeGen / RISCV / GlobalISel / irtranslator / calling-conv-ilp32d.ll
| blob | e33e279f7f48978e563c76b86bda806d534400a3 |
1 ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
2 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \
3 ; RUN: -global-isel -stop-after=irtranslator -verify-machineinstrs < %s \
4 ; RUN: | FileCheck -check-prefix=RV32-ILP32D %s
6 ; This file contains tests that will have differing output for the ilp32/ilp32f
7 ; and ilp32d ABIs.
9 define i32 @callee_double_in_fpr(i32 %a, double %b) nounwind {
10 ; RV32-ILP32D-LABEL: name: callee_double_in_fpr
11 ; RV32-ILP32D: bb.1 (%ir-block.0):
12 ; RV32-ILP32D-NEXT: liveins: $x10, $f10_d
13 ; RV32-ILP32D-NEXT: {{ $}}
14 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
15 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f10_d
16 ; RV32-ILP32D-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY1]](s64)
17 ; RV32-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[FPTOSI]]
18 ; RV32-ILP32D-NEXT: $x10 = COPY [[ADD]](s32)
19 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
20 %b_fptosi = fptosi double %b to i32
21 %1 = add i32 %a, %b_fptosi
22 ret i32 %1
23 }
25 define i32 @caller_double_in_fpr() nounwind {
26 ; RV32-ILP32D-LABEL: name: caller_double_in_fpr
27 ; RV32-ILP32D: bb.1 (%ir-block.0):
28 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
29 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
30 ; RV32-ILP32D-NEXT: $x10 = COPY [[C]](s32)
31 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C1]](s64)
32 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr, implicit-def $x1, implicit $x10, implicit $f10_d, implicit-def $x10
33 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
34 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32)
35 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
36 %1 = call i32 @callee_double_in_fpr(i32 1, double 2.0)
37 ret i32 %1
38 }
40 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
41 define i32 @callee_double_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, double %f) nounwind {
42 ; RV32-ILP32D-LABEL: name: callee_double_in_fpr_exhausted_gprs
43 ; RV32-ILP32D: bb.1 (%ir-block.0):
44 ; RV32-ILP32D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_d
45 ; RV32-ILP32D-NEXT: {{ $}}
46 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
47 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
48 ; RV32-ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
49 ; RV32-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x12
50 ; RV32-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x13
51 ; RV32-ILP32D-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
52 ; RV32-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x14
53 ; RV32-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $x15
54 ; RV32-ILP32D-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
55 ; RV32-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x16
56 ; RV32-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x17
57 ; RV32-ILP32D-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
58 ; RV32-ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
59 ; RV32-ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16)
60 ; RV32-ILP32D-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $f10_d
61 ; RV32-ILP32D-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY8]](s64)
62 ; RV32-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD]], [[FPTOSI]]
63 ; RV32-ILP32D-NEXT: $x10 = COPY [[ADD]](s32)
64 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
65 %f_fptosi = fptosi double %f to i32
66 %1 = add i32 %e, %f_fptosi
67 ret i32 %1
68 }
70 define i32 @caller_double_in_fpr_exhausted_gprs() nounwind {
71 ; RV32-ILP32D-LABEL: name: caller_double_in_fpr_exhausted_gprs
72 ; RV32-ILP32D: bb.1 (%ir-block.0):
73 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
74 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
75 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
76 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
77 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
78 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s64) = G_FCONSTANT double 6.000000e+00
79 ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
80 ; RV32-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C1]](s64)
81 ; RV32-ILP32D-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
82 ; RV32-ILP32D-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C3]](s64)
83 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
84 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
85 ; RV32-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C6]](s32)
86 ; RV32-ILP32D-NEXT: G_STORE [[C4]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
87 ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)
88 ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)
89 ; RV32-ILP32D-NEXT: $x12 = COPY [[UV2]](s32)
90 ; RV32-ILP32D-NEXT: $x13 = COPY [[UV3]](s32)
91 ; RV32-ILP32D-NEXT: $x14 = COPY [[UV4]](s32)
92 ; RV32-ILP32D-NEXT: $x15 = COPY [[UV5]](s32)
93 ; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32)
94 ; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32)
95 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C5]](s64)
96 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_fpr_exhausted_gprs, implicit-def $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit $f10_d, implicit-def $x10
97 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
98 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)
99 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
100 %1 = call i32 @callee_double_in_fpr_exhausted_gprs(
101 i64 1, i64 2, i64 3, i64 4, i32 5, double 6.0)
102 ret i32 %1
103 }
105 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
106 define i32 @callee_double_in_gpr_exhausted_fprs(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i) nounwind {
107 ; RV32-ILP32D-LABEL: name: callee_double_in_gpr_exhausted_fprs
108 ; RV32-ILP32D: bb.1 (%ir-block.0):
109 ; RV32-ILP32D-NEXT: liveins: $x10, $x11, $f10_d, $f11_d, $f12_d, $f13_d, $f14_d, $f15_d, $f16_d, $f17_d
110 ; RV32-ILP32D-NEXT: {{ $}}
111 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
112 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $f11_d
113 ; RV32-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f12_d
114 ; RV32-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $f13_d
115 ; RV32-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $f14_d
116 ; RV32-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $f15_d
117 ; RV32-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $f16_d
118 ; RV32-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $f17_d
119 ; RV32-ILP32D-NEXT: [[COPY8:%[0-9]+]]:_(s32) = COPY $x10
120 ; RV32-ILP32D-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x11
121 ; RV32-ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY8]](s32), [[COPY9]](s32)
122 ; RV32-ILP32D-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY7]](s64)
123 ; RV32-ILP32D-NEXT: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[MV]](s64)
124 ; RV32-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[FPTOSI]], [[FPTOSI1]]
125 ; RV32-ILP32D-NEXT: $x10 = COPY [[ADD]](s32)
126 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
127 %h_fptosi = fptosi double %h to i32
128 %i_fptosi = fptosi double %i to i32
129 %1 = add i32 %h_fptosi, %i_fptosi
130 ret i32 %1
131 }
133 define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
134 ; RV32-ILP32D-LABEL: name: caller_double_in_gpr_exhausted_fprs
135 ; RV32-ILP32D: bb.1 (%ir-block.0):
136 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
137 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
138 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 3.000000e+00
139 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00
140 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s64) = G_FCONSTANT double 5.000000e+00
141 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s64) = G_FCONSTANT double 6.000000e+00
142 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s64) = G_FCONSTANT double 7.000000e+00
143 ; RV32-ILP32D-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 8.000000e+00
144 ; RV32-ILP32D-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 9.000000e+00
145 ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C8]](s64)
146 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C]](s64)
147 ; RV32-ILP32D-NEXT: $f11_d = COPY [[C1]](s64)
148 ; RV32-ILP32D-NEXT: $f12_d = COPY [[C2]](s64)
149 ; RV32-ILP32D-NEXT: $f13_d = COPY [[C3]](s64)
150 ; RV32-ILP32D-NEXT: $f14_d = COPY [[C4]](s64)
151 ; RV32-ILP32D-NEXT: $f15_d = COPY [[C5]](s64)
152 ; RV32-ILP32D-NEXT: $f16_d = COPY [[C6]](s64)
153 ; RV32-ILP32D-NEXT: $f17_d = COPY [[C7]](s64)
154 ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)
155 ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)
156 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_exhausted_fprs, implicit-def $x1, implicit $f10_d, implicit $f11_d, implicit $f12_d, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x10, implicit $x11, implicit-def $x10
157 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
158 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY]](s32)
159 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
160 %1 = call i32 @callee_double_in_gpr_exhausted_fprs(
161 double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0,
162 double 7.0, double 8.0, double 9.0)
163 ret i32 %1
164 }
166 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
167 define i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i32 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind {
168 ; RV32-ILP32D-LABEL: name: callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs
169 ; RV32-ILP32D: bb.1 (%ir-block.0):
170 ; RV32-ILP32D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_d, $f11_d, $f12_d, $f13_d, $f14_d, $f15_d, $f16_d, $f17_d
171 ; RV32-ILP32D-NEXT: {{ $}}
172 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
173 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
174 ; RV32-ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
175 ; RV32-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f10_d
176 ; RV32-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x12
177 ; RV32-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x13
178 ; RV32-ILP32D-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)
179 ; RV32-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $f11_d
180 ; RV32-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x14
181 ; RV32-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x15
182 ; RV32-ILP32D-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
183 ; RV32-ILP32D-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $f12_d
184 ; RV32-ILP32D-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x16
185 ; RV32-ILP32D-NEXT: [[COPY10:%[0-9]+]]:_(s64) = COPY $f13_d
186 ; RV32-ILP32D-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $f14_d
187 ; RV32-ILP32D-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $f15_d
188 ; RV32-ILP32D-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $f16_d
189 ; RV32-ILP32D-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $f17_d
190 ; RV32-ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
191 ; RV32-ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 16)
192 ; RV32-ILP32D-NEXT: [[COPY15:%[0-9]+]]:_(s32) = COPY $x17
193 ; RV32-ILP32D-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY15]](s32), [[LOAD]](s32)
194 ; RV32-ILP32D-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[MV3]](s64)
195 ; RV32-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY9]], [[FPTOSI]]
196 ; RV32-ILP32D-NEXT: $x10 = COPY [[ADD]](s32)
197 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
198 %m_fptosi = fptosi double %m to i32
199 %1 = add i32 %g, %m_fptosi
200 ret i32 %1
201 }
203 define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind {
204 ; RV32-ILP32D-LABEL: name: caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs
205 ; RV32-ILP32D: bb.1 (%ir-block.0):
206 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
207 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
208 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
209 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00
210 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
211 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s64) = G_FCONSTANT double 6.000000e+00
212 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
213 ; RV32-ILP32D-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 8.000000e+00
214 ; RV32-ILP32D-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 9.000000e+00
215 ; RV32-ILP32D-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+01
216 ; RV32-ILP32D-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.100000e+01
217 ; RV32-ILP32D-NEXT: [[C11:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.200000e+01
218 ; RV32-ILP32D-NEXT: [[C12:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.300000e+01
219 ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
220 ; RV32-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
221 ; RV32-ILP32D-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
222 ; RV32-ILP32D-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C12]](s64)
223 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
224 ; RV32-ILP32D-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
225 ; RV32-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s32)
226 ; RV32-ILP32D-NEXT: G_STORE [[UV7]](s32), [[PTR_ADD]](p0) :: (store (s32) into stack, align 16)
227 ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)
228 ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)
229 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C1]](s64)
230 ; RV32-ILP32D-NEXT: $x12 = COPY [[UV2]](s32)
231 ; RV32-ILP32D-NEXT: $x13 = COPY [[UV3]](s32)
232 ; RV32-ILP32D-NEXT: $f11_d = COPY [[C3]](s64)
233 ; RV32-ILP32D-NEXT: $x14 = COPY [[UV4]](s32)
234 ; RV32-ILP32D-NEXT: $x15 = COPY [[UV5]](s32)
235 ; RV32-ILP32D-NEXT: $f12_d = COPY [[C5]](s64)
236 ; RV32-ILP32D-NEXT: $x16 = COPY [[C6]](s32)
237 ; RV32-ILP32D-NEXT: $f13_d = COPY [[C7]](s64)
238 ; RV32-ILP32D-NEXT: $f14_d = COPY [[C8]](s64)
239 ; RV32-ILP32D-NEXT: $f15_d = COPY [[C9]](s64)
240 ; RV32-ILP32D-NEXT: $f16_d = COPY [[C10]](s64)
241 ; RV32-ILP32D-NEXT: $f17_d = COPY [[C11]](s64)
242 ; RV32-ILP32D-NEXT: $x17 = COPY [[UV6]](s32)
243 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit $x17, implicit-def $x10
244 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
245 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)
246 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
247 %1 = call i32 @callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs(
248 i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i32 7, double 8.0,
249 double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)
250 ret i32 %1
251 }
254 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
255 define i32 @callee_double_on_stack_exhausted_gprs_fprs(i64 %a, double %b, i64 %c, double %d, i64 %e, double %f, i64 %g, double %h, double %i, double %j, double %k, double %l, double %m) nounwind {
256 ; RV32-ILP32D-LABEL: name: callee_double_on_stack_exhausted_gprs_fprs
257 ; RV32-ILP32D: bb.1 (%ir-block.0):
258 ; RV32-ILP32D-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15, $x16, $x17, $f10_d, $f11_d, $f12_d, $f13_d, $f14_d, $f15_d, $f16_d, $f17_d
259 ; RV32-ILP32D-NEXT: {{ $}}
260 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
261 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
262 ; RV32-ILP32D-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
263 ; RV32-ILP32D-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $f10_d
264 ; RV32-ILP32D-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x12
265 ; RV32-ILP32D-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $x13
266 ; RV32-ILP32D-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)
267 ; RV32-ILP32D-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $f11_d
268 ; RV32-ILP32D-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $x14
269 ; RV32-ILP32D-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $x15
270 ; RV32-ILP32D-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
271 ; RV32-ILP32D-NEXT: [[COPY8:%[0-9]+]]:_(s64) = COPY $f12_d
272 ; RV32-ILP32D-NEXT: [[COPY9:%[0-9]+]]:_(s32) = COPY $x16
273 ; RV32-ILP32D-NEXT: [[COPY10:%[0-9]+]]:_(s32) = COPY $x17
274 ; RV32-ILP32D-NEXT: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY9]](s32), [[COPY10]](s32)
275 ; RV32-ILP32D-NEXT: [[COPY11:%[0-9]+]]:_(s64) = COPY $f13_d
276 ; RV32-ILP32D-NEXT: [[COPY12:%[0-9]+]]:_(s64) = COPY $f14_d
277 ; RV32-ILP32D-NEXT: [[COPY13:%[0-9]+]]:_(s64) = COPY $f15_d
278 ; RV32-ILP32D-NEXT: [[COPY14:%[0-9]+]]:_(s64) = COPY $f16_d
279 ; RV32-ILP32D-NEXT: [[COPY15:%[0-9]+]]:_(s64) = COPY $f17_d
280 ; RV32-ILP32D-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
281 ; RV32-ILP32D-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s64) from %fixed-stack.0, align 16)
282 ; RV32-ILP32D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[MV3]](s64)
283 ; RV32-ILP32D-NEXT: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[LOAD]](s64)
284 ; RV32-ILP32D-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[FPTOSI]]
285 ; RV32-ILP32D-NEXT: $x10 = COPY [[ADD]](s32)
286 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
287 %g_trunc = trunc i64 %g to i32
288 %m_fptosi = fptosi double %m to i32
289 %1 = add i32 %g_trunc, %m_fptosi
290 ret i32 %1
291 }
293 define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
294 ; RV32-ILP32D-LABEL: name: caller_double_on_stack_exhausted_gprs_fprs
295 ; RV32-ILP32D: bb.1 (%ir-block.0):
296 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
297 ; RV32-ILP32D-NEXT: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
298 ; RV32-ILP32D-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
299 ; RV32-ILP32D-NEXT: [[C3:%[0-9]+]]:_(s64) = G_FCONSTANT double 4.000000e+00
300 ; RV32-ILP32D-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
301 ; RV32-ILP32D-NEXT: [[C5:%[0-9]+]]:_(s64) = G_FCONSTANT double 6.000000e+00
302 ; RV32-ILP32D-NEXT: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
303 ; RV32-ILP32D-NEXT: [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 8.000000e+00
304 ; RV32-ILP32D-NEXT: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 9.000000e+00
305 ; RV32-ILP32D-NEXT: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+01
306 ; RV32-ILP32D-NEXT: [[C10:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.100000e+01
307 ; RV32-ILP32D-NEXT: [[C11:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.200000e+01
308 ; RV32-ILP32D-NEXT: [[C12:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.300000e+01
309 ; RV32-ILP32D-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64)
310 ; RV32-ILP32D-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C2]](s64)
311 ; RV32-ILP32D-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C4]](s64)
312 ; RV32-ILP32D-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C6]](s64)
313 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x2
314 ; RV32-ILP32D-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
315 ; RV32-ILP32D-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s32)
316 ; RV32-ILP32D-NEXT: G_STORE [[C12]](s64), [[PTR_ADD]](p0) :: (store (s64) into stack, align 16)
317 ; RV32-ILP32D-NEXT: $x10 = COPY [[UV]](s32)
318 ; RV32-ILP32D-NEXT: $x11 = COPY [[UV1]](s32)
319 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C1]](s64)
320 ; RV32-ILP32D-NEXT: $x12 = COPY [[UV2]](s32)
321 ; RV32-ILP32D-NEXT: $x13 = COPY [[UV3]](s32)
322 ; RV32-ILP32D-NEXT: $f11_d = COPY [[C3]](s64)
323 ; RV32-ILP32D-NEXT: $x14 = COPY [[UV4]](s32)
324 ; RV32-ILP32D-NEXT: $x15 = COPY [[UV5]](s32)
325 ; RV32-ILP32D-NEXT: $f12_d = COPY [[C5]](s64)
326 ; RV32-ILP32D-NEXT: $x16 = COPY [[UV6]](s32)
327 ; RV32-ILP32D-NEXT: $x17 = COPY [[UV7]](s32)
328 ; RV32-ILP32D-NEXT: $f13_d = COPY [[C7]](s64)
329 ; RV32-ILP32D-NEXT: $f14_d = COPY [[C8]](s64)
330 ; RV32-ILP32D-NEXT: $f15_d = COPY [[C9]](s64)
331 ; RV32-ILP32D-NEXT: $f16_d = COPY [[C10]](s64)
332 ; RV32-ILP32D-NEXT: $f17_d = COPY [[C11]](s64)
333 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_on_stack_exhausted_gprs_fprs, implicit-def $x1, implicit $x10, implicit $x11, implicit $f10_d, implicit $x12, implicit $x13, implicit $f11_d, implicit $x14, implicit $x15, implicit $f12_d, implicit $x16, implicit $x17, implicit $f13_d, implicit $f14_d, implicit $f15_d, implicit $f16_d, implicit $f17_d, implicit-def $x10
334 ; RV32-ILP32D-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
335 ; RV32-ILP32D-NEXT: $x10 = COPY [[COPY1]](s32)
336 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
337 %1 = call i32 @callee_double_on_stack_exhausted_gprs_fprs(
338 i64 1, double 2.0, i64 3, double 4.0, i64 5, double 6.0, i64 7, double 8.0,
339 double 9.0, double 10.0, double 11.0, double 12.0, double 13.0)
340 ret i32 %1
341 }
343 define double @callee_double_ret() nounwind {
344 ; RV32-ILP32D-LABEL: name: callee_double_ret
345 ; RV32-ILP32D: bb.1 (%ir-block.0):
346 ; RV32-ILP32D-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
347 ; RV32-ILP32D-NEXT: $f10_d = COPY [[C]](s64)
348 ; RV32-ILP32D-NEXT: PseudoRET implicit $f10_d
349 ret double 1.0
350 }
352 define i32 @caller_double_ret() nounwind {
353 ; RV32-ILP32D-LABEL: name: caller_double_ret
354 ; RV32-ILP32D: bb.1 (%ir-block.0):
355 ; RV32-ILP32D-NEXT: PseudoCALL target-flags(riscv-call) @callee_double_ret, implicit-def $x1, implicit-def $f10_d
356 ; RV32-ILP32D-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $f10_d
357 ; RV32-ILP32D-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
358 ; RV32-ILP32D-NEXT: $x10 = COPY [[TRUNC]](s32)
359 ; RV32-ILP32D-NEXT: PseudoRET implicit $x10
360 %1 = call double @callee_double_ret()
361 %2 = bitcast double %1 to i64
362 %3 = trunc i64 %2 to i32
363 ret i32 %3
364 }