| blob | 8a0c4240d161bfbd28bfd451a08e93f814f22aba |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
2 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin -verify-machineinstrs \
3 ; RUN: -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECK32ZFBFMIN,RV32IZFBFMIN %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfbfmin -verify-machineinstrs \
5 ; RUN: -target-abi ilp32d < %s | FileCheck -check-prefixes=CHECK32ZFBFMIN,R32IDZFBFMIN %s
6 ; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs \
7 ; RUN: -target-abi ilp32d < %s | FileCheck -check-prefixes=RV32ID %s
8 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin -verify-machineinstrs \
9 ; RUN: -target-abi lp64f < %s | FileCheck -check-prefixes=CHECK64ZFBFMIN,RV64IZFBFMIN %s
10 ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfbfmin -verify-machineinstrs \
11 ; RUN: -target-abi lp64d < %s | FileCheck -check-prefixes=CHECK64ZFBFMIN,RV64IDZFBFMIN %s
12 ; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs \
13 ; RUN: -target-abi lp64d < %s | FileCheck -check-prefixes=RV64ID %s
15 ; These tests descend from float-arith.ll, where each function was targeted at
16 ; a particular RISC-V FPU instruction.
18 define i16 @fcvt_si_bf16(bfloat %a) nounwind {
19 ; CHECK32ZFBFMIN-LABEL: fcvt_si_bf16:
20 ; CHECK32ZFBFMIN: # %bb.0:
21 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
22 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
23 ; CHECK32ZFBFMIN-NEXT: ret
24 ;
25 ; RV32ID-LABEL: fcvt_si_bf16:
26 ; RV32ID: # %bb.0:
27 ; RV32ID-NEXT: fmv.x.w a0, fa0
28 ; RV32ID-NEXT: slli a0, a0, 16
29 ; RV32ID-NEXT: fmv.w.x fa5, a0
30 ; RV32ID-NEXT: fcvt.w.s a0, fa5, rtz
31 ; RV32ID-NEXT: ret
32 ;
33 ; CHECK64ZFBFMIN-LABEL: fcvt_si_bf16:
34 ; CHECK64ZFBFMIN: # %bb.0:
35 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
36 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
37 ; CHECK64ZFBFMIN-NEXT: ret
38 ;
39 ; RV64ID-LABEL: fcvt_si_bf16:
40 ; RV64ID: # %bb.0:
41 ; RV64ID-NEXT: fmv.x.w a0, fa0
42 ; RV64ID-NEXT: slli a0, a0, 48
43 ; RV64ID-NEXT: srli a0, a0, 48
44 ; RV64ID-NEXT: slli a0, a0, 16
45 ; RV64ID-NEXT: fmv.w.x fa5, a0
46 ; RV64ID-NEXT: fcvt.l.s a0, fa5, rtz
47 ; RV64ID-NEXT: ret
48 %1 = fptosi bfloat %a to i16
49 ret i16 %1
50 }
52 define i16 @fcvt_si_bf16_sat(bfloat %a) nounwind {
53 ; CHECK32ZFBFMIN-LABEL: fcvt_si_bf16_sat:
54 ; CHECK32ZFBFMIN: # %bb.0: # %start
55 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
56 ; CHECK32ZFBFMIN-NEXT: feq.s a0, fa5, fa5
57 ; CHECK32ZFBFMIN-NEXT: neg a0, a0
58 ; CHECK32ZFBFMIN-NEXT: lui a1, %hi(.LCPI1_0)
59 ; CHECK32ZFBFMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
60 ; CHECK32ZFBFMIN-NEXT: lui a1, 815104
61 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa3, a1
62 ; CHECK32ZFBFMIN-NEXT: fmax.s fa5, fa5, fa3
63 ; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
64 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a1, fa5, rtz
65 ; CHECK32ZFBFMIN-NEXT: and a0, a0, a1
66 ; CHECK32ZFBFMIN-NEXT: ret
67 ;
68 ; RV32ID-LABEL: fcvt_si_bf16_sat:
69 ; RV32ID: # %bb.0: # %start
70 ; RV32ID-NEXT: fmv.x.w a0, fa0
71 ; RV32ID-NEXT: slli a0, a0, 16
72 ; RV32ID-NEXT: fmv.w.x fa5, a0
73 ; RV32ID-NEXT: feq.s a0, fa5, fa5
74 ; RV32ID-NEXT: lui a1, %hi(.LCPI1_0)
75 ; RV32ID-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
76 ; RV32ID-NEXT: lui a1, 815104
77 ; RV32ID-NEXT: fmv.w.x fa3, a1
78 ; RV32ID-NEXT: fmax.s fa5, fa5, fa3
79 ; RV32ID-NEXT: neg a0, a0
80 ; RV32ID-NEXT: fmin.s fa5, fa5, fa4
81 ; RV32ID-NEXT: fcvt.w.s a1, fa5, rtz
82 ; RV32ID-NEXT: and a0, a0, a1
83 ; RV32ID-NEXT: ret
84 ;
85 ; CHECK64ZFBFMIN-LABEL: fcvt_si_bf16_sat:
86 ; CHECK64ZFBFMIN: # %bb.0: # %start
87 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
88 ; CHECK64ZFBFMIN-NEXT: feq.s a0, fa5, fa5
89 ; CHECK64ZFBFMIN-NEXT: lui a1, %hi(.LCPI1_0)
90 ; CHECK64ZFBFMIN-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
91 ; CHECK64ZFBFMIN-NEXT: lui a1, 815104
92 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa3, a1
93 ; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa3
94 ; CHECK64ZFBFMIN-NEXT: neg a0, a0
95 ; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
96 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a1, fa5, rtz
97 ; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
98 ; CHECK64ZFBFMIN-NEXT: ret
99 ;
100 ; RV64ID-LABEL: fcvt_si_bf16_sat:
101 ; RV64ID: # %bb.0: # %start
102 ; RV64ID-NEXT: fmv.x.w a0, fa0
103 ; RV64ID-NEXT: slli a0, a0, 48
104 ; RV64ID-NEXT: srli a0, a0, 48
105 ; RV64ID-NEXT: slli a0, a0, 16
106 ; RV64ID-NEXT: fmv.w.x fa5, a0
107 ; RV64ID-NEXT: feq.s a0, fa5, fa5
108 ; RV64ID-NEXT: lui a1, %hi(.LCPI1_0)
109 ; RV64ID-NEXT: flw fa4, %lo(.LCPI1_0)(a1)
110 ; RV64ID-NEXT: lui a1, 815104
111 ; RV64ID-NEXT: fmv.w.x fa3, a1
112 ; RV64ID-NEXT: fmax.s fa5, fa5, fa3
113 ; RV64ID-NEXT: neg a0, a0
114 ; RV64ID-NEXT: fmin.s fa5, fa5, fa4
115 ; RV64ID-NEXT: fcvt.l.s a1, fa5, rtz
116 ; RV64ID-NEXT: and a0, a0, a1
117 ; RV64ID-NEXT: ret
118 start:
119 %0 = tail call i16 @llvm.fptosi.sat.i16.bf16(bfloat %a)
120 ret i16 %0
121 }
122 declare i16 @llvm.fptosi.sat.i16.bf16(bfloat)
124 define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
125 ; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16:
126 ; CHECK32ZFBFMIN: # %bb.0:
127 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
128 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
129 ; CHECK32ZFBFMIN-NEXT: ret
130 ;
131 ; RV32ID-LABEL: fcvt_ui_bf16:
132 ; RV32ID: # %bb.0:
133 ; RV32ID-NEXT: fmv.x.w a0, fa0
134 ; RV32ID-NEXT: slli a0, a0, 16
135 ; RV32ID-NEXT: fmv.w.x fa5, a0
136 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
137 ; RV32ID-NEXT: ret
138 ;
139 ; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16:
140 ; CHECK64ZFBFMIN: # %bb.0:
141 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
142 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
143 ; CHECK64ZFBFMIN-NEXT: ret
144 ;
145 ; RV64ID-LABEL: fcvt_ui_bf16:
146 ; RV64ID: # %bb.0:
147 ; RV64ID-NEXT: fmv.x.w a0, fa0
148 ; RV64ID-NEXT: slli a0, a0, 48
149 ; RV64ID-NEXT: srli a0, a0, 48
150 ; RV64ID-NEXT: slli a0, a0, 16
151 ; RV64ID-NEXT: fmv.w.x fa5, a0
152 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
153 ; RV64ID-NEXT: ret
154 %1 = fptoui bfloat %a to i16
155 ret i16 %1
156 }
158 define i16 @fcvt_ui_bf16_sat(bfloat %a) nounwind {
159 ; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16_sat:
160 ; CHECK32ZFBFMIN: # %bb.0: # %start
161 ; CHECK32ZFBFMIN-NEXT: lui a0, %hi(.LCPI3_0)
162 ; CHECK32ZFBFMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
163 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
164 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa3, zero
165 ; CHECK32ZFBFMIN-NEXT: fmax.s fa4, fa4, fa3
166 ; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa4, fa5
167 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
168 ; CHECK32ZFBFMIN-NEXT: ret
169 ;
170 ; RV32ID-LABEL: fcvt_ui_bf16_sat:
171 ; RV32ID: # %bb.0: # %start
172 ; RV32ID-NEXT: fmv.x.w a0, fa0
173 ; RV32ID-NEXT: slli a0, a0, 16
174 ; RV32ID-NEXT: lui a1, %hi(.LCPI3_0)
175 ; RV32ID-NEXT: flw fa5, %lo(.LCPI3_0)(a1)
176 ; RV32ID-NEXT: fmv.w.x fa4, a0
177 ; RV32ID-NEXT: fmv.w.x fa3, zero
178 ; RV32ID-NEXT: fmax.s fa4, fa4, fa3
179 ; RV32ID-NEXT: fmin.s fa5, fa4, fa5
180 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
181 ; RV32ID-NEXT: ret
182 ;
183 ; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16_sat:
184 ; CHECK64ZFBFMIN: # %bb.0: # %start
185 ; CHECK64ZFBFMIN-NEXT: lui a0, %hi(.LCPI3_0)
186 ; CHECK64ZFBFMIN-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
187 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
188 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa3, zero
189 ; CHECK64ZFBFMIN-NEXT: fmax.s fa4, fa4, fa3
190 ; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa4, fa5
191 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
192 ; CHECK64ZFBFMIN-NEXT: ret
193 ;
194 ; RV64ID-LABEL: fcvt_ui_bf16_sat:
195 ; RV64ID: # %bb.0: # %start
196 ; RV64ID-NEXT: lui a0, %hi(.LCPI3_0)
197 ; RV64ID-NEXT: flw fa5, %lo(.LCPI3_0)(a0)
198 ; RV64ID-NEXT: fmv.x.w a0, fa0
199 ; RV64ID-NEXT: slli a0, a0, 48
200 ; RV64ID-NEXT: srli a0, a0, 48
201 ; RV64ID-NEXT: slli a0, a0, 16
202 ; RV64ID-NEXT: fmv.w.x fa4, a0
203 ; RV64ID-NEXT: fmv.w.x fa3, zero
204 ; RV64ID-NEXT: fmax.s fa4, fa4, fa3
205 ; RV64ID-NEXT: fmin.s fa5, fa4, fa5
206 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
207 ; RV64ID-NEXT: ret
208 start:
209 %0 = tail call i16 @llvm.fptoui.sat.i16.bf16(bfloat %a)
210 ret i16 %0
211 }
212 declare i16 @llvm.fptoui.sat.i16.bf16(bfloat)
214 define i32 @fcvt_w_bf16(bfloat %a) nounwind {
215 ; CHECK32ZFBFMIN-LABEL: fcvt_w_bf16:
216 ; CHECK32ZFBFMIN: # %bb.0:
217 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
218 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
219 ; CHECK32ZFBFMIN-NEXT: ret
220 ;
221 ; RV32ID-LABEL: fcvt_w_bf16:
222 ; RV32ID: # %bb.0:
223 ; RV32ID-NEXT: fmv.x.w a0, fa0
224 ; RV32ID-NEXT: slli a0, a0, 16
225 ; RV32ID-NEXT: fmv.w.x fa5, a0
226 ; RV32ID-NEXT: fcvt.w.s a0, fa5, rtz
227 ; RV32ID-NEXT: ret
228 ;
229 ; CHECK64ZFBFMIN-LABEL: fcvt_w_bf16:
230 ; CHECK64ZFBFMIN: # %bb.0:
231 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
232 ; CHECK64ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
233 ; CHECK64ZFBFMIN-NEXT: ret
234 ;
235 ; RV64ID-LABEL: fcvt_w_bf16:
236 ; RV64ID: # %bb.0:
237 ; RV64ID-NEXT: fmv.x.w a0, fa0
238 ; RV64ID-NEXT: slli a0, a0, 48
239 ; RV64ID-NEXT: srli a0, a0, 48
240 ; RV64ID-NEXT: slli a0, a0, 16
241 ; RV64ID-NEXT: fmv.w.x fa5, a0
242 ; RV64ID-NEXT: fcvt.l.s a0, fa5, rtz
243 ; RV64ID-NEXT: ret
244 %1 = fptosi bfloat %a to i32
245 ret i32 %1
246 }
248 define i32 @fcvt_w_bf16_sat(bfloat %a) nounwind {
249 ; CHECK32ZFBFMIN-LABEL: fcvt_w_bf16_sat:
250 ; CHECK32ZFBFMIN: # %bb.0: # %start
251 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
252 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
253 ; CHECK32ZFBFMIN-NEXT: feq.s a1, fa5, fa5
254 ; CHECK32ZFBFMIN-NEXT: seqz a1, a1
255 ; CHECK32ZFBFMIN-NEXT: addi a1, a1, -1
256 ; CHECK32ZFBFMIN-NEXT: and a0, a1, a0
257 ; CHECK32ZFBFMIN-NEXT: ret
258 ;
259 ; RV32ID-LABEL: fcvt_w_bf16_sat:
260 ; RV32ID: # %bb.0: # %start
261 ; RV32ID-NEXT: fmv.x.w a0, fa0
262 ; RV32ID-NEXT: slli a0, a0, 16
263 ; RV32ID-NEXT: fmv.w.x fa5, a0
264 ; RV32ID-NEXT: fcvt.w.s a0, fa5, rtz
265 ; RV32ID-NEXT: feq.s a1, fa5, fa5
266 ; RV32ID-NEXT: seqz a1, a1
267 ; RV32ID-NEXT: addi a1, a1, -1
268 ; RV32ID-NEXT: and a0, a1, a0
269 ; RV32ID-NEXT: ret
270 ;
271 ; CHECK64ZFBFMIN-LABEL: fcvt_w_bf16_sat:
272 ; CHECK64ZFBFMIN: # %bb.0: # %start
273 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
274 ; CHECK64ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
275 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
276 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
277 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
278 ; CHECK64ZFBFMIN-NEXT: and a0, a1, a0
279 ; CHECK64ZFBFMIN-NEXT: ret
280 ;
281 ; RV64ID-LABEL: fcvt_w_bf16_sat:
282 ; RV64ID: # %bb.0: # %start
283 ; RV64ID-NEXT: fmv.x.w a0, fa0
284 ; RV64ID-NEXT: slli a0, a0, 48
285 ; RV64ID-NEXT: srli a0, a0, 48
286 ; RV64ID-NEXT: slli a0, a0, 16
287 ; RV64ID-NEXT: fmv.w.x fa5, a0
288 ; RV64ID-NEXT: fcvt.w.s a0, fa5, rtz
289 ; RV64ID-NEXT: feq.s a1, fa5, fa5
290 ; RV64ID-NEXT: seqz a1, a1
291 ; RV64ID-NEXT: addi a1, a1, -1
292 ; RV64ID-NEXT: and a0, a1, a0
293 ; RV64ID-NEXT: ret
294 start:
295 %0 = tail call i32 @llvm.fptosi.sat.i32.bf16(bfloat %a)
296 ret i32 %0
297 }
298 declare i32 @llvm.fptosi.sat.i32.bf16(bfloat)
300 define i32 @fcvt_wu_bf16(bfloat %a) nounwind {
301 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16:
302 ; CHECK32ZFBFMIN: # %bb.0:
303 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
304 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
305 ; CHECK32ZFBFMIN-NEXT: ret
306 ;
307 ; RV32ID-LABEL: fcvt_wu_bf16:
308 ; RV32ID: # %bb.0:
309 ; RV32ID-NEXT: fmv.x.w a0, fa0
310 ; RV32ID-NEXT: slli a0, a0, 16
311 ; RV32ID-NEXT: fmv.w.x fa5, a0
312 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
313 ; RV32ID-NEXT: ret
314 ;
315 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_bf16:
316 ; CHECK64ZFBFMIN: # %bb.0:
317 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
318 ; CHECK64ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
319 ; CHECK64ZFBFMIN-NEXT: ret
320 ;
321 ; RV64ID-LABEL: fcvt_wu_bf16:
322 ; RV64ID: # %bb.0:
323 ; RV64ID-NEXT: fmv.x.w a0, fa0
324 ; RV64ID-NEXT: slli a0, a0, 48
325 ; RV64ID-NEXT: srli a0, a0, 48
326 ; RV64ID-NEXT: slli a0, a0, 16
327 ; RV64ID-NEXT: fmv.w.x fa5, a0
328 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
329 ; RV64ID-NEXT: ret
330 %1 = fptoui bfloat %a to i32
331 ret i32 %1
332 }
334 define i32 @fcvt_wu_bf16_multiple_use(bfloat %x, ptr %y) nounwind {
335 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16_multiple_use:
336 ; CHECK32ZFBFMIN: # %bb.0:
337 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
338 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
339 ; CHECK32ZFBFMIN-NEXT: seqz a1, a0
340 ; CHECK32ZFBFMIN-NEXT: add a0, a0, a1
341 ; CHECK32ZFBFMIN-NEXT: ret
342 ;
343 ; RV32ID-LABEL: fcvt_wu_bf16_multiple_use:
344 ; RV32ID: # %bb.0:
345 ; RV32ID-NEXT: fmv.x.w a0, fa0
346 ; RV32ID-NEXT: slli a0, a0, 16
347 ; RV32ID-NEXT: fmv.w.x fa5, a0
348 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
349 ; RV32ID-NEXT: seqz a1, a0
350 ; RV32ID-NEXT: add a0, a0, a1
351 ; RV32ID-NEXT: ret
352 ;
353 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_bf16_multiple_use:
354 ; CHECK64ZFBFMIN: # %bb.0:
355 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
356 ; CHECK64ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
357 ; CHECK64ZFBFMIN-NEXT: seqz a1, a0
358 ; CHECK64ZFBFMIN-NEXT: add a0, a0, a1
359 ; CHECK64ZFBFMIN-NEXT: ret
360 ;
361 ; RV64ID-LABEL: fcvt_wu_bf16_multiple_use:
362 ; RV64ID: # %bb.0:
363 ; RV64ID-NEXT: fmv.x.w a0, fa0
364 ; RV64ID-NEXT: slli a0, a0, 48
365 ; RV64ID-NEXT: srli a0, a0, 48
366 ; RV64ID-NEXT: slli a0, a0, 16
367 ; RV64ID-NEXT: fmv.w.x fa5, a0
368 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
369 ; RV64ID-NEXT: seqz a1, a0
370 ; RV64ID-NEXT: add a0, a0, a1
371 ; RV64ID-NEXT: ret
372 %a = fptoui bfloat %x to i32
373 %b = icmp eq i32 %a, 0
374 %c = select i1 %b, i32 1, i32 %a
375 ret i32 %c
376 }
378 define i32 @fcvt_wu_bf16_sat(bfloat %a) nounwind {
379 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16_sat:
380 ; CHECK32ZFBFMIN: # %bb.0: # %start
381 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
382 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
383 ; CHECK32ZFBFMIN-NEXT: feq.s a1, fa5, fa5
384 ; CHECK32ZFBFMIN-NEXT: seqz a1, a1
385 ; CHECK32ZFBFMIN-NEXT: addi a1, a1, -1
386 ; CHECK32ZFBFMIN-NEXT: and a0, a1, a0
387 ; CHECK32ZFBFMIN-NEXT: ret
388 ;
389 ; RV32ID-LABEL: fcvt_wu_bf16_sat:
390 ; RV32ID: # %bb.0: # %start
391 ; RV32ID-NEXT: fmv.x.w a0, fa0
392 ; RV32ID-NEXT: slli a0, a0, 16
393 ; RV32ID-NEXT: fmv.w.x fa5, a0
394 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
395 ; RV32ID-NEXT: feq.s a1, fa5, fa5
396 ; RV32ID-NEXT: seqz a1, a1
397 ; RV32ID-NEXT: addi a1, a1, -1
398 ; RV32ID-NEXT: and a0, a1, a0
399 ; RV32ID-NEXT: ret
400 ;
401 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_bf16_sat:
402 ; CHECK64ZFBFMIN: # %bb.0: # %start
403 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
404 ; CHECK64ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
405 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
406 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
407 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
408 ; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
409 ; CHECK64ZFBFMIN-NEXT: slli a0, a0, 32
410 ; CHECK64ZFBFMIN-NEXT: srli a0, a0, 32
411 ; CHECK64ZFBFMIN-NEXT: ret
412 ;
413 ; RV64ID-LABEL: fcvt_wu_bf16_sat:
414 ; RV64ID: # %bb.0: # %start
415 ; RV64ID-NEXT: fmv.x.w a0, fa0
416 ; RV64ID-NEXT: slli a0, a0, 48
417 ; RV64ID-NEXT: srli a0, a0, 48
418 ; RV64ID-NEXT: slli a0, a0, 16
419 ; RV64ID-NEXT: fmv.w.x fa5, a0
420 ; RV64ID-NEXT: fcvt.wu.s a0, fa5, rtz
421 ; RV64ID-NEXT: feq.s a1, fa5, fa5
422 ; RV64ID-NEXT: seqz a1, a1
423 ; RV64ID-NEXT: addi a1, a1, -1
424 ; RV64ID-NEXT: and a0, a0, a1
425 ; RV64ID-NEXT: slli a0, a0, 32
426 ; RV64ID-NEXT: srli a0, a0, 32
427 ; RV64ID-NEXT: ret
428 start:
429 %0 = tail call i32 @llvm.fptoui.sat.i32.bf16(bfloat %a)
430 ret i32 %0
431 }
432 declare i32 @llvm.fptoui.sat.i32.bf16(bfloat)
434 define i64 @fcvt_l_bf16(bfloat %a) nounwind {
435 ; CHECK32ZFBFMIN-LABEL: fcvt_l_bf16:
436 ; CHECK32ZFBFMIN: # %bb.0:
437 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16
438 ; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
439 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
440 ; CHECK32ZFBFMIN-NEXT: call __fixsfdi@plt
441 ; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
442 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16
443 ; CHECK32ZFBFMIN-NEXT: ret
444 ;
445 ; RV32ID-LABEL: fcvt_l_bf16:
446 ; RV32ID: # %bb.0:
447 ; RV32ID-NEXT: addi sp, sp, -16
448 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
449 ; RV32ID-NEXT: fmv.x.w a0, fa0
450 ; RV32ID-NEXT: slli a0, a0, 16
451 ; RV32ID-NEXT: fmv.w.x fa0, a0
452 ; RV32ID-NEXT: call __fixsfdi@plt
453 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
454 ; RV32ID-NEXT: addi sp, sp, 16
455 ; RV32ID-NEXT: ret
456 ;
457 ; CHECK64ZFBFMIN-LABEL: fcvt_l_bf16:
458 ; CHECK64ZFBFMIN: # %bb.0:
459 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
460 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
461 ; CHECK64ZFBFMIN-NEXT: ret
462 ;
463 ; RV64ID-LABEL: fcvt_l_bf16:
464 ; RV64ID: # %bb.0:
465 ; RV64ID-NEXT: fmv.x.w a0, fa0
466 ; RV64ID-NEXT: slli a0, a0, 48
467 ; RV64ID-NEXT: srli a0, a0, 48
468 ; RV64ID-NEXT: slli a0, a0, 16
469 ; RV64ID-NEXT: fmv.w.x fa5, a0
470 ; RV64ID-NEXT: fcvt.l.s a0, fa5, rtz
471 ; RV64ID-NEXT: ret
472 %1 = fptosi bfloat %a to i64
473 ret i64 %1
474 }
476 define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind {
477 ; RV32IZFBFMIN-LABEL: fcvt_l_bf16_sat:
478 ; RV32IZFBFMIN: # %bb.0: # %start
479 ; RV32IZFBFMIN-NEXT: addi sp, sp, -16
480 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
481 ; RV32IZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
482 ; RV32IZFBFMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill
483 ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0
484 ; RV32IZFBFMIN-NEXT: lui a0, 913408
485 ; RV32IZFBFMIN-NEXT: fmv.w.x fa5, a0
486 ; RV32IZFBFMIN-NEXT: fle.s s0, fa5, fs0
487 ; RV32IZFBFMIN-NEXT: fmv.s fa0, fs0
488 ; RV32IZFBFMIN-NEXT: call __fixsfdi@plt
489 ; RV32IZFBFMIN-NEXT: lui a4, 524288
490 ; RV32IZFBFMIN-NEXT: lui a2, 524288
491 ; RV32IZFBFMIN-NEXT: beqz s0, .LBB10_2
492 ; RV32IZFBFMIN-NEXT: # %bb.1: # %start
493 ; RV32IZFBFMIN-NEXT: mv a2, a1
494 ; RV32IZFBFMIN-NEXT: .LBB10_2: # %start
495 ; RV32IZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0)
496 ; RV32IZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
497 ; RV32IZFBFMIN-NEXT: flt.s a3, fa5, fs0
498 ; RV32IZFBFMIN-NEXT: beqz a3, .LBB10_4
499 ; RV32IZFBFMIN-NEXT: # %bb.3:
500 ; RV32IZFBFMIN-NEXT: addi a2, a4, -1
501 ; RV32IZFBFMIN-NEXT: .LBB10_4: # %start
502 ; RV32IZFBFMIN-NEXT: feq.s a1, fs0, fs0
503 ; RV32IZFBFMIN-NEXT: neg a4, a1
504 ; RV32IZFBFMIN-NEXT: and a1, a4, a2
505 ; RV32IZFBFMIN-NEXT: neg a2, a3
506 ; RV32IZFBFMIN-NEXT: neg a3, s0
507 ; RV32IZFBFMIN-NEXT: and a0, a3, a0
508 ; RV32IZFBFMIN-NEXT: or a0, a2, a0
509 ; RV32IZFBFMIN-NEXT: and a0, a4, a0
510 ; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
511 ; RV32IZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
512 ; RV32IZFBFMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
513 ; RV32IZFBFMIN-NEXT: addi sp, sp, 16
514 ; RV32IZFBFMIN-NEXT: ret
515 ;
516 ; R32IDZFBFMIN-LABEL: fcvt_l_bf16_sat:
517 ; R32IDZFBFMIN: # %bb.0: # %start
518 ; R32IDZFBFMIN-NEXT: addi sp, sp, -16
519 ; R32IDZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
520 ; R32IDZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
521 ; R32IDZFBFMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
522 ; R32IDZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0
523 ; R32IDZFBFMIN-NEXT: lui a0, 913408
524 ; R32IDZFBFMIN-NEXT: fmv.w.x fa5, a0
525 ; R32IDZFBFMIN-NEXT: fle.s s0, fa5, fs0
526 ; R32IDZFBFMIN-NEXT: fmv.s fa0, fs0
527 ; R32IDZFBFMIN-NEXT: call __fixsfdi@plt
528 ; R32IDZFBFMIN-NEXT: lui a4, 524288
529 ; R32IDZFBFMIN-NEXT: lui a2, 524288
530 ; R32IDZFBFMIN-NEXT: beqz s0, .LBB10_2
531 ; R32IDZFBFMIN-NEXT: # %bb.1: # %start
532 ; R32IDZFBFMIN-NEXT: mv a2, a1
533 ; R32IDZFBFMIN-NEXT: .LBB10_2: # %start
534 ; R32IDZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0)
535 ; R32IDZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
536 ; R32IDZFBFMIN-NEXT: flt.s a3, fa5, fs0
537 ; R32IDZFBFMIN-NEXT: beqz a3, .LBB10_4
538 ; R32IDZFBFMIN-NEXT: # %bb.3:
539 ; R32IDZFBFMIN-NEXT: addi a2, a4, -1
540 ; R32IDZFBFMIN-NEXT: .LBB10_4: # %start
541 ; R32IDZFBFMIN-NEXT: feq.s a1, fs0, fs0
542 ; R32IDZFBFMIN-NEXT: neg a4, a1
543 ; R32IDZFBFMIN-NEXT: and a1, a4, a2
544 ; R32IDZFBFMIN-NEXT: neg a2, a3
545 ; R32IDZFBFMIN-NEXT: neg a3, s0
546 ; R32IDZFBFMIN-NEXT: and a0, a3, a0
547 ; R32IDZFBFMIN-NEXT: or a0, a2, a0
548 ; R32IDZFBFMIN-NEXT: and a0, a4, a0
549 ; R32IDZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
550 ; R32IDZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
551 ; R32IDZFBFMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
552 ; R32IDZFBFMIN-NEXT: addi sp, sp, 16
553 ; R32IDZFBFMIN-NEXT: ret
554 ;
555 ; RV32ID-LABEL: fcvt_l_bf16_sat:
556 ; RV32ID: # %bb.0: # %start
557 ; RV32ID-NEXT: addi sp, sp, -16
558 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
559 ; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
560 ; RV32ID-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
561 ; RV32ID-NEXT: fmv.x.w a0, fa0
562 ; RV32ID-NEXT: slli a0, a0, 16
563 ; RV32ID-NEXT: fmv.w.x fs0, a0
564 ; RV32ID-NEXT: lui a0, 913408
565 ; RV32ID-NEXT: fmv.w.x fa5, a0
566 ; RV32ID-NEXT: fle.s s0, fa5, fs0
567 ; RV32ID-NEXT: fmv.s fa0, fs0
568 ; RV32ID-NEXT: call __fixsfdi@plt
569 ; RV32ID-NEXT: lui a4, 524288
570 ; RV32ID-NEXT: lui a2, 524288
571 ; RV32ID-NEXT: beqz s0, .LBB10_2
572 ; RV32ID-NEXT: # %bb.1: # %start
573 ; RV32ID-NEXT: mv a2, a1
574 ; RV32ID-NEXT: .LBB10_2: # %start
575 ; RV32ID-NEXT: lui a1, %hi(.LCPI10_0)
576 ; RV32ID-NEXT: flw fa5, %lo(.LCPI10_0)(a1)
577 ; RV32ID-NEXT: flt.s a3, fa5, fs0
578 ; RV32ID-NEXT: beqz a3, .LBB10_4
579 ; RV32ID-NEXT: # %bb.3:
580 ; RV32ID-NEXT: addi a2, a4, -1
581 ; RV32ID-NEXT: .LBB10_4: # %start
582 ; RV32ID-NEXT: feq.s a1, fs0, fs0
583 ; RV32ID-NEXT: neg a4, a1
584 ; RV32ID-NEXT: and a1, a4, a2
585 ; RV32ID-NEXT: neg a2, a3
586 ; RV32ID-NEXT: neg a3, s0
587 ; RV32ID-NEXT: and a0, a3, a0
588 ; RV32ID-NEXT: or a0, a2, a0
589 ; RV32ID-NEXT: and a0, a4, a0
590 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
591 ; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
592 ; RV32ID-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
593 ; RV32ID-NEXT: addi sp, sp, 16
594 ; RV32ID-NEXT: ret
595 ;
596 ; CHECK64ZFBFMIN-LABEL: fcvt_l_bf16_sat:
597 ; CHECK64ZFBFMIN: # %bb.0: # %start
598 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
599 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
600 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
601 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
602 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
603 ; CHECK64ZFBFMIN-NEXT: and a0, a1, a0
604 ; CHECK64ZFBFMIN-NEXT: ret
605 ;
606 ; RV64ID-LABEL: fcvt_l_bf16_sat:
607 ; RV64ID: # %bb.0: # %start
608 ; RV64ID-NEXT: fmv.x.w a0, fa0
609 ; RV64ID-NEXT: slli a0, a0, 48
610 ; RV64ID-NEXT: srli a0, a0, 48
611 ; RV64ID-NEXT: slli a0, a0, 16
612 ; RV64ID-NEXT: fmv.w.x fa5, a0
613 ; RV64ID-NEXT: fcvt.l.s a0, fa5, rtz
614 ; RV64ID-NEXT: feq.s a1, fa5, fa5
615 ; RV64ID-NEXT: seqz a1, a1
616 ; RV64ID-NEXT: addi a1, a1, -1
617 ; RV64ID-NEXT: and a0, a1, a0
618 ; RV64ID-NEXT: ret
619 start:
620 %0 = tail call i64 @llvm.fptosi.sat.i64.bf16(bfloat %a)
621 ret i64 %0
622 }
623 declare i64 @llvm.fptosi.sat.i64.bf16(bfloat)
625 define i64 @fcvt_lu_bf16(bfloat %a) nounwind {
626 ; CHECK32ZFBFMIN-LABEL: fcvt_lu_bf16:
627 ; CHECK32ZFBFMIN: # %bb.0:
628 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16
629 ; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
630 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
631 ; CHECK32ZFBFMIN-NEXT: call __fixunssfdi@plt
632 ; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
633 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16
634 ; CHECK32ZFBFMIN-NEXT: ret
635 ;
636 ; RV32ID-LABEL: fcvt_lu_bf16:
637 ; RV32ID: # %bb.0:
638 ; RV32ID-NEXT: addi sp, sp, -16
639 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
640 ; RV32ID-NEXT: fmv.x.w a0, fa0
641 ; RV32ID-NEXT: slli a0, a0, 16
642 ; RV32ID-NEXT: fmv.w.x fa0, a0
643 ; RV32ID-NEXT: call __fixunssfdi@plt
644 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
645 ; RV32ID-NEXT: addi sp, sp, 16
646 ; RV32ID-NEXT: ret
647 ;
648 ; CHECK64ZFBFMIN-LABEL: fcvt_lu_bf16:
649 ; CHECK64ZFBFMIN: # %bb.0:
650 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
651 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
652 ; CHECK64ZFBFMIN-NEXT: ret
653 ;
654 ; RV64ID-LABEL: fcvt_lu_bf16:
655 ; RV64ID: # %bb.0:
656 ; RV64ID-NEXT: fmv.x.w a0, fa0
657 ; RV64ID-NEXT: slli a0, a0, 48
658 ; RV64ID-NEXT: srli a0, a0, 48
659 ; RV64ID-NEXT: slli a0, a0, 16
660 ; RV64ID-NEXT: fmv.w.x fa5, a0
661 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
662 ; RV64ID-NEXT: ret
663 %1 = fptoui bfloat %a to i64
664 ret i64 %1
665 }
667 define i64 @fcvt_lu_bf16_sat(bfloat %a) nounwind {
668 ; CHECK32ZFBFMIN-LABEL: fcvt_lu_bf16_sat:
669 ; CHECK32ZFBFMIN: # %bb.0: # %start
670 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, -16
671 ; CHECK32ZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
672 ; CHECK32ZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
673 ; CHECK32ZFBFMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
674 ; CHECK32ZFBFMIN-NEXT: lui a0, %hi(.LCPI12_0)
675 ; CHECK32ZFBFMIN-NEXT: flw fa5, %lo(.LCPI12_0)(a0)
676 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
677 ; CHECK32ZFBFMIN-NEXT: flt.s a0, fa5, fa0
678 ; CHECK32ZFBFMIN-NEXT: neg s0, a0
679 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa5, zero
680 ; CHECK32ZFBFMIN-NEXT: fle.s a0, fa5, fa0
681 ; CHECK32ZFBFMIN-NEXT: neg s1, a0
682 ; CHECK32ZFBFMIN-NEXT: call __fixunssfdi@plt
683 ; CHECK32ZFBFMIN-NEXT: and a0, s1, a0
684 ; CHECK32ZFBFMIN-NEXT: or a0, s0, a0
685 ; CHECK32ZFBFMIN-NEXT: and a1, s1, a1
686 ; CHECK32ZFBFMIN-NEXT: or a1, s0, a1
687 ; CHECK32ZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
688 ; CHECK32ZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
689 ; CHECK32ZFBFMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
690 ; CHECK32ZFBFMIN-NEXT: addi sp, sp, 16
691 ; CHECK32ZFBFMIN-NEXT: ret
692 ;
693 ; RV32ID-LABEL: fcvt_lu_bf16_sat:
694 ; RV32ID: # %bb.0: # %start
695 ; RV32ID-NEXT: addi sp, sp, -16
696 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
697 ; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
698 ; RV32ID-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
699 ; RV32ID-NEXT: lui a0, %hi(.LCPI12_0)
700 ; RV32ID-NEXT: flw fa5, %lo(.LCPI12_0)(a0)
701 ; RV32ID-NEXT: fmv.x.w a0, fa0
702 ; RV32ID-NEXT: slli a0, a0, 16
703 ; RV32ID-NEXT: fmv.w.x fa0, a0
704 ; RV32ID-NEXT: flt.s a0, fa5, fa0
705 ; RV32ID-NEXT: neg s0, a0
706 ; RV32ID-NEXT: fmv.w.x fa5, zero
707 ; RV32ID-NEXT: fle.s a0, fa5, fa0
708 ; RV32ID-NEXT: neg s1, a0
709 ; RV32ID-NEXT: call __fixunssfdi@plt
710 ; RV32ID-NEXT: and a0, s1, a0
711 ; RV32ID-NEXT: or a0, s0, a0
712 ; RV32ID-NEXT: and a1, s1, a1
713 ; RV32ID-NEXT: or a1, s0, a1
714 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
715 ; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
716 ; RV32ID-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
717 ; RV32ID-NEXT: addi sp, sp, 16
718 ; RV32ID-NEXT: ret
719 ;
720 ; CHECK64ZFBFMIN-LABEL: fcvt_lu_bf16_sat:
721 ; CHECK64ZFBFMIN: # %bb.0: # %start
722 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
723 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
724 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
725 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
726 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
727 ; CHECK64ZFBFMIN-NEXT: and a0, a1, a0
728 ; CHECK64ZFBFMIN-NEXT: ret
729 ;
730 ; RV64ID-LABEL: fcvt_lu_bf16_sat:
731 ; RV64ID: # %bb.0: # %start
732 ; RV64ID-NEXT: fmv.x.w a0, fa0
733 ; RV64ID-NEXT: slli a0, a0, 48
734 ; RV64ID-NEXT: srli a0, a0, 48
735 ; RV64ID-NEXT: slli a0, a0, 16
736 ; RV64ID-NEXT: fmv.w.x fa5, a0
737 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
738 ; RV64ID-NEXT: feq.s a1, fa5, fa5
739 ; RV64ID-NEXT: seqz a1, a1
740 ; RV64ID-NEXT: addi a1, a1, -1
741 ; RV64ID-NEXT: and a0, a1, a0
742 ; RV64ID-NEXT: ret
743 start:
744 %0 = tail call i64 @llvm.fptoui.sat.i64.bf16(bfloat %a)
745 ret i64 %0
746 }
747 declare i64 @llvm.fptoui.sat.i64.bf16(bfloat)
749 define bfloat @fcvt_bf16_si(i16 %a) nounwind {
750 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_si:
751 ; CHECK32ZFBFMIN: # %bb.0:
752 ; CHECK32ZFBFMIN-NEXT: slli a0, a0, 16
753 ; CHECK32ZFBFMIN-NEXT: srai a0, a0, 16
754 ; CHECK32ZFBFMIN-NEXT: fcvt.s.w fa5, a0
755 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
756 ; CHECK32ZFBFMIN-NEXT: ret
757 ;
758 ; RV32ID-LABEL: fcvt_bf16_si:
759 ; RV32ID: # %bb.0:
760 ; RV32ID-NEXT: addi sp, sp, -16
761 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
762 ; RV32ID-NEXT: slli a0, a0, 16
763 ; RV32ID-NEXT: srai a0, a0, 16
764 ; RV32ID-NEXT: fcvt.s.w fa0, a0
765 ; RV32ID-NEXT: call __truncsfbf2@plt
766 ; RV32ID-NEXT: fmv.x.w a0, fa0
767 ; RV32ID-NEXT: lui a1, 1048560
768 ; RV32ID-NEXT: or a0, a0, a1
769 ; RV32ID-NEXT: fmv.w.x fa0, a0
770 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
771 ; RV32ID-NEXT: addi sp, sp, 16
772 ; RV32ID-NEXT: ret
773 ;
774 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_si:
775 ; CHECK64ZFBFMIN: # %bb.0:
776 ; CHECK64ZFBFMIN-NEXT: slli a0, a0, 48
777 ; CHECK64ZFBFMIN-NEXT: srai a0, a0, 48
778 ; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
779 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
780 ; CHECK64ZFBFMIN-NEXT: ret
781 ;
782 ; RV64ID-LABEL: fcvt_bf16_si:
783 ; RV64ID: # %bb.0:
784 ; RV64ID-NEXT: addi sp, sp, -16
785 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
786 ; RV64ID-NEXT: slli a0, a0, 48
787 ; RV64ID-NEXT: srai a0, a0, 48
788 ; RV64ID-NEXT: fcvt.s.w fa0, a0
789 ; RV64ID-NEXT: call __truncsfbf2@plt
790 ; RV64ID-NEXT: fmv.x.w a0, fa0
791 ; RV64ID-NEXT: lui a1, 1048560
792 ; RV64ID-NEXT: or a0, a0, a1
793 ; RV64ID-NEXT: fmv.w.x fa0, a0
794 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
795 ; RV64ID-NEXT: addi sp, sp, 16
796 ; RV64ID-NEXT: ret
797 %1 = sitofp i16 %a to bfloat
798 ret bfloat %1
799 }
801 define bfloat @fcvt_bf16_si_signext(i16 signext %a) nounwind {
802 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_si_signext:
803 ; CHECK32ZFBFMIN: # %bb.0:
804 ; CHECK32ZFBFMIN-NEXT: fcvt.s.w fa5, a0
805 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
806 ; CHECK32ZFBFMIN-NEXT: ret
807 ;
808 ; RV32ID-LABEL: fcvt_bf16_si_signext:
809 ; RV32ID: # %bb.0:
810 ; RV32ID-NEXT: addi sp, sp, -16
811 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
812 ; RV32ID-NEXT: fcvt.s.w fa0, a0
813 ; RV32ID-NEXT: call __truncsfbf2@plt
814 ; RV32ID-NEXT: fmv.x.w a0, fa0
815 ; RV32ID-NEXT: lui a1, 1048560
816 ; RV32ID-NEXT: or a0, a0, a1
817 ; RV32ID-NEXT: fmv.w.x fa0, a0
818 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
819 ; RV32ID-NEXT: addi sp, sp, 16
820 ; RV32ID-NEXT: ret
821 ;
822 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_si_signext:
823 ; CHECK64ZFBFMIN: # %bb.0:
824 ; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
825 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
826 ; CHECK64ZFBFMIN-NEXT: ret
827 ;
828 ; RV64ID-LABEL: fcvt_bf16_si_signext:
829 ; RV64ID: # %bb.0:
830 ; RV64ID-NEXT: addi sp, sp, -16
831 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
832 ; RV64ID-NEXT: fcvt.s.w fa0, a0
833 ; RV64ID-NEXT: call __truncsfbf2@plt
834 ; RV64ID-NEXT: fmv.x.w a0, fa0
835 ; RV64ID-NEXT: lui a1, 1048560
836 ; RV64ID-NEXT: or a0, a0, a1
837 ; RV64ID-NEXT: fmv.w.x fa0, a0
838 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
839 ; RV64ID-NEXT: addi sp, sp, 16
840 ; RV64ID-NEXT: ret
841 %1 = sitofp i16 %a to bfloat
842 ret bfloat %1
843 }
845 define bfloat @fcvt_bf16_ui(i16 %a) nounwind {
846 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_ui:
847 ; CHECK32ZFBFMIN: # %bb.0:
848 ; CHECK32ZFBFMIN-NEXT: slli a0, a0, 16
849 ; CHECK32ZFBFMIN-NEXT: srli a0, a0, 16
850 ; CHECK32ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
851 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
852 ; CHECK32ZFBFMIN-NEXT: ret
853 ;
854 ; RV32ID-LABEL: fcvt_bf16_ui:
855 ; RV32ID: # %bb.0:
856 ; RV32ID-NEXT: addi sp, sp, -16
857 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
858 ; RV32ID-NEXT: slli a0, a0, 16
859 ; RV32ID-NEXT: srli a0, a0, 16
860 ; RV32ID-NEXT: fcvt.s.wu fa0, a0
861 ; RV32ID-NEXT: call __truncsfbf2@plt
862 ; RV32ID-NEXT: fmv.x.w a0, fa0
863 ; RV32ID-NEXT: lui a1, 1048560
864 ; RV32ID-NEXT: or a0, a0, a1
865 ; RV32ID-NEXT: fmv.w.x fa0, a0
866 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
867 ; RV32ID-NEXT: addi sp, sp, 16
868 ; RV32ID-NEXT: ret
869 ;
870 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_ui:
871 ; CHECK64ZFBFMIN: # %bb.0:
872 ; CHECK64ZFBFMIN-NEXT: slli a0, a0, 48
873 ; CHECK64ZFBFMIN-NEXT: srli a0, a0, 48
874 ; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
875 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
876 ; CHECK64ZFBFMIN-NEXT: ret
877 ;
878 ; RV64ID-LABEL: fcvt_bf16_ui:
879 ; RV64ID: # %bb.0:
880 ; RV64ID-NEXT: addi sp, sp, -16
881 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
882 ; RV64ID-NEXT: slli a0, a0, 48
883 ; RV64ID-NEXT: srli a0, a0, 48
884 ; RV64ID-NEXT: fcvt.s.wu fa0, a0
885 ; RV64ID-NEXT: call __truncsfbf2@plt
886 ; RV64ID-NEXT: fmv.x.w a0, fa0
887 ; RV64ID-NEXT: lui a1, 1048560
888 ; RV64ID-NEXT: or a0, a0, a1
889 ; RV64ID-NEXT: fmv.w.x fa0, a0
890 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
891 ; RV64ID-NEXT: addi sp, sp, 16
892 ; RV64ID-NEXT: ret
893 %1 = uitofp i16 %a to bfloat
894 ret bfloat %1
895 }
897 define bfloat @fcvt_bf16_ui_zeroext(i16 zeroext %a) nounwind {
898 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_ui_zeroext:
899 ; CHECK32ZFBFMIN: # %bb.0:
900 ; CHECK32ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
901 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
902 ; CHECK32ZFBFMIN-NEXT: ret
903 ;
904 ; RV32ID-LABEL: fcvt_bf16_ui_zeroext:
905 ; RV32ID: # %bb.0:
906 ; RV32ID-NEXT: addi sp, sp, -16
907 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
908 ; RV32ID-NEXT: fcvt.s.wu fa0, a0
909 ; RV32ID-NEXT: call __truncsfbf2@plt
910 ; RV32ID-NEXT: fmv.x.w a0, fa0
911 ; RV32ID-NEXT: lui a1, 1048560
912 ; RV32ID-NEXT: or a0, a0, a1
913 ; RV32ID-NEXT: fmv.w.x fa0, a0
914 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
915 ; RV32ID-NEXT: addi sp, sp, 16
916 ; RV32ID-NEXT: ret
917 ;
918 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_ui_zeroext:
919 ; CHECK64ZFBFMIN: # %bb.0:
920 ; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
921 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
922 ; CHECK64ZFBFMIN-NEXT: ret
923 ;
924 ; RV64ID-LABEL: fcvt_bf16_ui_zeroext:
925 ; RV64ID: # %bb.0:
926 ; RV64ID-NEXT: addi sp, sp, -16
927 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
928 ; RV64ID-NEXT: fcvt.s.wu fa0, a0
929 ; RV64ID-NEXT: call __truncsfbf2@plt
930 ; RV64ID-NEXT: fmv.x.w a0, fa0
931 ; RV64ID-NEXT: lui a1, 1048560
932 ; RV64ID-NEXT: or a0, a0, a1
933 ; RV64ID-NEXT: fmv.w.x fa0, a0
934 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
935 ; RV64ID-NEXT: addi sp, sp, 16
936 ; RV64ID-NEXT: ret
937 %1 = uitofp i16 %a to bfloat
938 ret bfloat %1
939 }
941 define bfloat @fcvt_bf16_w(i32 %a) nounwind {
942 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_w:
943 ; CHECK32ZFBFMIN: # %bb.0:
944 ; CHECK32ZFBFMIN-NEXT: fcvt.s.w fa5, a0
945 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
946 ; CHECK32ZFBFMIN-NEXT: ret
947 ;
948 ; RV32ID-LABEL: fcvt_bf16_w:
949 ; RV32ID: # %bb.0:
950 ; RV32ID-NEXT: addi sp, sp, -16
951 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
952 ; RV32ID-NEXT: fcvt.s.w fa0, a0
953 ; RV32ID-NEXT: call __truncsfbf2@plt
954 ; RV32ID-NEXT: fmv.x.w a0, fa0
955 ; RV32ID-NEXT: lui a1, 1048560
956 ; RV32ID-NEXT: or a0, a0, a1
957 ; RV32ID-NEXT: fmv.w.x fa0, a0
958 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
959 ; RV32ID-NEXT: addi sp, sp, 16
960 ; RV32ID-NEXT: ret
961 ;
962 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_w:
963 ; CHECK64ZFBFMIN: # %bb.0:
964 ; CHECK64ZFBFMIN-NEXT: sext.w a0, a0
965 ; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
966 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
967 ; CHECK64ZFBFMIN-NEXT: ret
968 ;
969 ; RV64ID-LABEL: fcvt_bf16_w:
970 ; RV64ID: # %bb.0:
971 ; RV64ID-NEXT: addi sp, sp, -16
972 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
973 ; RV64ID-NEXT: fcvt.s.w fa0, a0
974 ; RV64ID-NEXT: call __truncsfbf2@plt
975 ; RV64ID-NEXT: fmv.x.w a0, fa0
976 ; RV64ID-NEXT: lui a1, 1048560
977 ; RV64ID-NEXT: or a0, a0, a1
978 ; RV64ID-NEXT: fmv.w.x fa0, a0
979 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
980 ; RV64ID-NEXT: addi sp, sp, 16
981 ; RV64ID-NEXT: ret
982 %1 = sitofp i32 %a to bfloat
983 ret bfloat %1
984 }
986 define bfloat @fcvt_bf16_w_load(ptr %p) nounwind {
987 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_w_load:
988 ; CHECK32ZFBFMIN: # %bb.0:
989 ; CHECK32ZFBFMIN-NEXT: lw a0, 0(a0)
990 ; CHECK32ZFBFMIN-NEXT: fcvt.s.w fa5, a0
991 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
992 ; CHECK32ZFBFMIN-NEXT: ret
993 ;
994 ; RV32ID-LABEL: fcvt_bf16_w_load:
995 ; RV32ID: # %bb.0:
996 ; RV32ID-NEXT: addi sp, sp, -16
997 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
998 ; RV32ID-NEXT: lw a0, 0(a0)
999 ; RV32ID-NEXT: fcvt.s.w fa0, a0
1000 ; RV32ID-NEXT: call __truncsfbf2@plt
1001 ; RV32ID-NEXT: fmv.x.w a0, fa0
1002 ; RV32ID-NEXT: lui a1, 1048560
1003 ; RV32ID-NEXT: or a0, a0, a1
1004 ; RV32ID-NEXT: fmv.w.x fa0, a0
1005 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1006 ; RV32ID-NEXT: addi sp, sp, 16
1007 ; RV32ID-NEXT: ret
1008 ;
1009 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_w_load:
1010 ; CHECK64ZFBFMIN: # %bb.0:
1011 ; CHECK64ZFBFMIN-NEXT: lw a0, 0(a0)
1012 ; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
1013 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1014 ; CHECK64ZFBFMIN-NEXT: ret
1015 ;
1016 ; RV64ID-LABEL: fcvt_bf16_w_load:
1017 ; RV64ID: # %bb.0:
1018 ; RV64ID-NEXT: addi sp, sp, -16
1019 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1020 ; RV64ID-NEXT: lw a0, 0(a0)
1021 ; RV64ID-NEXT: fcvt.s.w fa0, a0
1022 ; RV64ID-NEXT: call __truncsfbf2@plt
1023 ; RV64ID-NEXT: fmv.x.w a0, fa0
1024 ; RV64ID-NEXT: lui a1, 1048560
1025 ; RV64ID-NEXT: or a0, a0, a1
1026 ; RV64ID-NEXT: fmv.w.x fa0, a0
1027 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1028 ; RV64ID-NEXT: addi sp, sp, 16
1029 ; RV64ID-NEXT: ret
1030 %a = load i32, ptr %p
1031 %1 = sitofp i32 %a to bfloat
1032 ret bfloat %1
1033 }
1035 define bfloat @fcvt_bf16_wu(i32 %a) nounwind {
1036 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_wu:
1037 ; CHECK32ZFBFMIN: # %bb.0:
1038 ; CHECK32ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
1039 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1040 ; CHECK32ZFBFMIN-NEXT: ret
1041 ;
1042 ; RV32ID-LABEL: fcvt_bf16_wu:
1043 ; RV32ID: # %bb.0:
1044 ; RV32ID-NEXT: addi sp, sp, -16
1045 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1046 ; RV32ID-NEXT: fcvt.s.wu fa0, a0
1047 ; RV32ID-NEXT: call __truncsfbf2@plt
1048 ; RV32ID-NEXT: fmv.x.w a0, fa0
1049 ; RV32ID-NEXT: lui a1, 1048560
1050 ; RV32ID-NEXT: or a0, a0, a1
1051 ; RV32ID-NEXT: fmv.w.x fa0, a0
1052 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1053 ; RV32ID-NEXT: addi sp, sp, 16
1054 ; RV32ID-NEXT: ret
1055 ;
1056 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_wu:
1057 ; CHECK64ZFBFMIN: # %bb.0:
1058 ; CHECK64ZFBFMIN-NEXT: slli a0, a0, 32
1059 ; CHECK64ZFBFMIN-NEXT: srli a0, a0, 32
1060 ; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
1061 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1062 ; CHECK64ZFBFMIN-NEXT: ret
1063 ;
1064 ; RV64ID-LABEL: fcvt_bf16_wu:
1065 ; RV64ID: # %bb.0:
1066 ; RV64ID-NEXT: addi sp, sp, -16
1067 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1068 ; RV64ID-NEXT: fcvt.s.wu fa0, a0
1069 ; RV64ID-NEXT: call __truncsfbf2@plt
1070 ; RV64ID-NEXT: fmv.x.w a0, fa0
1071 ; RV64ID-NEXT: lui a1, 1048560
1072 ; RV64ID-NEXT: or a0, a0, a1
1073 ; RV64ID-NEXT: fmv.w.x fa0, a0
1074 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1075 ; RV64ID-NEXT: addi sp, sp, 16
1076 ; RV64ID-NEXT: ret
1077 %1 = uitofp i32 %a to bfloat
1078 ret bfloat %1
1079 }
1081 define bfloat @fcvt_bf16_wu_load(ptr %p) nounwind {
1082 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_wu_load:
1083 ; CHECK32ZFBFMIN: # %bb.0:
1084 ; CHECK32ZFBFMIN-NEXT: lw a0, 0(a0)
1085 ; CHECK32ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
1086 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1087 ; CHECK32ZFBFMIN-NEXT: ret
1088 ;
1089 ; RV32ID-LABEL: fcvt_bf16_wu_load:
1090 ; RV32ID: # %bb.0:
1091 ; RV32ID-NEXT: addi sp, sp, -16
1092 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1093 ; RV32ID-NEXT: lw a0, 0(a0)
1094 ; RV32ID-NEXT: fcvt.s.wu fa0, a0
1095 ; RV32ID-NEXT: call __truncsfbf2@plt
1096 ; RV32ID-NEXT: fmv.x.w a0, fa0
1097 ; RV32ID-NEXT: lui a1, 1048560
1098 ; RV32ID-NEXT: or a0, a0, a1
1099 ; RV32ID-NEXT: fmv.w.x fa0, a0
1100 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1101 ; RV32ID-NEXT: addi sp, sp, 16
1102 ; RV32ID-NEXT: ret
1103 ;
1104 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_wu_load:
1105 ; CHECK64ZFBFMIN: # %bb.0:
1106 ; CHECK64ZFBFMIN-NEXT: lwu a0, 0(a0)
1107 ; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a0
1108 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1109 ; CHECK64ZFBFMIN-NEXT: ret
1110 ;
1111 ; RV64ID-LABEL: fcvt_bf16_wu_load:
1112 ; RV64ID: # %bb.0:
1113 ; RV64ID-NEXT: addi sp, sp, -16
1114 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1115 ; RV64ID-NEXT: lwu a0, 0(a0)
1116 ; RV64ID-NEXT: fcvt.s.wu fa0, a0
1117 ; RV64ID-NEXT: call __truncsfbf2@plt
1118 ; RV64ID-NEXT: fmv.x.w a0, fa0
1119 ; RV64ID-NEXT: lui a1, 1048560
1120 ; RV64ID-NEXT: or a0, a0, a1
1121 ; RV64ID-NEXT: fmv.w.x fa0, a0
1122 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1123 ; RV64ID-NEXT: addi sp, sp, 16
1124 ; RV64ID-NEXT: ret
1125 %a = load i32, ptr %p
1126 %1 = uitofp i32 %a to bfloat
1127 ret bfloat %1
1128 }
1130 ; TODO: The following tests error on rv32 with zfbfmin enabled.
1132 ; define bfloat @fcvt_bf16_l(i64 %a) nounwind {
1133 ; %1 = sitofp i64 %a to bfloat
1134 ; ret bfloat %1
1135 ; }
1137 ; define bfloat @fcvt_bf16_lu(i64 %a) nounwind {
1138 ; %1 = uitofp i64 %a to bfloat
1139 ; ret bfloat %1
1140 ; }
1142 define bfloat @fcvt_bf16_s(float %a) nounwind {
1143 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_s:
1144 ; CHECK32ZFBFMIN: # %bb.0:
1145 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa0
1146 ; CHECK32ZFBFMIN-NEXT: ret
1147 ;
1148 ; RV32ID-LABEL: fcvt_bf16_s:
1149 ; RV32ID: # %bb.0:
1150 ; RV32ID-NEXT: addi sp, sp, -16
1151 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1152 ; RV32ID-NEXT: call __truncsfbf2@plt
1153 ; RV32ID-NEXT: fmv.x.w a0, fa0
1154 ; RV32ID-NEXT: lui a1, 1048560
1155 ; RV32ID-NEXT: or a0, a0, a1
1156 ; RV32ID-NEXT: fmv.w.x fa0, a0
1157 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1158 ; RV32ID-NEXT: addi sp, sp, 16
1159 ; RV32ID-NEXT: ret
1160 ;
1161 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_s:
1162 ; CHECK64ZFBFMIN: # %bb.0:
1163 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa0, fa0
1164 ; CHECK64ZFBFMIN-NEXT: ret
1165 ;
1166 ; RV64ID-LABEL: fcvt_bf16_s:
1167 ; RV64ID: # %bb.0:
1168 ; RV64ID-NEXT: addi sp, sp, -16
1169 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1170 ; RV64ID-NEXT: call __truncsfbf2@plt
1171 ; RV64ID-NEXT: fmv.x.w a0, fa0
1172 ; RV64ID-NEXT: lui a1, 1048560
1173 ; RV64ID-NEXT: or a0, a0, a1
1174 ; RV64ID-NEXT: fmv.w.x fa0, a0
1175 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1176 ; RV64ID-NEXT: addi sp, sp, 16
1177 ; RV64ID-NEXT: ret
1178 %1 = fptrunc float %a to bfloat
1179 ret bfloat %1
1180 }
1182 define float @fcvt_s_bf16(bfloat %a) nounwind {
1183 ; CHECK32ZFBFMIN-LABEL: fcvt_s_bf16:
1184 ; CHECK32ZFBFMIN: # %bb.0:
1185 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
1186 ; CHECK32ZFBFMIN-NEXT: ret
1187 ;
1188 ; RV32ID-LABEL: fcvt_s_bf16:
1189 ; RV32ID: # %bb.0:
1190 ; RV32ID-NEXT: fmv.x.w a0, fa0
1191 ; RV32ID-NEXT: slli a0, a0, 16
1192 ; RV32ID-NEXT: fmv.w.x fa0, a0
1193 ; RV32ID-NEXT: ret
1194 ;
1195 ; CHECK64ZFBFMIN-LABEL: fcvt_s_bf16:
1196 ; CHECK64ZFBFMIN: # %bb.0:
1197 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
1198 ; CHECK64ZFBFMIN-NEXT: ret
1199 ;
1200 ; RV64ID-LABEL: fcvt_s_bf16:
1201 ; RV64ID: # %bb.0:
1202 ; RV64ID-NEXT: fmv.x.w a0, fa0
1203 ; RV64ID-NEXT: slli a0, a0, 48
1204 ; RV64ID-NEXT: srli a0, a0, 48
1205 ; RV64ID-NEXT: slli a0, a0, 16
1206 ; RV64ID-NEXT: fmv.w.x fa0, a0
1207 ; RV64ID-NEXT: ret
1208 %1 = fpext bfloat %a to float
1209 ret float %1
1210 }
1212 define bfloat @fcvt_bf16_d(double %a) nounwind {
1213 ; RV32IZFBFMIN-LABEL: fcvt_bf16_d:
1214 ; RV32IZFBFMIN: # %bb.0:
1215 ; RV32IZFBFMIN-NEXT: addi sp, sp, -16
1216 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1217 ; RV32IZFBFMIN-NEXT: call __truncdfbf2@plt
1218 ; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1219 ; RV32IZFBFMIN-NEXT: addi sp, sp, 16
1220 ; RV32IZFBFMIN-NEXT: ret
1221 ;
1222 ; R32IDZFBFMIN-LABEL: fcvt_bf16_d:
1223 ; R32IDZFBFMIN: # %bb.0:
1224 ; R32IDZFBFMIN-NEXT: fcvt.s.d fa5, fa0
1225 ; R32IDZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1226 ; R32IDZFBFMIN-NEXT: ret
1227 ;
1228 ; RV32ID-LABEL: fcvt_bf16_d:
1229 ; RV32ID: # %bb.0:
1230 ; RV32ID-NEXT: addi sp, sp, -16
1231 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1232 ; RV32ID-NEXT: call __truncdfbf2@plt
1233 ; RV32ID-NEXT: fmv.x.w a0, fa0
1234 ; RV32ID-NEXT: lui a1, 1048560
1235 ; RV32ID-NEXT: or a0, a0, a1
1236 ; RV32ID-NEXT: fmv.w.x fa0, a0
1237 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1238 ; RV32ID-NEXT: addi sp, sp, 16
1239 ; RV32ID-NEXT: ret
1240 ;
1241 ; RV64IZFBFMIN-LABEL: fcvt_bf16_d:
1242 ; RV64IZFBFMIN: # %bb.0:
1243 ; RV64IZFBFMIN-NEXT: addi sp, sp, -16
1244 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1245 ; RV64IZFBFMIN-NEXT: call __truncdfbf2@plt
1246 ; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1247 ; RV64IZFBFMIN-NEXT: addi sp, sp, 16
1248 ; RV64IZFBFMIN-NEXT: ret
1249 ;
1250 ; RV64IDZFBFMIN-LABEL: fcvt_bf16_d:
1251 ; RV64IDZFBFMIN: # %bb.0:
1252 ; RV64IDZFBFMIN-NEXT: fcvt.s.d fa5, fa0
1253 ; RV64IDZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
1254 ; RV64IDZFBFMIN-NEXT: ret
1255 ;
1256 ; RV64ID-LABEL: fcvt_bf16_d:
1257 ; RV64ID: # %bb.0:
1258 ; RV64ID-NEXT: addi sp, sp, -16
1259 ; RV64ID-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1260 ; RV64ID-NEXT: call __truncdfbf2@plt
1261 ; RV64ID-NEXT: fmv.x.w a0, fa0
1262 ; RV64ID-NEXT: lui a1, 1048560
1263 ; RV64ID-NEXT: or a0, a0, a1
1264 ; RV64ID-NEXT: fmv.w.x fa0, a0
1265 ; RV64ID-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1266 ; RV64ID-NEXT: addi sp, sp, 16
1267 ; RV64ID-NEXT: ret
1268 %1 = fptrunc double %a to bfloat
1269 ret bfloat %1
1270 }
1272 define double @fcvt_d_bf16(bfloat %a) nounwind {
1273 ; RV32IZFBFMIN-LABEL: fcvt_d_bf16:
1274 ; RV32IZFBFMIN: # %bb.0:
1275 ; RV32IZFBFMIN-NEXT: addi sp, sp, -16
1276 ; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1277 ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
1278 ; RV32IZFBFMIN-NEXT: call __extendsfdf2@plt
1279 ; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1280 ; RV32IZFBFMIN-NEXT: addi sp, sp, 16
1281 ; RV32IZFBFMIN-NEXT: ret
1282 ;
1283 ; R32IDZFBFMIN-LABEL: fcvt_d_bf16:
1284 ; R32IDZFBFMIN: # %bb.0:
1285 ; R32IDZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1286 ; R32IDZFBFMIN-NEXT: fcvt.d.s fa0, fa5
1287 ; R32IDZFBFMIN-NEXT: ret
1288 ;
1289 ; RV32ID-LABEL: fcvt_d_bf16:
1290 ; RV32ID: # %bb.0:
1291 ; RV32ID-NEXT: fmv.x.w a0, fa0
1292 ; RV32ID-NEXT: slli a0, a0, 16
1293 ; RV32ID-NEXT: fmv.w.x fa5, a0
1294 ; RV32ID-NEXT: fcvt.d.s fa0, fa5
1295 ; RV32ID-NEXT: ret
1296 ;
1297 ; RV64IZFBFMIN-LABEL: fcvt_d_bf16:
1298 ; RV64IZFBFMIN: # %bb.0:
1299 ; RV64IZFBFMIN-NEXT: addi sp, sp, -16
1300 ; RV64IZFBFMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
1301 ; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa0, fa0
1302 ; RV64IZFBFMIN-NEXT: call __extendsfdf2@plt
1303 ; RV64IZFBFMIN-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
1304 ; RV64IZFBFMIN-NEXT: addi sp, sp, 16
1305 ; RV64IZFBFMIN-NEXT: ret
1306 ;
1307 ; RV64IDZFBFMIN-LABEL: fcvt_d_bf16:
1308 ; RV64IDZFBFMIN: # %bb.0:
1309 ; RV64IDZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1310 ; RV64IDZFBFMIN-NEXT: fcvt.d.s fa0, fa5
1311 ; RV64IDZFBFMIN-NEXT: ret
1312 ;
1313 ; RV64ID-LABEL: fcvt_d_bf16:
1314 ; RV64ID: # %bb.0:
1315 ; RV64ID-NEXT: fmv.x.w a0, fa0
1316 ; RV64ID-NEXT: slli a0, a0, 48
1317 ; RV64ID-NEXT: srli a0, a0, 48
1318 ; RV64ID-NEXT: slli a0, a0, 16
1319 ; RV64ID-NEXT: fmv.w.x fa5, a0
1320 ; RV64ID-NEXT: fcvt.d.s fa0, fa5
1321 ; RV64ID-NEXT: ret
1322 %1 = fpext bfloat %a to double
1323 ret double %1
1324 }
1326 define bfloat @bitcast_bf16_i16(i16 %a) nounwind {
1327 ; CHECK32ZFBFMIN-LABEL: bitcast_bf16_i16:
1328 ; CHECK32ZFBFMIN: # %bb.0:
1329 ; CHECK32ZFBFMIN-NEXT: fmv.h.x fa0, a0
1330 ; CHECK32ZFBFMIN-NEXT: ret
1331 ;
1332 ; RV32ID-LABEL: bitcast_bf16_i16:
1333 ; RV32ID: # %bb.0:
1334 ; RV32ID-NEXT: lui a1, 1048560
1335 ; RV32ID-NEXT: or a0, a0, a1
1336 ; RV32ID-NEXT: fmv.w.x fa0, a0
1337 ; RV32ID-NEXT: ret
1338 ;
1339 ; CHECK64ZFBFMIN-LABEL: bitcast_bf16_i16:
1340 ; CHECK64ZFBFMIN: # %bb.0:
1341 ; CHECK64ZFBFMIN-NEXT: fmv.h.x fa0, a0
1342 ; CHECK64ZFBFMIN-NEXT: ret
1343 ;
1344 ; RV64ID-LABEL: bitcast_bf16_i16:
1345 ; RV64ID: # %bb.0:
1346 ; RV64ID-NEXT: lui a1, 1048560
1347 ; RV64ID-NEXT: or a0, a0, a1
1348 ; RV64ID-NEXT: fmv.w.x fa0, a0
1349 ; RV64ID-NEXT: ret
1350 %1 = bitcast i16 %a to bfloat
1351 ret bfloat %1
1352 }
1354 define i16 @bitcast_i16_bf16(bfloat %a) nounwind {
1355 ; CHECK32ZFBFMIN-LABEL: bitcast_i16_bf16:
1356 ; CHECK32ZFBFMIN: # %bb.0:
1357 ; CHECK32ZFBFMIN-NEXT: fmv.x.h a0, fa0
1358 ; CHECK32ZFBFMIN-NEXT: ret
1359 ;
1360 ; RV32ID-LABEL: bitcast_i16_bf16:
1361 ; RV32ID: # %bb.0:
1362 ; RV32ID-NEXT: fmv.x.w a0, fa0
1363 ; RV32ID-NEXT: ret
1364 ;
1365 ; CHECK64ZFBFMIN-LABEL: bitcast_i16_bf16:
1366 ; CHECK64ZFBFMIN: # %bb.0:
1367 ; CHECK64ZFBFMIN-NEXT: fmv.x.h a0, fa0
1368 ; CHECK64ZFBFMIN-NEXT: ret
1369 ;
1370 ; RV64ID-LABEL: bitcast_i16_bf16:
1371 ; RV64ID: # %bb.0:
1372 ; RV64ID-NEXT: fmv.x.w a0, fa0
1373 ; RV64ID-NEXT: ret
1374 %1 = bitcast bfloat %a to i16
1375 ret i16 %1
1376 }
1378 define signext i32 @fcvt_bf16_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
1379 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_w_demanded_bits:
1380 ; CHECK32ZFBFMIN: # %bb.0:
1381 ; CHECK32ZFBFMIN-NEXT: addi a0, a0, 1
1382 ; CHECK32ZFBFMIN-NEXT: fcvt.s.w fa5, a0
1383 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
1384 ; CHECK32ZFBFMIN-NEXT: fsh fa5, 0(a1)
1385 ; CHECK32ZFBFMIN-NEXT: ret
1386 ;
1387 ; RV32ID-LABEL: fcvt_bf16_w_demanded_bits:
1388 ; RV32ID: # %bb.0:
1389 ; RV32ID-NEXT: addi sp, sp, -16
1390 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1391 ; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1392 ; RV32ID-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1393 ; RV32ID-NEXT: mv s0, a1
1394 ; RV32ID-NEXT: addi s1, a0, 1
1395 ; RV32ID-NEXT: fcvt.s.w fa0, s1
1396 ; RV32ID-NEXT: call __truncsfbf2@plt
1397 ; RV32ID-NEXT: fmv.x.w a0, fa0
1398 ; RV32ID-NEXT: sh a0, 0(s0)
1399 ; RV32ID-NEXT: mv a0, s1
1400 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1401 ; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1402 ; RV32ID-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1403 ; RV32ID-NEXT: addi sp, sp, 16
1404 ; RV32ID-NEXT: ret
1405 ;
1406 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_w_demanded_bits:
1407 ; CHECK64ZFBFMIN: # %bb.0:
1408 ; CHECK64ZFBFMIN-NEXT: addiw a0, a0, 1
1409 ; CHECK64ZFBFMIN-NEXT: fcvt.s.l fa5, a0
1410 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
1411 ; CHECK64ZFBFMIN-NEXT: fsh fa5, 0(a1)
1412 ; CHECK64ZFBFMIN-NEXT: ret
1413 ;
1414 ; RV64ID-LABEL: fcvt_bf16_w_demanded_bits:
1415 ; RV64ID: # %bb.0:
1416 ; RV64ID-NEXT: addi sp, sp, -32
1417 ; RV64ID-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1418 ; RV64ID-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1419 ; RV64ID-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1420 ; RV64ID-NEXT: mv s0, a1
1421 ; RV64ID-NEXT: addiw s1, a0, 1
1422 ; RV64ID-NEXT: fcvt.s.w fa0, s1
1423 ; RV64ID-NEXT: call __truncsfbf2@plt
1424 ; RV64ID-NEXT: fmv.x.w a0, fa0
1425 ; RV64ID-NEXT: sh a0, 0(s0)
1426 ; RV64ID-NEXT: mv a0, s1
1427 ; RV64ID-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1428 ; RV64ID-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1429 ; RV64ID-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1430 ; RV64ID-NEXT: addi sp, sp, 32
1431 ; RV64ID-NEXT: ret
1432 %3 = add i32 %0, 1
1433 %4 = sitofp i32 %3 to bfloat
1434 store bfloat %4, ptr %1, align 2
1435 ret i32 %3
1436 }
1438 define signext i32 @fcvt_bf16_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {
1439 ; CHECK32ZFBFMIN-LABEL: fcvt_bf16_wu_demanded_bits:
1440 ; CHECK32ZFBFMIN: # %bb.0:
1441 ; CHECK32ZFBFMIN-NEXT: addi a0, a0, 1
1442 ; CHECK32ZFBFMIN-NEXT: fcvt.s.wu fa5, a0
1443 ; CHECK32ZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
1444 ; CHECK32ZFBFMIN-NEXT: fsh fa5, 0(a1)
1445 ; CHECK32ZFBFMIN-NEXT: ret
1446 ;
1447 ; RV32ID-LABEL: fcvt_bf16_wu_demanded_bits:
1448 ; RV32ID: # %bb.0:
1449 ; RV32ID-NEXT: addi sp, sp, -16
1450 ; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
1451 ; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
1452 ; RV32ID-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
1453 ; RV32ID-NEXT: mv s0, a1
1454 ; RV32ID-NEXT: addi s1, a0, 1
1455 ; RV32ID-NEXT: fcvt.s.wu fa0, s1
1456 ; RV32ID-NEXT: call __truncsfbf2@plt
1457 ; RV32ID-NEXT: fmv.x.w a0, fa0
1458 ; RV32ID-NEXT: sh a0, 0(s0)
1459 ; RV32ID-NEXT: mv a0, s1
1460 ; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
1461 ; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
1462 ; RV32ID-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
1463 ; RV32ID-NEXT: addi sp, sp, 16
1464 ; RV32ID-NEXT: ret
1465 ;
1466 ; CHECK64ZFBFMIN-LABEL: fcvt_bf16_wu_demanded_bits:
1467 ; CHECK64ZFBFMIN: # %bb.0:
1468 ; CHECK64ZFBFMIN-NEXT: addiw a0, a0, 1
1469 ; CHECK64ZFBFMIN-NEXT: slli a2, a0, 32
1470 ; CHECK64ZFBFMIN-NEXT: srli a2, a2, 32
1471 ; CHECK64ZFBFMIN-NEXT: fcvt.s.lu fa5, a2
1472 ; CHECK64ZFBFMIN-NEXT: fcvt.bf16.s fa5, fa5
1473 ; CHECK64ZFBFMIN-NEXT: fsh fa5, 0(a1)
1474 ; CHECK64ZFBFMIN-NEXT: ret
1475 ;
1476 ; RV64ID-LABEL: fcvt_bf16_wu_demanded_bits:
1477 ; RV64ID: # %bb.0:
1478 ; RV64ID-NEXT: addi sp, sp, -32
1479 ; RV64ID-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
1480 ; RV64ID-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
1481 ; RV64ID-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
1482 ; RV64ID-NEXT: mv s0, a1
1483 ; RV64ID-NEXT: addiw s1, a0, 1
1484 ; RV64ID-NEXT: fcvt.s.wu fa0, s1
1485 ; RV64ID-NEXT: call __truncsfbf2@plt
1486 ; RV64ID-NEXT: fmv.x.w a0, fa0
1487 ; RV64ID-NEXT: sh a0, 0(s0)
1488 ; RV64ID-NEXT: mv a0, s1
1489 ; RV64ID-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
1490 ; RV64ID-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
1491 ; RV64ID-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
1492 ; RV64ID-NEXT: addi sp, sp, 32
1493 ; RV64ID-NEXT: ret
1494 %3 = add i32 %0, 1
1495 %4 = uitofp i32 %3 to bfloat
1496 store bfloat %4, ptr %1, align 2
1497 ret i32 %3
1498 }
1500 define signext i8 @fcvt_w_s_i8(bfloat %a) nounwind {
1501 ; CHECK32ZFBFMIN-LABEL: fcvt_w_s_i8:
1502 ; CHECK32ZFBFMIN: # %bb.0:
1503 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1504 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
1505 ; CHECK32ZFBFMIN-NEXT: ret
1506 ;
1507 ; RV32ID-LABEL: fcvt_w_s_i8:
1508 ; RV32ID: # %bb.0:
1509 ; RV32ID-NEXT: fmv.x.w a0, fa0
1510 ; RV32ID-NEXT: slli a0, a0, 16
1511 ; RV32ID-NEXT: fmv.w.x fa5, a0
1512 ; RV32ID-NEXT: fcvt.w.s a0, fa5, rtz
1513 ; RV32ID-NEXT: ret
1514 ;
1515 ; CHECK64ZFBFMIN-LABEL: fcvt_w_s_i8:
1516 ; CHECK64ZFBFMIN: # %bb.0:
1517 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1518 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
1519 ; CHECK64ZFBFMIN-NEXT: ret
1520 ;
1521 ; RV64ID-LABEL: fcvt_w_s_i8:
1522 ; RV64ID: # %bb.0:
1523 ; RV64ID-NEXT: fmv.x.w a0, fa0
1524 ; RV64ID-NEXT: slli a0, a0, 48
1525 ; RV64ID-NEXT: srli a0, a0, 48
1526 ; RV64ID-NEXT: slli a0, a0, 16
1527 ; RV64ID-NEXT: fmv.w.x fa5, a0
1528 ; RV64ID-NEXT: fcvt.l.s a0, fa5, rtz
1529 ; RV64ID-NEXT: ret
1530 %1 = fptosi bfloat %a to i8
1531 ret i8 %1
1532 }
1534 define signext i8 @fcvt_w_s_sat_i8(bfloat %a) nounwind {
1535 ; CHECK32ZFBFMIN-LABEL: fcvt_w_s_sat_i8:
1536 ; CHECK32ZFBFMIN: # %bb.0: # %start
1537 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1538 ; CHECK32ZFBFMIN-NEXT: feq.s a0, fa5, fa5
1539 ; CHECK32ZFBFMIN-NEXT: neg a0, a0
1540 ; CHECK32ZFBFMIN-NEXT: lui a1, 798720
1541 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, a1
1542 ; CHECK32ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
1543 ; CHECK32ZFBFMIN-NEXT: lui a1, 274400
1544 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, a1
1545 ; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
1546 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a1, fa5, rtz
1547 ; CHECK32ZFBFMIN-NEXT: and a0, a0, a1
1548 ; CHECK32ZFBFMIN-NEXT: ret
1549 ;
1550 ; RV32ID-LABEL: fcvt_w_s_sat_i8:
1551 ; RV32ID: # %bb.0: # %start
1552 ; RV32ID-NEXT: fmv.x.w a0, fa0
1553 ; RV32ID-NEXT: slli a0, a0, 16
1554 ; RV32ID-NEXT: fmv.w.x fa5, a0
1555 ; RV32ID-NEXT: feq.s a0, fa5, fa5
1556 ; RV32ID-NEXT: neg a0, a0
1557 ; RV32ID-NEXT: lui a1, 798720
1558 ; RV32ID-NEXT: fmv.w.x fa4, a1
1559 ; RV32ID-NEXT: fmax.s fa5, fa5, fa4
1560 ; RV32ID-NEXT: lui a1, 274400
1561 ; RV32ID-NEXT: fmv.w.x fa4, a1
1562 ; RV32ID-NEXT: fmin.s fa5, fa5, fa4
1563 ; RV32ID-NEXT: fcvt.w.s a1, fa5, rtz
1564 ; RV32ID-NEXT: and a0, a0, a1
1565 ; RV32ID-NEXT: ret
1566 ;
1567 ; CHECK64ZFBFMIN-LABEL: fcvt_w_s_sat_i8:
1568 ; CHECK64ZFBFMIN: # %bb.0: # %start
1569 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1570 ; CHECK64ZFBFMIN-NEXT: feq.s a0, fa5, fa5
1571 ; CHECK64ZFBFMIN-NEXT: neg a0, a0
1572 ; CHECK64ZFBFMIN-NEXT: lui a1, 798720
1573 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, a1
1574 ; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
1575 ; CHECK64ZFBFMIN-NEXT: lui a1, 274400
1576 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, a1
1577 ; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
1578 ; CHECK64ZFBFMIN-NEXT: fcvt.l.s a1, fa5, rtz
1579 ; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
1580 ; CHECK64ZFBFMIN-NEXT: ret
1581 ;
1582 ; RV64ID-LABEL: fcvt_w_s_sat_i8:
1583 ; RV64ID: # %bb.0: # %start
1584 ; RV64ID-NEXT: fmv.x.w a0, fa0
1585 ; RV64ID-NEXT: slli a0, a0, 48
1586 ; RV64ID-NEXT: srli a0, a0, 48
1587 ; RV64ID-NEXT: slli a0, a0, 16
1588 ; RV64ID-NEXT: fmv.w.x fa5, a0
1589 ; RV64ID-NEXT: feq.s a0, fa5, fa5
1590 ; RV64ID-NEXT: neg a0, a0
1591 ; RV64ID-NEXT: lui a1, 798720
1592 ; RV64ID-NEXT: fmv.w.x fa4, a1
1593 ; RV64ID-NEXT: fmax.s fa5, fa5, fa4
1594 ; RV64ID-NEXT: lui a1, 274400
1595 ; RV64ID-NEXT: fmv.w.x fa4, a1
1596 ; RV64ID-NEXT: fmin.s fa5, fa5, fa4
1597 ; RV64ID-NEXT: fcvt.l.s a1, fa5, rtz
1598 ; RV64ID-NEXT: and a0, a0, a1
1599 ; RV64ID-NEXT: ret
1600 start:
1601 %0 = tail call i8 @llvm.fptosi.sat.i8.bf16(bfloat %a)
1602 ret i8 %0
1603 }
1604 declare i8 @llvm.fptosi.sat.i8.bf16(bfloat)
1606 define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
1607 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_s_i8:
1608 ; CHECK32ZFBFMIN: # %bb.0:
1609 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1610 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1611 ; CHECK32ZFBFMIN-NEXT: ret
1612 ;
1613 ; RV32ID-LABEL: fcvt_wu_s_i8:
1614 ; RV32ID: # %bb.0:
1615 ; RV32ID-NEXT: fmv.x.w a0, fa0
1616 ; RV32ID-NEXT: slli a0, a0, 16
1617 ; RV32ID-NEXT: fmv.w.x fa5, a0
1618 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
1619 ; RV32ID-NEXT: ret
1620 ;
1621 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_s_i8:
1622 ; CHECK64ZFBFMIN: # %bb.0:
1623 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
1624 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1625 ; CHECK64ZFBFMIN-NEXT: ret
1626 ;
1627 ; RV64ID-LABEL: fcvt_wu_s_i8:
1628 ; RV64ID: # %bb.0:
1629 ; RV64ID-NEXT: fmv.x.w a0, fa0
1630 ; RV64ID-NEXT: slli a0, a0, 48
1631 ; RV64ID-NEXT: srli a0, a0, 48
1632 ; RV64ID-NEXT: slli a0, a0, 16
1633 ; RV64ID-NEXT: fmv.w.x fa5, a0
1634 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
1635 ; RV64ID-NEXT: ret
1636 %1 = fptoui bfloat %a to i8
1637 ret i8 %1
1638 }
1640 define zeroext i8 @fcvt_wu_s_sat_i8(bfloat %a) nounwind {
1641 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_s_sat_i8:
1642 ; CHECK32ZFBFMIN: # %bb.0: # %start
1643 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1644 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, zero
1645 ; CHECK32ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
1646 ; CHECK32ZFBFMIN-NEXT: lui a0, 276464
1647 ; CHECK32ZFBFMIN-NEXT: fmv.w.x fa4, a0
1648 ; CHECK32ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
1649 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1650 ; CHECK32ZFBFMIN-NEXT: ret
1651 ;
1652 ; RV32ID-LABEL: fcvt_wu_s_sat_i8:
1653 ; RV32ID: # %bb.0: # %start
1654 ; RV32ID-NEXT: fmv.x.w a0, fa0
1655 ; RV32ID-NEXT: slli a0, a0, 16
1656 ; RV32ID-NEXT: fmv.w.x fa5, a0
1657 ; RV32ID-NEXT: fmv.w.x fa4, zero
1658 ; RV32ID-NEXT: fmax.s fa5, fa5, fa4
1659 ; RV32ID-NEXT: lui a0, 276464
1660 ; RV32ID-NEXT: fmv.w.x fa4, a0
1661 ; RV32ID-NEXT: fmin.s fa5, fa5, fa4
1662 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
1663 ; RV32ID-NEXT: ret
1664 ;
1665 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_s_sat_i8:
1666 ; CHECK64ZFBFMIN: # %bb.0: # %start
1667 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1668 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, zero
1669 ; CHECK64ZFBFMIN-NEXT: fmax.s fa5, fa5, fa4
1670 ; CHECK64ZFBFMIN-NEXT: lui a0, 276464
1671 ; CHECK64ZFBFMIN-NEXT: fmv.w.x fa4, a0
1672 ; CHECK64ZFBFMIN-NEXT: fmin.s fa5, fa5, fa4
1673 ; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
1674 ; CHECK64ZFBFMIN-NEXT: ret
1675 ;
1676 ; RV64ID-LABEL: fcvt_wu_s_sat_i8:
1677 ; RV64ID: # %bb.0: # %start
1678 ; RV64ID-NEXT: fmv.x.w a0, fa0
1679 ; RV64ID-NEXT: slli a0, a0, 48
1680 ; RV64ID-NEXT: srli a0, a0, 48
1681 ; RV64ID-NEXT: slli a0, a0, 16
1682 ; RV64ID-NEXT: fmv.w.x fa5, a0
1683 ; RV64ID-NEXT: fmv.w.x fa4, zero
1684 ; RV64ID-NEXT: fmax.s fa5, fa5, fa4
1685 ; RV64ID-NEXT: lui a0, 276464
1686 ; RV64ID-NEXT: fmv.w.x fa4, a0
1687 ; RV64ID-NEXT: fmin.s fa5, fa5, fa4
1688 ; RV64ID-NEXT: fcvt.lu.s a0, fa5, rtz
1689 ; RV64ID-NEXT: ret
1690 start:
1691 %0 = tail call i8 @llvm.fptoui.sat.i8.bf16(bfloat %a)
1692 ret i8 %0
1693 }
1694 declare i8 @llvm.fptoui.sat.i8.bf16(bfloat)
1696 define zeroext i32 @fcvt_wu_bf16_sat_zext(bfloat %a) nounwind {
1697 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16_sat_zext:
1698 ; CHECK32ZFBFMIN: # %bb.0: # %start
1699 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1700 ; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1701 ; CHECK32ZFBFMIN-NEXT: feq.s a1, fa5, fa5
1702 ; CHECK32ZFBFMIN-NEXT: seqz a1, a1
1703 ; CHECK32ZFBFMIN-NEXT: addi a1, a1, -1
1704 ; CHECK32ZFBFMIN-NEXT: and a0, a1, a0
1705 ; CHECK32ZFBFMIN-NEXT: ret
1706 ;
1707 ; RV32ID-LABEL: fcvt_wu_bf16_sat_zext:
1708 ; RV32ID: # %bb.0: # %start
1709 ; RV32ID-NEXT: fmv.x.w a0, fa0
1710 ; RV32ID-NEXT: slli a0, a0, 16
1711 ; RV32ID-NEXT: fmv.w.x fa5, a0
1712 ; RV32ID-NEXT: fcvt.wu.s a0, fa5, rtz
1713 ; RV32ID-NEXT: feq.s a1, fa5, fa5
1714 ; RV32ID-NEXT: seqz a1, a1
1715 ; RV32ID-NEXT: addi a1, a1, -1
1716 ; RV32ID-NEXT: and a0, a1, a0
1717 ; RV32ID-NEXT: ret
1718 ;
1719 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_bf16_sat_zext:
1720 ; CHECK64ZFBFMIN: # %bb.0: # %start
1721 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1722 ; CHECK64ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
1723 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
1724 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
1725 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
1726 ; CHECK64ZFBFMIN-NEXT: and a0, a0, a1
1727 ; CHECK64ZFBFMIN-NEXT: slli a0, a0, 32
1728 ; CHECK64ZFBFMIN-NEXT: srli a0, a0, 32
1729 ; CHECK64ZFBFMIN-NEXT: ret
1730 ;
1731 ; RV64ID-LABEL: fcvt_wu_bf16_sat_zext:
1732 ; RV64ID: # %bb.0: # %start
1733 ; RV64ID-NEXT: fmv.x.w a0, fa0
1734 ; RV64ID-NEXT: slli a0, a0, 48
1735 ; RV64ID-NEXT: srli a0, a0, 48
1736 ; RV64ID-NEXT: slli a0, a0, 16
1737 ; RV64ID-NEXT: fmv.w.x fa5, a0
1738 ; RV64ID-NEXT: fcvt.wu.s a0, fa5, rtz
1739 ; RV64ID-NEXT: feq.s a1, fa5, fa5
1740 ; RV64ID-NEXT: seqz a1, a1
1741 ; RV64ID-NEXT: addi a1, a1, -1
1742 ; RV64ID-NEXT: and a0, a0, a1
1743 ; RV64ID-NEXT: slli a0, a0, 32
1744 ; RV64ID-NEXT: srli a0, a0, 32
1745 ; RV64ID-NEXT: ret
1746 start:
1747 %0 = tail call i32 @llvm.fptoui.sat.i32.bf16(bfloat %a)
1748 ret i32 %0
1749 }
1751 define signext i32 @fcvt_w_bf16_sat_sext(bfloat %a) nounwind {
1752 ; CHECK32ZFBFMIN-LABEL: fcvt_w_bf16_sat_sext:
1753 ; CHECK32ZFBFMIN: # %bb.0: # %start
1754 ; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1755 ; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
1756 ; CHECK32ZFBFMIN-NEXT: feq.s a1, fa5, fa5
1757 ; CHECK32ZFBFMIN-NEXT: seqz a1, a1
1758 ; CHECK32ZFBFMIN-NEXT: addi a1, a1, -1
1759 ; CHECK32ZFBFMIN-NEXT: and a0, a1, a0
1760 ; CHECK32ZFBFMIN-NEXT: ret
1761 ;
1762 ; RV32ID-LABEL: fcvt_w_bf16_sat_sext:
1763 ; RV32ID: # %bb.0: # %start
1764 ; RV32ID-NEXT: fmv.x.w a0, fa0
1765 ; RV32ID-NEXT: slli a0, a0, 16
1766 ; RV32ID-NEXT: fmv.w.x fa5, a0
1767 ; RV32ID-NEXT: fcvt.w.s a0, fa5, rtz
1768 ; RV32ID-NEXT: feq.s a1, fa5, fa5
1769 ; RV32ID-NEXT: seqz a1, a1
1770 ; RV32ID-NEXT: addi a1, a1, -1
1771 ; RV32ID-NEXT: and a0, a1, a0
1772 ; RV32ID-NEXT: ret
1773 ;
1774 ; CHECK64ZFBFMIN-LABEL: fcvt_w_bf16_sat_sext:
1775 ; CHECK64ZFBFMIN: # %bb.0: # %start
1776 ; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
1777 ; CHECK64ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
1778 ; CHECK64ZFBFMIN-NEXT: feq.s a1, fa5, fa5
1779 ; CHECK64ZFBFMIN-NEXT: seqz a1, a1
1780 ; CHECK64ZFBFMIN-NEXT: addi a1, a1, -1
1781 ; CHECK64ZFBFMIN-NEXT: and a0, a1, a0
1782 ; CHECK64ZFBFMIN-NEXT: ret
1783 ;
1784 ; RV64ID-LABEL: fcvt_w_bf16_sat_sext:
1785 ; RV64ID: # %bb.0: # %start
1786 ; RV64ID-NEXT: fmv.x.w a0, fa0
1787 ; RV64ID-NEXT: slli a0, a0, 48
1788 ; RV64ID-NEXT: srli a0, a0, 48
1789 ; RV64ID-NEXT: slli a0, a0, 16
1790 ; RV64ID-NEXT: fmv.w.x fa5, a0
1791 ; RV64ID-NEXT: fcvt.w.s a0, fa5, rtz
1792 ; RV64ID-NEXT: feq.s a1, fa5, fa5
1793 ; RV64ID-NEXT: seqz a1, a1
1794 ; RV64ID-NEXT: addi a1, a1, -1
1795 ; RV64ID-NEXT: and a0, a1, a0
1796 ; RV64ID-NEXT: ret
1797 start:
1798 %0 = tail call i32 @llvm.fptosi.sat.i32.bf16(bfloat %a)
1799 ret i32 %0
1800 }