| blob | fb4735240904682e103ac3309788a9d3b8894f97 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVE64X,RV32,RV32I
3 ; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-ZVE64X,RV64,RV64I
4 ; RUN: llc -mtriple=riscv32 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV32,RV32F
5 ; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+f -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-F,RV64,RV64F
6 ; RUN: llc -mtriple=riscv32 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV32,RV32D
7 ; RUN: llc -mtriple=riscv64 -mattr=+v,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-D,RV64,RV64D
8 ; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
9 ; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
11 define <vscale x 1 x i8> @cttz_nxv1i8(<vscale x 1 x i8> %va) {
12 ; CHECK-ZVE64X-LABEL: cttz_nxv1i8:
13 ; CHECK-ZVE64X: # %bb.0:
14 ; CHECK-ZVE64X-NEXT: li a0, 1
15 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
16 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
17 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
18 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
19 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
20 ; CHECK-ZVE64X-NEXT: li a0, 85
21 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
22 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
23 ; CHECK-ZVE64X-NEXT: li a0, 51
24 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
25 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
26 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
27 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
28 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
29 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
30 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
31 ; CHECK-ZVE64X-NEXT: ret
32 ;
33 ; CHECK-F-LABEL: cttz_nxv1i8:
34 ; CHECK-F: # %bb.0:
35 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
36 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
37 ; CHECK-F-NEXT: vand.vv v9, v8, v9
38 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
39 ; CHECK-F-NEXT: vzext.vf2 v10, v9
40 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v10
41 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 23
42 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
43 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
44 ; CHECK-F-NEXT: li a0, 127
45 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
46 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
47 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
48 ; CHECK-F-NEXT: ret
49 ;
50 ; CHECK-D-LABEL: cttz_nxv1i8:
51 ; CHECK-D: # %bb.0:
52 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
53 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
54 ; CHECK-D-NEXT: vand.vv v9, v8, v9
55 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
56 ; CHECK-D-NEXT: vzext.vf2 v10, v9
57 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v10
58 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 23
59 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
60 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
61 ; CHECK-D-NEXT: li a0, 127
62 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
63 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
64 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
65 ; CHECK-D-NEXT: ret
66 ;
67 ; CHECK-ZVBB-LABEL: cttz_nxv1i8:
68 ; CHECK-ZVBB: # %bb.0:
69 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
70 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
71 ; CHECK-ZVBB-NEXT: ret
72 %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 false)
73 ret <vscale x 1 x i8> %a
74 }
75 declare <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8>, i1)
77 define <vscale x 2 x i8> @cttz_nxv2i8(<vscale x 2 x i8> %va) {
78 ; CHECK-ZVE64X-LABEL: cttz_nxv2i8:
79 ; CHECK-ZVE64X: # %bb.0:
80 ; CHECK-ZVE64X-NEXT: li a0, 1
81 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
82 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
83 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
84 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
85 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
86 ; CHECK-ZVE64X-NEXT: li a0, 85
87 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
88 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
89 ; CHECK-ZVE64X-NEXT: li a0, 51
90 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
91 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
92 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
93 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
94 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
95 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
96 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
97 ; CHECK-ZVE64X-NEXT: ret
98 ;
99 ; CHECK-F-LABEL: cttz_nxv2i8:
100 ; CHECK-F: # %bb.0:
101 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
102 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
103 ; CHECK-F-NEXT: vand.vv v9, v8, v9
104 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
105 ; CHECK-F-NEXT: vzext.vf2 v10, v9
106 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v10
107 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 23
108 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
109 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
110 ; CHECK-F-NEXT: li a0, 127
111 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
112 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
113 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
114 ; CHECK-F-NEXT: ret
115 ;
116 ; CHECK-D-LABEL: cttz_nxv2i8:
117 ; CHECK-D: # %bb.0:
118 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
119 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
120 ; CHECK-D-NEXT: vand.vv v9, v8, v9
121 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
122 ; CHECK-D-NEXT: vzext.vf2 v10, v9
123 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v10
124 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 23
125 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
126 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
127 ; CHECK-D-NEXT: li a0, 127
128 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
129 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
130 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
131 ; CHECK-D-NEXT: ret
132 ;
133 ; CHECK-ZVBB-LABEL: cttz_nxv2i8:
134 ; CHECK-ZVBB: # %bb.0:
135 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
136 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
137 ; CHECK-ZVBB-NEXT: ret
138 %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 false)
139 ret <vscale x 2 x i8> %a
140 }
141 declare <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8>, i1)
143 define <vscale x 4 x i8> @cttz_nxv4i8(<vscale x 4 x i8> %va) {
144 ; CHECK-ZVE64X-LABEL: cttz_nxv4i8:
145 ; CHECK-ZVE64X: # %bb.0:
146 ; CHECK-ZVE64X-NEXT: li a0, 1
147 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
148 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
149 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
150 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
151 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
152 ; CHECK-ZVE64X-NEXT: li a0, 85
153 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
154 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
155 ; CHECK-ZVE64X-NEXT: li a0, 51
156 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
157 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
158 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
159 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
160 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
161 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
162 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
163 ; CHECK-ZVE64X-NEXT: ret
164 ;
165 ; CHECK-F-LABEL: cttz_nxv4i8:
166 ; CHECK-F: # %bb.0:
167 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
168 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
169 ; CHECK-F-NEXT: vand.vv v9, v8, v9
170 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
171 ; CHECK-F-NEXT: vzext.vf2 v10, v9
172 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
173 ; CHECK-F-NEXT: vnsrl.wi v9, v12, 23
174 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
175 ; CHECK-F-NEXT: vnsrl.wi v9, v9, 0
176 ; CHECK-F-NEXT: li a0, 127
177 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
178 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
179 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
180 ; CHECK-F-NEXT: ret
181 ;
182 ; CHECK-D-LABEL: cttz_nxv4i8:
183 ; CHECK-D: # %bb.0:
184 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
185 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
186 ; CHECK-D-NEXT: vand.vv v9, v8, v9
187 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m1, ta, ma
188 ; CHECK-D-NEXT: vzext.vf2 v10, v9
189 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
190 ; CHECK-D-NEXT: vnsrl.wi v9, v12, 23
191 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
192 ; CHECK-D-NEXT: vnsrl.wi v9, v9, 0
193 ; CHECK-D-NEXT: li a0, 127
194 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
195 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
196 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
197 ; CHECK-D-NEXT: ret
198 ;
199 ; CHECK-ZVBB-LABEL: cttz_nxv4i8:
200 ; CHECK-ZVBB: # %bb.0:
201 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
202 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
203 ; CHECK-ZVBB-NEXT: ret
204 %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 false)
205 ret <vscale x 4 x i8> %a
206 }
207 declare <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8>, i1)
209 define <vscale x 8 x i8> @cttz_nxv8i8(<vscale x 8 x i8> %va) {
210 ; CHECK-ZVE64X-LABEL: cttz_nxv8i8:
211 ; CHECK-ZVE64X: # %bb.0:
212 ; CHECK-ZVE64X-NEXT: li a0, 1
213 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m1, ta, ma
214 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
215 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
216 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
217 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
218 ; CHECK-ZVE64X-NEXT: li a0, 85
219 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
220 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
221 ; CHECK-ZVE64X-NEXT: li a0, 51
222 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
223 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
224 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
225 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
226 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
227 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
228 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
229 ; CHECK-ZVE64X-NEXT: ret
230 ;
231 ; CHECK-F-LABEL: cttz_nxv8i8:
232 ; CHECK-F: # %bb.0:
233 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m1, ta, ma
234 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
235 ; CHECK-F-NEXT: vand.vv v9, v8, v9
236 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
237 ; CHECK-F-NEXT: vzext.vf2 v10, v9
238 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
239 ; CHECK-F-NEXT: vnsrl.wi v10, v12, 23
240 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
241 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 0
242 ; CHECK-F-NEXT: li a0, 127
243 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
244 ; CHECK-F-NEXT: vsub.vx v8, v9, a0
245 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
246 ; CHECK-F-NEXT: ret
247 ;
248 ; CHECK-D-LABEL: cttz_nxv8i8:
249 ; CHECK-D: # %bb.0:
250 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m1, ta, ma
251 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
252 ; CHECK-D-NEXT: vand.vv v9, v8, v9
253 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m2, ta, ma
254 ; CHECK-D-NEXT: vzext.vf2 v10, v9
255 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
256 ; CHECK-D-NEXT: vnsrl.wi v10, v12, 23
257 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m1, ta, ma
258 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 0
259 ; CHECK-D-NEXT: li a0, 127
260 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
261 ; CHECK-D-NEXT: vsub.vx v8, v9, a0
262 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
263 ; CHECK-D-NEXT: ret
264 ;
265 ; CHECK-ZVBB-LABEL: cttz_nxv8i8:
266 ; CHECK-ZVBB: # %bb.0:
267 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
268 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
269 ; CHECK-ZVBB-NEXT: ret
270 %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 false)
271 ret <vscale x 8 x i8> %a
272 }
273 declare <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8>, i1)
275 define <vscale x 16 x i8> @cttz_nxv16i8(<vscale x 16 x i8> %va) {
276 ; CHECK-ZVE64X-LABEL: cttz_nxv16i8:
277 ; CHECK-ZVE64X: # %bb.0:
278 ; CHECK-ZVE64X-NEXT: li a0, 1
279 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m2, ta, ma
280 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
281 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
282 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
283 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
284 ; CHECK-ZVE64X-NEXT: li a0, 85
285 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
286 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
287 ; CHECK-ZVE64X-NEXT: li a0, 51
288 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
289 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
290 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
291 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
292 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
293 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
294 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
295 ; CHECK-ZVE64X-NEXT: ret
296 ;
297 ; CHECK-F-LABEL: cttz_nxv16i8:
298 ; CHECK-F: # %bb.0:
299 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m2, ta, ma
300 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
301 ; CHECK-F-NEXT: vand.vv v10, v8, v10
302 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m4, ta, ma
303 ; CHECK-F-NEXT: vzext.vf2 v12, v10
304 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v12
305 ; CHECK-F-NEXT: vnsrl.wi v12, v16, 23
306 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m2, ta, ma
307 ; CHECK-F-NEXT: vnsrl.wi v10, v12, 0
308 ; CHECK-F-NEXT: li a0, 127
309 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
310 ; CHECK-F-NEXT: vsub.vx v8, v10, a0
311 ; CHECK-F-NEXT: vmerge.vim v8, v8, 8, v0
312 ; CHECK-F-NEXT: ret
313 ;
314 ; CHECK-D-LABEL: cttz_nxv16i8:
315 ; CHECK-D: # %bb.0:
316 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m2, ta, ma
317 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
318 ; CHECK-D-NEXT: vand.vv v10, v8, v10
319 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m4, ta, ma
320 ; CHECK-D-NEXT: vzext.vf2 v12, v10
321 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
322 ; CHECK-D-NEXT: vnsrl.wi v12, v16, 23
323 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m2, ta, ma
324 ; CHECK-D-NEXT: vnsrl.wi v10, v12, 0
325 ; CHECK-D-NEXT: li a0, 127
326 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
327 ; CHECK-D-NEXT: vsub.vx v8, v10, a0
328 ; CHECK-D-NEXT: vmerge.vim v8, v8, 8, v0
329 ; CHECK-D-NEXT: ret
330 ;
331 ; CHECK-ZVBB-LABEL: cttz_nxv16i8:
332 ; CHECK-ZVBB: # %bb.0:
333 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
334 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
335 ; CHECK-ZVBB-NEXT: ret
336 %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 false)
337 ret <vscale x 16 x i8> %a
338 }
339 declare <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8>, i1)
341 define <vscale x 32 x i8> @cttz_nxv32i8(<vscale x 32 x i8> %va) {
342 ; CHECK-LABEL: cttz_nxv32i8:
343 ; CHECK: # %bb.0:
344 ; CHECK-NEXT: li a0, 1
345 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
346 ; CHECK-NEXT: vsub.vx v12, v8, a0
347 ; CHECK-NEXT: vnot.v v8, v8
348 ; CHECK-NEXT: vand.vv v8, v8, v12
349 ; CHECK-NEXT: vsrl.vi v12, v8, 1
350 ; CHECK-NEXT: li a0, 85
351 ; CHECK-NEXT: vand.vx v12, v12, a0
352 ; CHECK-NEXT: vsub.vv v8, v8, v12
353 ; CHECK-NEXT: li a0, 51
354 ; CHECK-NEXT: vand.vx v12, v8, a0
355 ; CHECK-NEXT: vsrl.vi v8, v8, 2
356 ; CHECK-NEXT: vand.vx v8, v8, a0
357 ; CHECK-NEXT: vadd.vv v8, v12, v8
358 ; CHECK-NEXT: vsrl.vi v12, v8, 4
359 ; CHECK-NEXT: vadd.vv v8, v8, v12
360 ; CHECK-NEXT: vand.vi v8, v8, 15
361 ; CHECK-NEXT: ret
362 ;
363 ; CHECK-ZVBB-LABEL: cttz_nxv32i8:
364 ; CHECK-ZVBB: # %bb.0:
365 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
366 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
367 ; CHECK-ZVBB-NEXT: ret
368 %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 false)
369 ret <vscale x 32 x i8> %a
370 }
371 declare <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8>, i1)
373 define <vscale x 64 x i8> @cttz_nxv64i8(<vscale x 64 x i8> %va) {
374 ; CHECK-LABEL: cttz_nxv64i8:
375 ; CHECK: # %bb.0:
376 ; CHECK-NEXT: li a0, 1
377 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
378 ; CHECK-NEXT: vsub.vx v16, v8, a0
379 ; CHECK-NEXT: vnot.v v8, v8
380 ; CHECK-NEXT: vand.vv v8, v8, v16
381 ; CHECK-NEXT: vsrl.vi v16, v8, 1
382 ; CHECK-NEXT: li a0, 85
383 ; CHECK-NEXT: vand.vx v16, v16, a0
384 ; CHECK-NEXT: vsub.vv v8, v8, v16
385 ; CHECK-NEXT: li a0, 51
386 ; CHECK-NEXT: vand.vx v16, v8, a0
387 ; CHECK-NEXT: vsrl.vi v8, v8, 2
388 ; CHECK-NEXT: vand.vx v8, v8, a0
389 ; CHECK-NEXT: vadd.vv v8, v16, v8
390 ; CHECK-NEXT: vsrl.vi v16, v8, 4
391 ; CHECK-NEXT: vadd.vv v8, v8, v16
392 ; CHECK-NEXT: vand.vi v8, v8, 15
393 ; CHECK-NEXT: ret
394 ;
395 ; CHECK-ZVBB-LABEL: cttz_nxv64i8:
396 ; CHECK-ZVBB: # %bb.0:
397 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
398 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
399 ; CHECK-ZVBB-NEXT: ret
400 %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 false)
401 ret <vscale x 64 x i8> %a
402 }
403 declare <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8>, i1)
405 define <vscale x 1 x i16> @cttz_nxv1i16(<vscale x 1 x i16> %va) {
406 ; CHECK-ZVE64X-LABEL: cttz_nxv1i16:
407 ; CHECK-ZVE64X: # %bb.0:
408 ; CHECK-ZVE64X-NEXT: li a0, 1
409 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
410 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
411 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
412 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
413 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
414 ; CHECK-ZVE64X-NEXT: lui a0, 5
415 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
416 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
417 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
418 ; CHECK-ZVE64X-NEXT: lui a0, 3
419 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
420 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
421 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
422 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
423 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
424 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
425 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
426 ; CHECK-ZVE64X-NEXT: lui a0, 1
427 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
428 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
429 ; CHECK-ZVE64X-NEXT: li a0, 257
430 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
431 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
432 ; CHECK-ZVE64X-NEXT: ret
433 ;
434 ; CHECK-F-LABEL: cttz_nxv1i16:
435 ; CHECK-F: # %bb.0:
436 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
437 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
438 ; CHECK-F-NEXT: vand.vv v9, v8, v9
439 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
440 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 23
441 ; CHECK-F-NEXT: li a0, 127
442 ; CHECK-F-NEXT: vsub.vx v9, v9, a0
443 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
444 ; CHECK-F-NEXT: li a0, 16
445 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a0, v0
446 ; CHECK-F-NEXT: ret
447 ;
448 ; CHECK-D-LABEL: cttz_nxv1i16:
449 ; CHECK-D: # %bb.0:
450 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
451 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
452 ; CHECK-D-NEXT: vand.vv v9, v8, v9
453 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
454 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 23
455 ; CHECK-D-NEXT: li a0, 127
456 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
457 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
458 ; CHECK-D-NEXT: li a0, 16
459 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
460 ; CHECK-D-NEXT: ret
461 ;
462 ; CHECK-ZVBB-LABEL: cttz_nxv1i16:
463 ; CHECK-ZVBB: # %bb.0:
464 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
465 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
466 ; CHECK-ZVBB-NEXT: ret
467 %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 false)
468 ret <vscale x 1 x i16> %a
469 }
470 declare <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16>, i1)
472 define <vscale x 2 x i16> @cttz_nxv2i16(<vscale x 2 x i16> %va) {
473 ; CHECK-ZVE64X-LABEL: cttz_nxv2i16:
474 ; CHECK-ZVE64X: # %bb.0:
475 ; CHECK-ZVE64X-NEXT: li a0, 1
476 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
477 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
478 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
479 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
480 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
481 ; CHECK-ZVE64X-NEXT: lui a0, 5
482 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
483 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
484 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
485 ; CHECK-ZVE64X-NEXT: lui a0, 3
486 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
487 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
488 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
489 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
490 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
491 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
492 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
493 ; CHECK-ZVE64X-NEXT: lui a0, 1
494 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
495 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
496 ; CHECK-ZVE64X-NEXT: li a0, 257
497 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
498 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
499 ; CHECK-ZVE64X-NEXT: ret
500 ;
501 ; CHECK-F-LABEL: cttz_nxv2i16:
502 ; CHECK-F: # %bb.0:
503 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
504 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
505 ; CHECK-F-NEXT: vand.vv v9, v8, v9
506 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
507 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 23
508 ; CHECK-F-NEXT: li a0, 127
509 ; CHECK-F-NEXT: vsub.vx v9, v9, a0
510 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
511 ; CHECK-F-NEXT: li a0, 16
512 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a0, v0
513 ; CHECK-F-NEXT: ret
514 ;
515 ; CHECK-D-LABEL: cttz_nxv2i16:
516 ; CHECK-D: # %bb.0:
517 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
518 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
519 ; CHECK-D-NEXT: vand.vv v9, v8, v9
520 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
521 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 23
522 ; CHECK-D-NEXT: li a0, 127
523 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
524 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
525 ; CHECK-D-NEXT: li a0, 16
526 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
527 ; CHECK-D-NEXT: ret
528 ;
529 ; CHECK-ZVBB-LABEL: cttz_nxv2i16:
530 ; CHECK-ZVBB: # %bb.0:
531 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
532 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
533 ; CHECK-ZVBB-NEXT: ret
534 %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 false)
535 ret <vscale x 2 x i16> %a
536 }
537 declare <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16>, i1)
539 define <vscale x 4 x i16> @cttz_nxv4i16(<vscale x 4 x i16> %va) {
540 ; CHECK-ZVE64X-LABEL: cttz_nxv4i16:
541 ; CHECK-ZVE64X: # %bb.0:
542 ; CHECK-ZVE64X-NEXT: li a0, 1
543 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m1, ta, ma
544 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
545 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
546 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
547 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
548 ; CHECK-ZVE64X-NEXT: lui a0, 5
549 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
550 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
551 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
552 ; CHECK-ZVE64X-NEXT: lui a0, 3
553 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
554 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
555 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
556 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
557 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
558 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
559 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
560 ; CHECK-ZVE64X-NEXT: lui a0, 1
561 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
562 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
563 ; CHECK-ZVE64X-NEXT: li a0, 257
564 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
565 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
566 ; CHECK-ZVE64X-NEXT: ret
567 ;
568 ; CHECK-F-LABEL: cttz_nxv4i16:
569 ; CHECK-F: # %bb.0:
570 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m1, ta, ma
571 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
572 ; CHECK-F-NEXT: vand.vv v9, v8, v9
573 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
574 ; CHECK-F-NEXT: vnsrl.wi v9, v10, 23
575 ; CHECK-F-NEXT: li a0, 127
576 ; CHECK-F-NEXT: vsub.vx v9, v9, a0
577 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
578 ; CHECK-F-NEXT: li a0, 16
579 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a0, v0
580 ; CHECK-F-NEXT: ret
581 ;
582 ; CHECK-D-LABEL: cttz_nxv4i16:
583 ; CHECK-D: # %bb.0:
584 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m1, ta, ma
585 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
586 ; CHECK-D-NEXT: vand.vv v9, v8, v9
587 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
588 ; CHECK-D-NEXT: vnsrl.wi v9, v10, 23
589 ; CHECK-D-NEXT: li a0, 127
590 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
591 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
592 ; CHECK-D-NEXT: li a0, 16
593 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
594 ; CHECK-D-NEXT: ret
595 ;
596 ; CHECK-ZVBB-LABEL: cttz_nxv4i16:
597 ; CHECK-ZVBB: # %bb.0:
598 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
599 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
600 ; CHECK-ZVBB-NEXT: ret
601 %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 false)
602 ret <vscale x 4 x i16> %a
603 }
604 declare <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16>, i1)
606 define <vscale x 8 x i16> @cttz_nxv8i16(<vscale x 8 x i16> %va) {
607 ; CHECK-ZVE64X-LABEL: cttz_nxv8i16:
608 ; CHECK-ZVE64X: # %bb.0:
609 ; CHECK-ZVE64X-NEXT: li a0, 1
610 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m2, ta, ma
611 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
612 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
613 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
614 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
615 ; CHECK-ZVE64X-NEXT: lui a0, 5
616 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
617 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
618 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
619 ; CHECK-ZVE64X-NEXT: lui a0, 3
620 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
621 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
622 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
623 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
624 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
625 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
626 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
627 ; CHECK-ZVE64X-NEXT: lui a0, 1
628 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
629 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
630 ; CHECK-ZVE64X-NEXT: li a0, 257
631 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
632 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
633 ; CHECK-ZVE64X-NEXT: ret
634 ;
635 ; CHECK-F-LABEL: cttz_nxv8i16:
636 ; CHECK-F: # %bb.0:
637 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m2, ta, ma
638 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
639 ; CHECK-F-NEXT: vand.vv v10, v8, v10
640 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
641 ; CHECK-F-NEXT: vnsrl.wi v10, v12, 23
642 ; CHECK-F-NEXT: li a0, 127
643 ; CHECK-F-NEXT: vsub.vx v10, v10, a0
644 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
645 ; CHECK-F-NEXT: li a0, 16
646 ; CHECK-F-NEXT: vmerge.vxm v8, v10, a0, v0
647 ; CHECK-F-NEXT: ret
648 ;
649 ; CHECK-D-LABEL: cttz_nxv8i16:
650 ; CHECK-D: # %bb.0:
651 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m2, ta, ma
652 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
653 ; CHECK-D-NEXT: vand.vv v10, v8, v10
654 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
655 ; CHECK-D-NEXT: vnsrl.wi v10, v12, 23
656 ; CHECK-D-NEXT: li a0, 127
657 ; CHECK-D-NEXT: vsub.vx v10, v10, a0
658 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
659 ; CHECK-D-NEXT: li a0, 16
660 ; CHECK-D-NEXT: vmerge.vxm v8, v10, a0, v0
661 ; CHECK-D-NEXT: ret
662 ;
663 ; CHECK-ZVBB-LABEL: cttz_nxv8i16:
664 ; CHECK-ZVBB: # %bb.0:
665 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
666 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
667 ; CHECK-ZVBB-NEXT: ret
668 %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 false)
669 ret <vscale x 8 x i16> %a
670 }
671 declare <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16>, i1)
673 define <vscale x 16 x i16> @cttz_nxv16i16(<vscale x 16 x i16> %va) {
674 ; CHECK-ZVE64X-LABEL: cttz_nxv16i16:
675 ; CHECK-ZVE64X: # %bb.0:
676 ; CHECK-ZVE64X-NEXT: li a0, 1
677 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m4, ta, ma
678 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
679 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
680 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
681 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
682 ; CHECK-ZVE64X-NEXT: lui a0, 5
683 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
684 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
685 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
686 ; CHECK-ZVE64X-NEXT: lui a0, 3
687 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
688 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
689 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
690 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
691 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
692 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
693 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
694 ; CHECK-ZVE64X-NEXT: lui a0, 1
695 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
696 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
697 ; CHECK-ZVE64X-NEXT: li a0, 257
698 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
699 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
700 ; CHECK-ZVE64X-NEXT: ret
701 ;
702 ; CHECK-F-LABEL: cttz_nxv16i16:
703 ; CHECK-F: # %bb.0:
704 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m4, ta, ma
705 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
706 ; CHECK-F-NEXT: vand.vv v12, v8, v12
707 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v12
708 ; CHECK-F-NEXT: vnsrl.wi v12, v16, 23
709 ; CHECK-F-NEXT: li a0, 127
710 ; CHECK-F-NEXT: vsub.vx v12, v12, a0
711 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
712 ; CHECK-F-NEXT: li a0, 16
713 ; CHECK-F-NEXT: vmerge.vxm v8, v12, a0, v0
714 ; CHECK-F-NEXT: ret
715 ;
716 ; CHECK-D-LABEL: cttz_nxv16i16:
717 ; CHECK-D: # %bb.0:
718 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m4, ta, ma
719 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
720 ; CHECK-D-NEXT: vand.vv v12, v8, v12
721 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
722 ; CHECK-D-NEXT: vnsrl.wi v12, v16, 23
723 ; CHECK-D-NEXT: li a0, 127
724 ; CHECK-D-NEXT: vsub.vx v12, v12, a0
725 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
726 ; CHECK-D-NEXT: li a0, 16
727 ; CHECK-D-NEXT: vmerge.vxm v8, v12, a0, v0
728 ; CHECK-D-NEXT: ret
729 ;
730 ; CHECK-ZVBB-LABEL: cttz_nxv16i16:
731 ; CHECK-ZVBB: # %bb.0:
732 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
733 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
734 ; CHECK-ZVBB-NEXT: ret
735 %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 false)
736 ret <vscale x 16 x i16> %a
737 }
738 declare <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16>, i1)
740 define <vscale x 32 x i16> @cttz_nxv32i16(<vscale x 32 x i16> %va) {
741 ; CHECK-LABEL: cttz_nxv32i16:
742 ; CHECK: # %bb.0:
743 ; CHECK-NEXT: li a0, 1
744 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
745 ; CHECK-NEXT: vsub.vx v16, v8, a0
746 ; CHECK-NEXT: vnot.v v8, v8
747 ; CHECK-NEXT: vand.vv v8, v8, v16
748 ; CHECK-NEXT: vsrl.vi v16, v8, 1
749 ; CHECK-NEXT: lui a0, 5
750 ; CHECK-NEXT: addi a0, a0, 1365
751 ; CHECK-NEXT: vand.vx v16, v16, a0
752 ; CHECK-NEXT: vsub.vv v8, v8, v16
753 ; CHECK-NEXT: lui a0, 3
754 ; CHECK-NEXT: addi a0, a0, 819
755 ; CHECK-NEXT: vand.vx v16, v8, a0
756 ; CHECK-NEXT: vsrl.vi v8, v8, 2
757 ; CHECK-NEXT: vand.vx v8, v8, a0
758 ; CHECK-NEXT: vadd.vv v8, v16, v8
759 ; CHECK-NEXT: vsrl.vi v16, v8, 4
760 ; CHECK-NEXT: vadd.vv v8, v8, v16
761 ; CHECK-NEXT: lui a0, 1
762 ; CHECK-NEXT: addi a0, a0, -241
763 ; CHECK-NEXT: vand.vx v8, v8, a0
764 ; CHECK-NEXT: li a0, 257
765 ; CHECK-NEXT: vmul.vx v8, v8, a0
766 ; CHECK-NEXT: vsrl.vi v8, v8, 8
767 ; CHECK-NEXT: ret
768 ;
769 ; CHECK-ZVBB-LABEL: cttz_nxv32i16:
770 ; CHECK-ZVBB: # %bb.0:
771 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
772 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
773 ; CHECK-ZVBB-NEXT: ret
774 %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 false)
775 ret <vscale x 32 x i16> %a
776 }
777 declare <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16>, i1)
779 define <vscale x 1 x i32> @cttz_nxv1i32(<vscale x 1 x i32> %va) {
780 ; CHECK-ZVE64X-LABEL: cttz_nxv1i32:
781 ; CHECK-ZVE64X: # %bb.0:
782 ; CHECK-ZVE64X-NEXT: li a0, 1
783 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
784 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
785 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
786 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
787 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
788 ; CHECK-ZVE64X-NEXT: lui a0, 349525
789 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
790 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
791 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
792 ; CHECK-ZVE64X-NEXT: lui a0, 209715
793 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
794 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
795 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
796 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
797 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
798 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
799 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
800 ; CHECK-ZVE64X-NEXT: lui a0, 61681
801 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
802 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
803 ; CHECK-ZVE64X-NEXT: lui a0, 4112
804 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
805 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
806 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
807 ; CHECK-ZVE64X-NEXT: ret
808 ;
809 ; CHECK-F-LABEL: cttz_nxv1i32:
810 ; CHECK-F: # %bb.0:
811 ; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
812 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
813 ; CHECK-F-NEXT: vand.vv v9, v8, v9
814 ; CHECK-F-NEXT: fsrmi a0, 1
815 ; CHECK-F-NEXT: vfcvt.f.xu.v v9, v9
816 ; CHECK-F-NEXT: vsrl.vi v9, v9, 23
817 ; CHECK-F-NEXT: li a1, 127
818 ; CHECK-F-NEXT: vsub.vx v9, v9, a1
819 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
820 ; CHECK-F-NEXT: li a1, 32
821 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a1, v0
822 ; CHECK-F-NEXT: fsrm a0
823 ; CHECK-F-NEXT: ret
824 ;
825 ; CHECK-D-LABEL: cttz_nxv1i32:
826 ; CHECK-D: # %bb.0:
827 ; CHECK-D-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
828 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
829 ; CHECK-D-NEXT: vand.vv v9, v8, v9
830 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
831 ; CHECK-D-NEXT: li a0, 52
832 ; CHECK-D-NEXT: vnsrl.wx v9, v10, a0
833 ; CHECK-D-NEXT: li a0, 1023
834 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
835 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
836 ; CHECK-D-NEXT: li a0, 32
837 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
838 ; CHECK-D-NEXT: ret
839 ;
840 ; CHECK-ZVBB-LABEL: cttz_nxv1i32:
841 ; CHECK-ZVBB: # %bb.0:
842 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
843 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
844 ; CHECK-ZVBB-NEXT: ret
845 %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 false)
846 ret <vscale x 1 x i32> %a
847 }
848 declare <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32>, i1)
850 define <vscale x 2 x i32> @cttz_nxv2i32(<vscale x 2 x i32> %va) {
851 ; CHECK-ZVE64X-LABEL: cttz_nxv2i32:
852 ; CHECK-ZVE64X: # %bb.0:
853 ; CHECK-ZVE64X-NEXT: li a0, 1
854 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m1, ta, ma
855 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
856 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
857 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
858 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
859 ; CHECK-ZVE64X-NEXT: lui a0, 349525
860 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
861 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
862 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
863 ; CHECK-ZVE64X-NEXT: lui a0, 209715
864 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
865 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
866 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
867 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
868 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
869 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
870 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
871 ; CHECK-ZVE64X-NEXT: lui a0, 61681
872 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
873 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
874 ; CHECK-ZVE64X-NEXT: lui a0, 4112
875 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
876 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
877 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
878 ; CHECK-ZVE64X-NEXT: ret
879 ;
880 ; CHECK-F-LABEL: cttz_nxv2i32:
881 ; CHECK-F: # %bb.0:
882 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
883 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
884 ; CHECK-F-NEXT: vand.vv v9, v8, v9
885 ; CHECK-F-NEXT: fsrmi a0, 1
886 ; CHECK-F-NEXT: vfcvt.f.xu.v v9, v9
887 ; CHECK-F-NEXT: vsrl.vi v9, v9, 23
888 ; CHECK-F-NEXT: li a1, 127
889 ; CHECK-F-NEXT: vsub.vx v9, v9, a1
890 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
891 ; CHECK-F-NEXT: li a1, 32
892 ; CHECK-F-NEXT: vmerge.vxm v8, v9, a1, v0
893 ; CHECK-F-NEXT: fsrm a0
894 ; CHECK-F-NEXT: ret
895 ;
896 ; CHECK-D-LABEL: cttz_nxv2i32:
897 ; CHECK-D: # %bb.0:
898 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m1, ta, ma
899 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
900 ; CHECK-D-NEXT: vand.vv v9, v8, v9
901 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
902 ; CHECK-D-NEXT: li a0, 52
903 ; CHECK-D-NEXT: vnsrl.wx v9, v10, a0
904 ; CHECK-D-NEXT: li a0, 1023
905 ; CHECK-D-NEXT: vsub.vx v9, v9, a0
906 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
907 ; CHECK-D-NEXT: li a0, 32
908 ; CHECK-D-NEXT: vmerge.vxm v8, v9, a0, v0
909 ; CHECK-D-NEXT: ret
910 ;
911 ; CHECK-ZVBB-LABEL: cttz_nxv2i32:
912 ; CHECK-ZVBB: # %bb.0:
913 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
914 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
915 ; CHECK-ZVBB-NEXT: ret
916 %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 false)
917 ret <vscale x 2 x i32> %a
918 }
919 declare <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32>, i1)
921 define <vscale x 4 x i32> @cttz_nxv4i32(<vscale x 4 x i32> %va) {
922 ; CHECK-ZVE64X-LABEL: cttz_nxv4i32:
923 ; CHECK-ZVE64X: # %bb.0:
924 ; CHECK-ZVE64X-NEXT: li a0, 1
925 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m2, ta, ma
926 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
927 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
928 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
929 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
930 ; CHECK-ZVE64X-NEXT: lui a0, 349525
931 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
932 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
933 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
934 ; CHECK-ZVE64X-NEXT: lui a0, 209715
935 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
936 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
937 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
938 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
939 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
940 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
941 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
942 ; CHECK-ZVE64X-NEXT: lui a0, 61681
943 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
944 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
945 ; CHECK-ZVE64X-NEXT: lui a0, 4112
946 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
947 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
948 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
949 ; CHECK-ZVE64X-NEXT: ret
950 ;
951 ; CHECK-F-LABEL: cttz_nxv4i32:
952 ; CHECK-F: # %bb.0:
953 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
954 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
955 ; CHECK-F-NEXT: vand.vv v10, v8, v10
956 ; CHECK-F-NEXT: fsrmi a0, 1
957 ; CHECK-F-NEXT: vfcvt.f.xu.v v10, v10
958 ; CHECK-F-NEXT: vsrl.vi v10, v10, 23
959 ; CHECK-F-NEXT: li a1, 127
960 ; CHECK-F-NEXT: vsub.vx v10, v10, a1
961 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
962 ; CHECK-F-NEXT: li a1, 32
963 ; CHECK-F-NEXT: vmerge.vxm v8, v10, a1, v0
964 ; CHECK-F-NEXT: fsrm a0
965 ; CHECK-F-NEXT: ret
966 ;
967 ; CHECK-D-LABEL: cttz_nxv4i32:
968 ; CHECK-D: # %bb.0:
969 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m2, ta, ma
970 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
971 ; CHECK-D-NEXT: vand.vv v10, v8, v10
972 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
973 ; CHECK-D-NEXT: li a0, 52
974 ; CHECK-D-NEXT: vnsrl.wx v10, v12, a0
975 ; CHECK-D-NEXT: li a0, 1023
976 ; CHECK-D-NEXT: vsub.vx v10, v10, a0
977 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
978 ; CHECK-D-NEXT: li a0, 32
979 ; CHECK-D-NEXT: vmerge.vxm v8, v10, a0, v0
980 ; CHECK-D-NEXT: ret
981 ;
982 ; CHECK-ZVBB-LABEL: cttz_nxv4i32:
983 ; CHECK-ZVBB: # %bb.0:
984 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
985 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
986 ; CHECK-ZVBB-NEXT: ret
987 %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 false)
988 ret <vscale x 4 x i32> %a
989 }
990 declare <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32>, i1)
992 define <vscale x 8 x i32> @cttz_nxv8i32(<vscale x 8 x i32> %va) {
993 ; CHECK-ZVE64X-LABEL: cttz_nxv8i32:
994 ; CHECK-ZVE64X: # %bb.0:
995 ; CHECK-ZVE64X-NEXT: li a0, 1
996 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m4, ta, ma
997 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
998 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
999 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
1000 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
1001 ; CHECK-ZVE64X-NEXT: lui a0, 349525
1002 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
1003 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
1004 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
1005 ; CHECK-ZVE64X-NEXT: lui a0, 209715
1006 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
1007 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
1008 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1009 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1010 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
1011 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
1012 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
1013 ; CHECK-ZVE64X-NEXT: lui a0, 61681
1014 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
1015 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1016 ; CHECK-ZVE64X-NEXT: lui a0, 4112
1017 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
1018 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
1019 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
1020 ; CHECK-ZVE64X-NEXT: ret
1021 ;
1022 ; CHECK-F-LABEL: cttz_nxv8i32:
1023 ; CHECK-F: # %bb.0:
1024 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
1025 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
1026 ; CHECK-F-NEXT: vand.vv v12, v8, v12
1027 ; CHECK-F-NEXT: fsrmi a0, 1
1028 ; CHECK-F-NEXT: vfcvt.f.xu.v v12, v12
1029 ; CHECK-F-NEXT: vsrl.vi v12, v12, 23
1030 ; CHECK-F-NEXT: li a1, 127
1031 ; CHECK-F-NEXT: vsub.vx v12, v12, a1
1032 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
1033 ; CHECK-F-NEXT: li a1, 32
1034 ; CHECK-F-NEXT: vmerge.vxm v8, v12, a1, v0
1035 ; CHECK-F-NEXT: fsrm a0
1036 ; CHECK-F-NEXT: ret
1037 ;
1038 ; CHECK-D-LABEL: cttz_nxv8i32:
1039 ; CHECK-D: # %bb.0:
1040 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m4, ta, ma
1041 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
1042 ; CHECK-D-NEXT: vand.vv v12, v8, v12
1043 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
1044 ; CHECK-D-NEXT: li a0, 52
1045 ; CHECK-D-NEXT: vnsrl.wx v12, v16, a0
1046 ; CHECK-D-NEXT: li a0, 1023
1047 ; CHECK-D-NEXT: vsub.vx v12, v12, a0
1048 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
1049 ; CHECK-D-NEXT: li a0, 32
1050 ; CHECK-D-NEXT: vmerge.vxm v8, v12, a0, v0
1051 ; CHECK-D-NEXT: ret
1052 ;
1053 ; CHECK-ZVBB-LABEL: cttz_nxv8i32:
1054 ; CHECK-ZVBB: # %bb.0:
1055 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
1056 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1057 ; CHECK-ZVBB-NEXT: ret
1058 %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 false)
1059 ret <vscale x 8 x i32> %a
1060 }
1061 declare <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32>, i1)
1063 define <vscale x 16 x i32> @cttz_nxv16i32(<vscale x 16 x i32> %va) {
1064 ; CHECK-ZVE64X-LABEL: cttz_nxv16i32:
1065 ; CHECK-ZVE64X: # %bb.0:
1066 ; CHECK-ZVE64X-NEXT: li a0, 1
1067 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1068 ; CHECK-ZVE64X-NEXT: vsub.vx v16, v8, a0
1069 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1070 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v16
1071 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
1072 ; CHECK-ZVE64X-NEXT: lui a0, 349525
1073 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
1074 ; CHECK-ZVE64X-NEXT: vand.vx v16, v16, a0
1075 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v16
1076 ; CHECK-ZVE64X-NEXT: lui a0, 209715
1077 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
1078 ; CHECK-ZVE64X-NEXT: vand.vx v16, v8, a0
1079 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1080 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1081 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v16, v8
1082 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 4
1083 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v16
1084 ; CHECK-ZVE64X-NEXT: lui a0, 61681
1085 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
1086 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1087 ; CHECK-ZVE64X-NEXT: lui a0, 4112
1088 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
1089 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
1090 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
1091 ; CHECK-ZVE64X-NEXT: ret
1092 ;
1093 ; CHECK-F-LABEL: cttz_nxv16i32:
1094 ; CHECK-F: # %bb.0:
1095 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1096 ; CHECK-F-NEXT: vrsub.vi v16, v8, 0
1097 ; CHECK-F-NEXT: vand.vv v16, v8, v16
1098 ; CHECK-F-NEXT: fsrmi a0, 1
1099 ; CHECK-F-NEXT: vfcvt.f.xu.v v16, v16
1100 ; CHECK-F-NEXT: vsrl.vi v16, v16, 23
1101 ; CHECK-F-NEXT: li a1, 127
1102 ; CHECK-F-NEXT: vsub.vx v16, v16, a1
1103 ; CHECK-F-NEXT: vmseq.vi v0, v8, 0
1104 ; CHECK-F-NEXT: li a1, 32
1105 ; CHECK-F-NEXT: vmerge.vxm v8, v16, a1, v0
1106 ; CHECK-F-NEXT: fsrm a0
1107 ; CHECK-F-NEXT: ret
1108 ;
1109 ; CHECK-D-LABEL: cttz_nxv16i32:
1110 ; CHECK-D: # %bb.0:
1111 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1112 ; CHECK-D-NEXT: vrsub.vi v16, v8, 0
1113 ; CHECK-D-NEXT: vand.vv v16, v8, v16
1114 ; CHECK-D-NEXT: fsrmi a0, 1
1115 ; CHECK-D-NEXT: vfcvt.f.xu.v v16, v16
1116 ; CHECK-D-NEXT: vsrl.vi v16, v16, 23
1117 ; CHECK-D-NEXT: li a1, 127
1118 ; CHECK-D-NEXT: vsub.vx v16, v16, a1
1119 ; CHECK-D-NEXT: vmseq.vi v0, v8, 0
1120 ; CHECK-D-NEXT: li a1, 32
1121 ; CHECK-D-NEXT: vmerge.vxm v8, v16, a1, v0
1122 ; CHECK-D-NEXT: fsrm a0
1123 ; CHECK-D-NEXT: ret
1124 ;
1125 ; CHECK-ZVBB-LABEL: cttz_nxv16i32:
1126 ; CHECK-ZVBB: # %bb.0:
1127 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
1128 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1129 ; CHECK-ZVBB-NEXT: ret
1130 %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 false)
1131 ret <vscale x 16 x i32> %a
1132 }
1133 declare <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32>, i1)
1135 define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
1136 ; RV32I-LABEL: cttz_nxv1i64:
1137 ; RV32I: # %bb.0:
1138 ; RV32I-NEXT: li a0, 1
1139 ; RV32I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
1140 ; RV32I-NEXT: vsub.vx v9, v8, a0
1141 ; RV32I-NEXT: vnot.v v8, v8
1142 ; RV32I-NEXT: vand.vv v8, v8, v9
1143 ; RV32I-NEXT: vsrl.vi v9, v8, 1
1144 ; RV32I-NEXT: lui a0, 349525
1145 ; RV32I-NEXT: addi a0, a0, 1365
1146 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1147 ; RV32I-NEXT: vmv.v.x v10, a0
1148 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1149 ; RV32I-NEXT: vand.vv v9, v9, v10
1150 ; RV32I-NEXT: vsub.vv v8, v8, v9
1151 ; RV32I-NEXT: lui a0, 209715
1152 ; RV32I-NEXT: addi a0, a0, 819
1153 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1154 ; RV32I-NEXT: vmv.v.x v9, a0
1155 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1156 ; RV32I-NEXT: vand.vv v10, v8, v9
1157 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1158 ; RV32I-NEXT: vand.vv v8, v8, v9
1159 ; RV32I-NEXT: vadd.vv v8, v10, v8
1160 ; RV32I-NEXT: vsrl.vi v9, v8, 4
1161 ; RV32I-NEXT: vadd.vv v8, v8, v9
1162 ; RV32I-NEXT: lui a0, 61681
1163 ; RV32I-NEXT: addi a0, a0, -241
1164 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1165 ; RV32I-NEXT: vmv.v.x v9, a0
1166 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1167 ; RV32I-NEXT: vand.vv v8, v8, v9
1168 ; RV32I-NEXT: lui a0, 4112
1169 ; RV32I-NEXT: addi a0, a0, 257
1170 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
1171 ; RV32I-NEXT: vmv.v.x v9, a0
1172 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1173 ; RV32I-NEXT: vmul.vv v8, v8, v9
1174 ; RV32I-NEXT: li a0, 56
1175 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1176 ; RV32I-NEXT: ret
1177 ;
1178 ; RV64I-LABEL: cttz_nxv1i64:
1179 ; RV64I: # %bb.0:
1180 ; RV64I-NEXT: li a0, 1
1181 ; RV64I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
1182 ; RV64I-NEXT: vsub.vx v9, v8, a0
1183 ; RV64I-NEXT: vnot.v v8, v8
1184 ; RV64I-NEXT: vand.vv v8, v8, v9
1185 ; RV64I-NEXT: vsrl.vi v9, v8, 1
1186 ; RV64I-NEXT: lui a0, 349525
1187 ; RV64I-NEXT: addiw a0, a0, 1365
1188 ; RV64I-NEXT: slli a1, a0, 32
1189 ; RV64I-NEXT: add a0, a0, a1
1190 ; RV64I-NEXT: vand.vx v9, v9, a0
1191 ; RV64I-NEXT: vsub.vv v8, v8, v9
1192 ; RV64I-NEXT: lui a0, 209715
1193 ; RV64I-NEXT: addiw a0, a0, 819
1194 ; RV64I-NEXT: slli a1, a0, 32
1195 ; RV64I-NEXT: add a0, a0, a1
1196 ; RV64I-NEXT: vand.vx v9, v8, a0
1197 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1198 ; RV64I-NEXT: vand.vx v8, v8, a0
1199 ; RV64I-NEXT: vadd.vv v8, v9, v8
1200 ; RV64I-NEXT: vsrl.vi v9, v8, 4
1201 ; RV64I-NEXT: vadd.vv v8, v8, v9
1202 ; RV64I-NEXT: lui a0, 61681
1203 ; RV64I-NEXT: addiw a0, a0, -241
1204 ; RV64I-NEXT: slli a1, a0, 32
1205 ; RV64I-NEXT: add a0, a0, a1
1206 ; RV64I-NEXT: vand.vx v8, v8, a0
1207 ; RV64I-NEXT: lui a0, 4112
1208 ; RV64I-NEXT: addiw a0, a0, 257
1209 ; RV64I-NEXT: slli a1, a0, 32
1210 ; RV64I-NEXT: add a0, a0, a1
1211 ; RV64I-NEXT: vmul.vx v8, v8, a0
1212 ; RV64I-NEXT: li a0, 56
1213 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1214 ; RV64I-NEXT: ret
1215 ;
1216 ; RV32F-LABEL: cttz_nxv1i64:
1217 ; RV32F: # %bb.0:
1218 ; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1219 ; RV32F-NEXT: vmseq.vx v0, v8, zero
1220 ; RV32F-NEXT: vrsub.vi v9, v8, 0
1221 ; RV32F-NEXT: vand.vv v8, v8, v9
1222 ; RV32F-NEXT: fsrmi a0, 1
1223 ; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
1224 ; RV32F-NEXT: vfncvt.f.xu.w v9, v8
1225 ; RV32F-NEXT: vsrl.vi v8, v9, 23
1226 ; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
1227 ; RV32F-NEXT: vzext.vf2 v9, v8
1228 ; RV32F-NEXT: li a1, 127
1229 ; RV32F-NEXT: vsub.vx v8, v9, a1
1230 ; RV32F-NEXT: li a1, 64
1231 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
1232 ; RV32F-NEXT: fsrm a0
1233 ; RV32F-NEXT: ret
1234 ;
1235 ; RV64F-LABEL: cttz_nxv1i64:
1236 ; RV64F: # %bb.0:
1237 ; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1238 ; RV64F-NEXT: vrsub.vi v9, v8, 0
1239 ; RV64F-NEXT: vand.vv v9, v8, v9
1240 ; RV64F-NEXT: fsrmi a0, 1
1241 ; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
1242 ; RV64F-NEXT: vfncvt.f.xu.w v10, v9
1243 ; RV64F-NEXT: vsrl.vi v9, v10, 23
1244 ; RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
1245 ; RV64F-NEXT: vzext.vf2 v10, v9
1246 ; RV64F-NEXT: li a1, 127
1247 ; RV64F-NEXT: vsub.vx v9, v10, a1
1248 ; RV64F-NEXT: vmseq.vi v0, v8, 0
1249 ; RV64F-NEXT: li a1, 64
1250 ; RV64F-NEXT: vmerge.vxm v8, v9, a1, v0
1251 ; RV64F-NEXT: fsrm a0
1252 ; RV64F-NEXT: ret
1253 ;
1254 ; RV32D-LABEL: cttz_nxv1i64:
1255 ; RV32D: # %bb.0:
1256 ; RV32D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1257 ; RV32D-NEXT: vmseq.vx v0, v8, zero
1258 ; RV32D-NEXT: vrsub.vi v9, v8, 0
1259 ; RV32D-NEXT: vand.vv v8, v8, v9
1260 ; RV32D-NEXT: fsrmi a0, 1
1261 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
1262 ; RV32D-NEXT: li a1, 52
1263 ; RV32D-NEXT: vsrl.vx v8, v8, a1
1264 ; RV32D-NEXT: li a1, 1023
1265 ; RV32D-NEXT: vsub.vx v8, v8, a1
1266 ; RV32D-NEXT: li a1, 64
1267 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
1268 ; RV32D-NEXT: fsrm a0
1269 ; RV32D-NEXT: ret
1270 ;
1271 ; RV64D-LABEL: cttz_nxv1i64:
1272 ; RV64D: # %bb.0:
1273 ; RV64D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1274 ; RV64D-NEXT: vrsub.vi v9, v8, 0
1275 ; RV64D-NEXT: vand.vv v9, v8, v9
1276 ; RV64D-NEXT: fsrmi a0, 1
1277 ; RV64D-NEXT: vfcvt.f.xu.v v9, v9
1278 ; RV64D-NEXT: li a1, 52
1279 ; RV64D-NEXT: vsrl.vx v9, v9, a1
1280 ; RV64D-NEXT: li a1, 1023
1281 ; RV64D-NEXT: vsub.vx v9, v9, a1
1282 ; RV64D-NEXT: vmseq.vi v0, v8, 0
1283 ; RV64D-NEXT: li a1, 64
1284 ; RV64D-NEXT: vmerge.vxm v8, v9, a1, v0
1285 ; RV64D-NEXT: fsrm a0
1286 ; RV64D-NEXT: ret
1287 ;
1288 ; CHECK-ZVBB-LABEL: cttz_nxv1i64:
1289 ; CHECK-ZVBB: # %bb.0:
1290 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
1291 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1292 ; CHECK-ZVBB-NEXT: ret
1293 %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 false)
1294 ret <vscale x 1 x i64> %a
1295 }
1296 declare <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64>, i1)
1298 define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
1299 ; RV32I-LABEL: cttz_nxv2i64:
1300 ; RV32I: # %bb.0:
1301 ; RV32I-NEXT: li a0, 1
1302 ; RV32I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1303 ; RV32I-NEXT: vsub.vx v10, v8, a0
1304 ; RV32I-NEXT: vnot.v v8, v8
1305 ; RV32I-NEXT: vand.vv v8, v8, v10
1306 ; RV32I-NEXT: vsrl.vi v10, v8, 1
1307 ; RV32I-NEXT: lui a0, 349525
1308 ; RV32I-NEXT: addi a0, a0, 1365
1309 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1310 ; RV32I-NEXT: vmv.v.x v12, a0
1311 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1312 ; RV32I-NEXT: vand.vv v10, v10, v12
1313 ; RV32I-NEXT: vsub.vv v8, v8, v10
1314 ; RV32I-NEXT: lui a0, 209715
1315 ; RV32I-NEXT: addi a0, a0, 819
1316 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1317 ; RV32I-NEXT: vmv.v.x v10, a0
1318 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1319 ; RV32I-NEXT: vand.vv v12, v8, v10
1320 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1321 ; RV32I-NEXT: vand.vv v8, v8, v10
1322 ; RV32I-NEXT: vadd.vv v8, v12, v8
1323 ; RV32I-NEXT: vsrl.vi v10, v8, 4
1324 ; RV32I-NEXT: vadd.vv v8, v8, v10
1325 ; RV32I-NEXT: lui a0, 61681
1326 ; RV32I-NEXT: addi a0, a0, -241
1327 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1328 ; RV32I-NEXT: vmv.v.x v10, a0
1329 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1330 ; RV32I-NEXT: vand.vv v8, v8, v10
1331 ; RV32I-NEXT: lui a0, 4112
1332 ; RV32I-NEXT: addi a0, a0, 257
1333 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
1334 ; RV32I-NEXT: vmv.v.x v10, a0
1335 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1336 ; RV32I-NEXT: vmul.vv v8, v8, v10
1337 ; RV32I-NEXT: li a0, 56
1338 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1339 ; RV32I-NEXT: ret
1340 ;
1341 ; RV64I-LABEL: cttz_nxv2i64:
1342 ; RV64I: # %bb.0:
1343 ; RV64I-NEXT: li a0, 1
1344 ; RV64I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
1345 ; RV64I-NEXT: vsub.vx v10, v8, a0
1346 ; RV64I-NEXT: vnot.v v8, v8
1347 ; RV64I-NEXT: vand.vv v8, v8, v10
1348 ; RV64I-NEXT: vsrl.vi v10, v8, 1
1349 ; RV64I-NEXT: lui a0, 349525
1350 ; RV64I-NEXT: addiw a0, a0, 1365
1351 ; RV64I-NEXT: slli a1, a0, 32
1352 ; RV64I-NEXT: add a0, a0, a1
1353 ; RV64I-NEXT: vand.vx v10, v10, a0
1354 ; RV64I-NEXT: vsub.vv v8, v8, v10
1355 ; RV64I-NEXT: lui a0, 209715
1356 ; RV64I-NEXT: addiw a0, a0, 819
1357 ; RV64I-NEXT: slli a1, a0, 32
1358 ; RV64I-NEXT: add a0, a0, a1
1359 ; RV64I-NEXT: vand.vx v10, v8, a0
1360 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1361 ; RV64I-NEXT: vand.vx v8, v8, a0
1362 ; RV64I-NEXT: vadd.vv v8, v10, v8
1363 ; RV64I-NEXT: vsrl.vi v10, v8, 4
1364 ; RV64I-NEXT: vadd.vv v8, v8, v10
1365 ; RV64I-NEXT: lui a0, 61681
1366 ; RV64I-NEXT: addiw a0, a0, -241
1367 ; RV64I-NEXT: slli a1, a0, 32
1368 ; RV64I-NEXT: add a0, a0, a1
1369 ; RV64I-NEXT: vand.vx v8, v8, a0
1370 ; RV64I-NEXT: lui a0, 4112
1371 ; RV64I-NEXT: addiw a0, a0, 257
1372 ; RV64I-NEXT: slli a1, a0, 32
1373 ; RV64I-NEXT: add a0, a0, a1
1374 ; RV64I-NEXT: vmul.vx v8, v8, a0
1375 ; RV64I-NEXT: li a0, 56
1376 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1377 ; RV64I-NEXT: ret
1378 ;
1379 ; RV32F-LABEL: cttz_nxv2i64:
1380 ; RV32F: # %bb.0:
1381 ; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1382 ; RV32F-NEXT: vmseq.vx v0, v8, zero
1383 ; RV32F-NEXT: vrsub.vi v10, v8, 0
1384 ; RV32F-NEXT: vand.vv v8, v8, v10
1385 ; RV32F-NEXT: fsrmi a0, 1
1386 ; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1387 ; RV32F-NEXT: vfncvt.f.xu.w v10, v8
1388 ; RV32F-NEXT: vsrl.vi v8, v10, 23
1389 ; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1390 ; RV32F-NEXT: vzext.vf2 v10, v8
1391 ; RV32F-NEXT: li a1, 127
1392 ; RV32F-NEXT: vsub.vx v8, v10, a1
1393 ; RV32F-NEXT: li a1, 64
1394 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
1395 ; RV32F-NEXT: fsrm a0
1396 ; RV32F-NEXT: ret
1397 ;
1398 ; RV64F-LABEL: cttz_nxv2i64:
1399 ; RV64F: # %bb.0:
1400 ; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1401 ; RV64F-NEXT: vrsub.vi v10, v8, 0
1402 ; RV64F-NEXT: vand.vv v10, v8, v10
1403 ; RV64F-NEXT: fsrmi a0, 1
1404 ; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
1405 ; RV64F-NEXT: vfncvt.f.xu.w v12, v10
1406 ; RV64F-NEXT: vsrl.vi v10, v12, 23
1407 ; RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
1408 ; RV64F-NEXT: vzext.vf2 v12, v10
1409 ; RV64F-NEXT: li a1, 127
1410 ; RV64F-NEXT: vsub.vx v10, v12, a1
1411 ; RV64F-NEXT: vmseq.vi v0, v8, 0
1412 ; RV64F-NEXT: li a1, 64
1413 ; RV64F-NEXT: vmerge.vxm v8, v10, a1, v0
1414 ; RV64F-NEXT: fsrm a0
1415 ; RV64F-NEXT: ret
1416 ;
1417 ; RV32D-LABEL: cttz_nxv2i64:
1418 ; RV32D: # %bb.0:
1419 ; RV32D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1420 ; RV32D-NEXT: vmseq.vx v0, v8, zero
1421 ; RV32D-NEXT: vrsub.vi v10, v8, 0
1422 ; RV32D-NEXT: vand.vv v8, v8, v10
1423 ; RV32D-NEXT: fsrmi a0, 1
1424 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
1425 ; RV32D-NEXT: li a1, 52
1426 ; RV32D-NEXT: vsrl.vx v8, v8, a1
1427 ; RV32D-NEXT: li a1, 1023
1428 ; RV32D-NEXT: vsub.vx v8, v8, a1
1429 ; RV32D-NEXT: li a1, 64
1430 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
1431 ; RV32D-NEXT: fsrm a0
1432 ; RV32D-NEXT: ret
1433 ;
1434 ; RV64D-LABEL: cttz_nxv2i64:
1435 ; RV64D: # %bb.0:
1436 ; RV64D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1437 ; RV64D-NEXT: vrsub.vi v10, v8, 0
1438 ; RV64D-NEXT: vand.vv v10, v8, v10
1439 ; RV64D-NEXT: fsrmi a0, 1
1440 ; RV64D-NEXT: vfcvt.f.xu.v v10, v10
1441 ; RV64D-NEXT: li a1, 52
1442 ; RV64D-NEXT: vsrl.vx v10, v10, a1
1443 ; RV64D-NEXT: li a1, 1023
1444 ; RV64D-NEXT: vsub.vx v10, v10, a1
1445 ; RV64D-NEXT: vmseq.vi v0, v8, 0
1446 ; RV64D-NEXT: li a1, 64
1447 ; RV64D-NEXT: vmerge.vxm v8, v10, a1, v0
1448 ; RV64D-NEXT: fsrm a0
1449 ; RV64D-NEXT: ret
1450 ;
1451 ; CHECK-ZVBB-LABEL: cttz_nxv2i64:
1452 ; CHECK-ZVBB: # %bb.0:
1453 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
1454 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1455 ; CHECK-ZVBB-NEXT: ret
1456 %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false)
1457 ret <vscale x 2 x i64> %a
1458 }
1459 declare <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64>, i1)
1461 define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
1462 ; RV32I-LABEL: cttz_nxv4i64:
1463 ; RV32I: # %bb.0:
1464 ; RV32I-NEXT: li a0, 1
1465 ; RV32I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
1466 ; RV32I-NEXT: vsub.vx v12, v8, a0
1467 ; RV32I-NEXT: vnot.v v8, v8
1468 ; RV32I-NEXT: vand.vv v8, v8, v12
1469 ; RV32I-NEXT: vsrl.vi v12, v8, 1
1470 ; RV32I-NEXT: lui a0, 349525
1471 ; RV32I-NEXT: addi a0, a0, 1365
1472 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1473 ; RV32I-NEXT: vmv.v.x v16, a0
1474 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1475 ; RV32I-NEXT: vand.vv v12, v12, v16
1476 ; RV32I-NEXT: vsub.vv v8, v8, v12
1477 ; RV32I-NEXT: lui a0, 209715
1478 ; RV32I-NEXT: addi a0, a0, 819
1479 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1480 ; RV32I-NEXT: vmv.v.x v12, a0
1481 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1482 ; RV32I-NEXT: vand.vv v16, v8, v12
1483 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1484 ; RV32I-NEXT: vand.vv v8, v8, v12
1485 ; RV32I-NEXT: vadd.vv v8, v16, v8
1486 ; RV32I-NEXT: vsrl.vi v12, v8, 4
1487 ; RV32I-NEXT: vadd.vv v8, v8, v12
1488 ; RV32I-NEXT: lui a0, 61681
1489 ; RV32I-NEXT: addi a0, a0, -241
1490 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1491 ; RV32I-NEXT: vmv.v.x v12, a0
1492 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1493 ; RV32I-NEXT: vand.vv v8, v8, v12
1494 ; RV32I-NEXT: lui a0, 4112
1495 ; RV32I-NEXT: addi a0, a0, 257
1496 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
1497 ; RV32I-NEXT: vmv.v.x v12, a0
1498 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1499 ; RV32I-NEXT: vmul.vv v8, v8, v12
1500 ; RV32I-NEXT: li a0, 56
1501 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1502 ; RV32I-NEXT: ret
1503 ;
1504 ; RV64I-LABEL: cttz_nxv4i64:
1505 ; RV64I: # %bb.0:
1506 ; RV64I-NEXT: li a0, 1
1507 ; RV64I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
1508 ; RV64I-NEXT: vsub.vx v12, v8, a0
1509 ; RV64I-NEXT: vnot.v v8, v8
1510 ; RV64I-NEXT: vand.vv v8, v8, v12
1511 ; RV64I-NEXT: vsrl.vi v12, v8, 1
1512 ; RV64I-NEXT: lui a0, 349525
1513 ; RV64I-NEXT: addiw a0, a0, 1365
1514 ; RV64I-NEXT: slli a1, a0, 32
1515 ; RV64I-NEXT: add a0, a0, a1
1516 ; RV64I-NEXT: vand.vx v12, v12, a0
1517 ; RV64I-NEXT: vsub.vv v8, v8, v12
1518 ; RV64I-NEXT: lui a0, 209715
1519 ; RV64I-NEXT: addiw a0, a0, 819
1520 ; RV64I-NEXT: slli a1, a0, 32
1521 ; RV64I-NEXT: add a0, a0, a1
1522 ; RV64I-NEXT: vand.vx v12, v8, a0
1523 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1524 ; RV64I-NEXT: vand.vx v8, v8, a0
1525 ; RV64I-NEXT: vadd.vv v8, v12, v8
1526 ; RV64I-NEXT: vsrl.vi v12, v8, 4
1527 ; RV64I-NEXT: vadd.vv v8, v8, v12
1528 ; RV64I-NEXT: lui a0, 61681
1529 ; RV64I-NEXT: addiw a0, a0, -241
1530 ; RV64I-NEXT: slli a1, a0, 32
1531 ; RV64I-NEXT: add a0, a0, a1
1532 ; RV64I-NEXT: vand.vx v8, v8, a0
1533 ; RV64I-NEXT: lui a0, 4112
1534 ; RV64I-NEXT: addiw a0, a0, 257
1535 ; RV64I-NEXT: slli a1, a0, 32
1536 ; RV64I-NEXT: add a0, a0, a1
1537 ; RV64I-NEXT: vmul.vx v8, v8, a0
1538 ; RV64I-NEXT: li a0, 56
1539 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1540 ; RV64I-NEXT: ret
1541 ;
1542 ; RV32F-LABEL: cttz_nxv4i64:
1543 ; RV32F: # %bb.0:
1544 ; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1545 ; RV32F-NEXT: vmseq.vx v0, v8, zero
1546 ; RV32F-NEXT: vrsub.vi v12, v8, 0
1547 ; RV32F-NEXT: vand.vv v8, v8, v12
1548 ; RV32F-NEXT: fsrmi a0, 1
1549 ; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1550 ; RV32F-NEXT: vfncvt.f.xu.w v12, v8
1551 ; RV32F-NEXT: vsrl.vi v8, v12, 23
1552 ; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1553 ; RV32F-NEXT: vzext.vf2 v12, v8
1554 ; RV32F-NEXT: li a1, 127
1555 ; RV32F-NEXT: vsub.vx v8, v12, a1
1556 ; RV32F-NEXT: li a1, 64
1557 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
1558 ; RV32F-NEXT: fsrm a0
1559 ; RV32F-NEXT: ret
1560 ;
1561 ; RV64F-LABEL: cttz_nxv4i64:
1562 ; RV64F: # %bb.0:
1563 ; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1564 ; RV64F-NEXT: vrsub.vi v12, v8, 0
1565 ; RV64F-NEXT: vand.vv v12, v8, v12
1566 ; RV64F-NEXT: fsrmi a0, 1
1567 ; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
1568 ; RV64F-NEXT: vfncvt.f.xu.w v16, v12
1569 ; RV64F-NEXT: vsrl.vi v12, v16, 23
1570 ; RV64F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
1571 ; RV64F-NEXT: vzext.vf2 v16, v12
1572 ; RV64F-NEXT: li a1, 127
1573 ; RV64F-NEXT: vsub.vx v12, v16, a1
1574 ; RV64F-NEXT: vmseq.vi v0, v8, 0
1575 ; RV64F-NEXT: li a1, 64
1576 ; RV64F-NEXT: vmerge.vxm v8, v12, a1, v0
1577 ; RV64F-NEXT: fsrm a0
1578 ; RV64F-NEXT: ret
1579 ;
1580 ; RV32D-LABEL: cttz_nxv4i64:
1581 ; RV32D: # %bb.0:
1582 ; RV32D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1583 ; RV32D-NEXT: vmseq.vx v0, v8, zero
1584 ; RV32D-NEXT: vrsub.vi v12, v8, 0
1585 ; RV32D-NEXT: vand.vv v8, v8, v12
1586 ; RV32D-NEXT: fsrmi a0, 1
1587 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
1588 ; RV32D-NEXT: li a1, 52
1589 ; RV32D-NEXT: vsrl.vx v8, v8, a1
1590 ; RV32D-NEXT: li a1, 1023
1591 ; RV32D-NEXT: vsub.vx v8, v8, a1
1592 ; RV32D-NEXT: li a1, 64
1593 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
1594 ; RV32D-NEXT: fsrm a0
1595 ; RV32D-NEXT: ret
1596 ;
1597 ; RV64D-LABEL: cttz_nxv4i64:
1598 ; RV64D: # %bb.0:
1599 ; RV64D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1600 ; RV64D-NEXT: vrsub.vi v12, v8, 0
1601 ; RV64D-NEXT: vand.vv v12, v8, v12
1602 ; RV64D-NEXT: fsrmi a0, 1
1603 ; RV64D-NEXT: vfcvt.f.xu.v v12, v12
1604 ; RV64D-NEXT: li a1, 52
1605 ; RV64D-NEXT: vsrl.vx v12, v12, a1
1606 ; RV64D-NEXT: li a1, 1023
1607 ; RV64D-NEXT: vsub.vx v12, v12, a1
1608 ; RV64D-NEXT: vmseq.vi v0, v8, 0
1609 ; RV64D-NEXT: li a1, 64
1610 ; RV64D-NEXT: vmerge.vxm v8, v12, a1, v0
1611 ; RV64D-NEXT: fsrm a0
1612 ; RV64D-NEXT: ret
1613 ;
1614 ; CHECK-ZVBB-LABEL: cttz_nxv4i64:
1615 ; CHECK-ZVBB: # %bb.0:
1616 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
1617 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1618 ; CHECK-ZVBB-NEXT: ret
1619 %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 false)
1620 ret <vscale x 4 x i64> %a
1621 }
1622 declare <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64>, i1)
1624 define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
1625 ; RV32I-LABEL: cttz_nxv8i64:
1626 ; RV32I: # %bb.0:
1627 ; RV32I-NEXT: li a0, 1
1628 ; RV32I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
1629 ; RV32I-NEXT: vsub.vx v16, v8, a0
1630 ; RV32I-NEXT: vnot.v v8, v8
1631 ; RV32I-NEXT: vand.vv v8, v8, v16
1632 ; RV32I-NEXT: vsrl.vi v16, v8, 1
1633 ; RV32I-NEXT: lui a0, 349525
1634 ; RV32I-NEXT: addi a0, a0, 1365
1635 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1636 ; RV32I-NEXT: vmv.v.x v24, a0
1637 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1638 ; RV32I-NEXT: vand.vv v16, v16, v24
1639 ; RV32I-NEXT: vsub.vv v8, v8, v16
1640 ; RV32I-NEXT: lui a0, 209715
1641 ; RV32I-NEXT: addi a0, a0, 819
1642 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1643 ; RV32I-NEXT: vmv.v.x v16, a0
1644 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1645 ; RV32I-NEXT: vand.vv v24, v8, v16
1646 ; RV32I-NEXT: vsrl.vi v8, v8, 2
1647 ; RV32I-NEXT: vand.vv v8, v8, v16
1648 ; RV32I-NEXT: vadd.vv v8, v24, v8
1649 ; RV32I-NEXT: vsrl.vi v16, v8, 4
1650 ; RV32I-NEXT: vadd.vv v8, v8, v16
1651 ; RV32I-NEXT: lui a0, 61681
1652 ; RV32I-NEXT: addi a0, a0, -241
1653 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1654 ; RV32I-NEXT: vmv.v.x v16, a0
1655 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1656 ; RV32I-NEXT: vand.vv v8, v8, v16
1657 ; RV32I-NEXT: lui a0, 4112
1658 ; RV32I-NEXT: addi a0, a0, 257
1659 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
1660 ; RV32I-NEXT: vmv.v.x v16, a0
1661 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1662 ; RV32I-NEXT: vmul.vv v8, v8, v16
1663 ; RV32I-NEXT: li a0, 56
1664 ; RV32I-NEXT: vsrl.vx v8, v8, a0
1665 ; RV32I-NEXT: ret
1666 ;
1667 ; RV64I-LABEL: cttz_nxv8i64:
1668 ; RV64I: # %bb.0:
1669 ; RV64I-NEXT: li a0, 1
1670 ; RV64I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
1671 ; RV64I-NEXT: vsub.vx v16, v8, a0
1672 ; RV64I-NEXT: vnot.v v8, v8
1673 ; RV64I-NEXT: vand.vv v8, v8, v16
1674 ; RV64I-NEXT: vsrl.vi v16, v8, 1
1675 ; RV64I-NEXT: lui a0, 349525
1676 ; RV64I-NEXT: addiw a0, a0, 1365
1677 ; RV64I-NEXT: slli a1, a0, 32
1678 ; RV64I-NEXT: add a0, a0, a1
1679 ; RV64I-NEXT: vand.vx v16, v16, a0
1680 ; RV64I-NEXT: vsub.vv v8, v8, v16
1681 ; RV64I-NEXT: lui a0, 209715
1682 ; RV64I-NEXT: addiw a0, a0, 819
1683 ; RV64I-NEXT: slli a1, a0, 32
1684 ; RV64I-NEXT: add a0, a0, a1
1685 ; RV64I-NEXT: vand.vx v16, v8, a0
1686 ; RV64I-NEXT: vsrl.vi v8, v8, 2
1687 ; RV64I-NEXT: vand.vx v8, v8, a0
1688 ; RV64I-NEXT: vadd.vv v8, v16, v8
1689 ; RV64I-NEXT: vsrl.vi v16, v8, 4
1690 ; RV64I-NEXT: vadd.vv v8, v8, v16
1691 ; RV64I-NEXT: lui a0, 61681
1692 ; RV64I-NEXT: addiw a0, a0, -241
1693 ; RV64I-NEXT: slli a1, a0, 32
1694 ; RV64I-NEXT: add a0, a0, a1
1695 ; RV64I-NEXT: vand.vx v8, v8, a0
1696 ; RV64I-NEXT: lui a0, 4112
1697 ; RV64I-NEXT: addiw a0, a0, 257
1698 ; RV64I-NEXT: slli a1, a0, 32
1699 ; RV64I-NEXT: add a0, a0, a1
1700 ; RV64I-NEXT: vmul.vx v8, v8, a0
1701 ; RV64I-NEXT: li a0, 56
1702 ; RV64I-NEXT: vsrl.vx v8, v8, a0
1703 ; RV64I-NEXT: ret
1704 ;
1705 ; RV32F-LABEL: cttz_nxv8i64:
1706 ; RV32F: # %bb.0:
1707 ; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1708 ; RV32F-NEXT: vmseq.vx v0, v8, zero
1709 ; RV32F-NEXT: vrsub.vi v16, v8, 0
1710 ; RV32F-NEXT: vand.vv v8, v8, v16
1711 ; RV32F-NEXT: fsrmi a0, 1
1712 ; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1713 ; RV32F-NEXT: vfncvt.f.xu.w v16, v8
1714 ; RV32F-NEXT: vsrl.vi v8, v16, 23
1715 ; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1716 ; RV32F-NEXT: vzext.vf2 v16, v8
1717 ; RV32F-NEXT: li a1, 127
1718 ; RV32F-NEXT: vsub.vx v8, v16, a1
1719 ; RV32F-NEXT: li a1, 64
1720 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
1721 ; RV32F-NEXT: fsrm a0
1722 ; RV32F-NEXT: ret
1723 ;
1724 ; RV64F-LABEL: cttz_nxv8i64:
1725 ; RV64F: # %bb.0:
1726 ; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1727 ; RV64F-NEXT: vrsub.vi v16, v8, 0
1728 ; RV64F-NEXT: vand.vv v16, v8, v16
1729 ; RV64F-NEXT: fsrmi a0, 1
1730 ; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
1731 ; RV64F-NEXT: vfncvt.f.xu.w v24, v16
1732 ; RV64F-NEXT: vsrl.vi v16, v24, 23
1733 ; RV64F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1734 ; RV64F-NEXT: vzext.vf2 v24, v16
1735 ; RV64F-NEXT: li a1, 127
1736 ; RV64F-NEXT: vsub.vx v16, v24, a1
1737 ; RV64F-NEXT: vmseq.vi v0, v8, 0
1738 ; RV64F-NEXT: li a1, 64
1739 ; RV64F-NEXT: vmerge.vxm v8, v16, a1, v0
1740 ; RV64F-NEXT: fsrm a0
1741 ; RV64F-NEXT: ret
1742 ;
1743 ; RV32D-LABEL: cttz_nxv8i64:
1744 ; RV32D: # %bb.0:
1745 ; RV32D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1746 ; RV32D-NEXT: vmseq.vx v0, v8, zero
1747 ; RV32D-NEXT: vrsub.vi v16, v8, 0
1748 ; RV32D-NEXT: vand.vv v8, v8, v16
1749 ; RV32D-NEXT: fsrmi a0, 1
1750 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
1751 ; RV32D-NEXT: li a1, 52
1752 ; RV32D-NEXT: vsrl.vx v8, v8, a1
1753 ; RV32D-NEXT: li a1, 1023
1754 ; RV32D-NEXT: vsub.vx v8, v8, a1
1755 ; RV32D-NEXT: li a1, 64
1756 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
1757 ; RV32D-NEXT: fsrm a0
1758 ; RV32D-NEXT: ret
1759 ;
1760 ; RV64D-LABEL: cttz_nxv8i64:
1761 ; RV64D: # %bb.0:
1762 ; RV64D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1763 ; RV64D-NEXT: vrsub.vi v16, v8, 0
1764 ; RV64D-NEXT: vand.vv v16, v8, v16
1765 ; RV64D-NEXT: fsrmi a0, 1
1766 ; RV64D-NEXT: vfcvt.f.xu.v v16, v16
1767 ; RV64D-NEXT: li a1, 52
1768 ; RV64D-NEXT: vsrl.vx v16, v16, a1
1769 ; RV64D-NEXT: li a1, 1023
1770 ; RV64D-NEXT: vsub.vx v16, v16, a1
1771 ; RV64D-NEXT: vmseq.vi v0, v8, 0
1772 ; RV64D-NEXT: li a1, 64
1773 ; RV64D-NEXT: vmerge.vxm v8, v16, a1, v0
1774 ; RV64D-NEXT: fsrm a0
1775 ; RV64D-NEXT: ret
1776 ;
1777 ; CHECK-ZVBB-LABEL: cttz_nxv8i64:
1778 ; CHECK-ZVBB: # %bb.0:
1779 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
1780 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1781 ; CHECK-ZVBB-NEXT: ret
1782 %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 false)
1783 ret <vscale x 8 x i64> %a
1784 }
1785 declare <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64>, i1)
1787 define <vscale x 1 x i8> @cttz_zero_undef_nxv1i8(<vscale x 1 x i8> %va) {
1788 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i8:
1789 ; CHECK-ZVE64X: # %bb.0:
1790 ; CHECK-ZVE64X-NEXT: li a0, 1
1791 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
1792 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1793 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1794 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1795 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1796 ; CHECK-ZVE64X-NEXT: li a0, 85
1797 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1798 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1799 ; CHECK-ZVE64X-NEXT: li a0, 51
1800 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1801 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1802 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1803 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1804 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1805 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1806 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1807 ; CHECK-ZVE64X-NEXT: ret
1808 ;
1809 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i8:
1810 ; CHECK-F: # %bb.0:
1811 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
1812 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1813 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1814 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
1815 ; CHECK-F-NEXT: vzext.vf2 v9, v8
1816 ; CHECK-F-NEXT: vfwcvt.f.xu.v v8, v9
1817 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 23
1818 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
1819 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 0
1820 ; CHECK-F-NEXT: li a0, 127
1821 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
1822 ; CHECK-F-NEXT: ret
1823 ;
1824 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i8:
1825 ; CHECK-D: # %bb.0:
1826 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
1827 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1828 ; CHECK-D-NEXT: vand.vv v8, v8, v9
1829 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
1830 ; CHECK-D-NEXT: vzext.vf2 v9, v8
1831 ; CHECK-D-NEXT: vfwcvt.f.xu.v v8, v9
1832 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 23
1833 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
1834 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
1835 ; CHECK-D-NEXT: li a0, 127
1836 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
1837 ; CHECK-D-NEXT: ret
1838 ;
1839 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i8:
1840 ; CHECK-ZVBB: # %bb.0:
1841 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
1842 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1843 ; CHECK-ZVBB-NEXT: ret
1844 %a = call <vscale x 1 x i8> @llvm.cttz.nxv1i8(<vscale x 1 x i8> %va, i1 true)
1845 ret <vscale x 1 x i8> %a
1846 }
1848 define <vscale x 2 x i8> @cttz_zero_undef_nxv2i8(<vscale x 2 x i8> %va) {
1849 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i8:
1850 ; CHECK-ZVE64X: # %bb.0:
1851 ; CHECK-ZVE64X-NEXT: li a0, 1
1852 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
1853 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1854 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1855 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1856 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1857 ; CHECK-ZVE64X-NEXT: li a0, 85
1858 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1859 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1860 ; CHECK-ZVE64X-NEXT: li a0, 51
1861 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1862 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1863 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1864 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1865 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1866 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1867 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1868 ; CHECK-ZVE64X-NEXT: ret
1869 ;
1870 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i8:
1871 ; CHECK-F: # %bb.0:
1872 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
1873 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1874 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1875 ; CHECK-F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1876 ; CHECK-F-NEXT: vzext.vf2 v9, v8
1877 ; CHECK-F-NEXT: vfwcvt.f.xu.v v8, v9
1878 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 23
1879 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
1880 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 0
1881 ; CHECK-F-NEXT: li a0, 127
1882 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
1883 ; CHECK-F-NEXT: ret
1884 ;
1885 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i8:
1886 ; CHECK-D: # %bb.0:
1887 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
1888 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1889 ; CHECK-D-NEXT: vand.vv v8, v8, v9
1890 ; CHECK-D-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
1891 ; CHECK-D-NEXT: vzext.vf2 v9, v8
1892 ; CHECK-D-NEXT: vfwcvt.f.xu.v v8, v9
1893 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 23
1894 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
1895 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
1896 ; CHECK-D-NEXT: li a0, 127
1897 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
1898 ; CHECK-D-NEXT: ret
1899 ;
1900 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i8:
1901 ; CHECK-ZVBB: # %bb.0:
1902 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
1903 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1904 ; CHECK-ZVBB-NEXT: ret
1905 %a = call <vscale x 2 x i8> @llvm.cttz.nxv2i8(<vscale x 2 x i8> %va, i1 true)
1906 ret <vscale x 2 x i8> %a
1907 }
1909 define <vscale x 4 x i8> @cttz_zero_undef_nxv4i8(<vscale x 4 x i8> %va) {
1910 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i8:
1911 ; CHECK-ZVE64X: # %bb.0:
1912 ; CHECK-ZVE64X-NEXT: li a0, 1
1913 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
1914 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1915 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1916 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1917 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1918 ; CHECK-ZVE64X-NEXT: li a0, 85
1919 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1920 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1921 ; CHECK-ZVE64X-NEXT: li a0, 51
1922 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1923 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1924 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1925 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1926 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1927 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1928 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1929 ; CHECK-ZVE64X-NEXT: ret
1930 ;
1931 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i8:
1932 ; CHECK-F: # %bb.0:
1933 ; CHECK-F-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
1934 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1935 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1936 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1937 ; CHECK-F-NEXT: vzext.vf2 v9, v8
1938 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v9
1939 ; CHECK-F-NEXT: vnsrl.wi v8, v10, 23
1940 ; CHECK-F-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
1941 ; CHECK-F-NEXT: vnsrl.wi v8, v8, 0
1942 ; CHECK-F-NEXT: li a0, 127
1943 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
1944 ; CHECK-F-NEXT: ret
1945 ;
1946 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i8:
1947 ; CHECK-D: # %bb.0:
1948 ; CHECK-D-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
1949 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
1950 ; CHECK-D-NEXT: vand.vv v8, v8, v9
1951 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m1, ta, ma
1952 ; CHECK-D-NEXT: vzext.vf2 v9, v8
1953 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v9
1954 ; CHECK-D-NEXT: vnsrl.wi v8, v10, 23
1955 ; CHECK-D-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
1956 ; CHECK-D-NEXT: vnsrl.wi v8, v8, 0
1957 ; CHECK-D-NEXT: li a0, 127
1958 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
1959 ; CHECK-D-NEXT: ret
1960 ;
1961 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i8:
1962 ; CHECK-ZVBB: # %bb.0:
1963 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
1964 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
1965 ; CHECK-ZVBB-NEXT: ret
1966 %a = call <vscale x 4 x i8> @llvm.cttz.nxv4i8(<vscale x 4 x i8> %va, i1 true)
1967 ret <vscale x 4 x i8> %a
1968 }
1970 define <vscale x 8 x i8> @cttz_zero_undef_nxv8i8(<vscale x 8 x i8> %va) {
1971 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i8:
1972 ; CHECK-ZVE64X: # %bb.0:
1973 ; CHECK-ZVE64X-NEXT: li a0, 1
1974 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m1, ta, ma
1975 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
1976 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
1977 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
1978 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
1979 ; CHECK-ZVE64X-NEXT: li a0, 85
1980 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
1981 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
1982 ; CHECK-ZVE64X-NEXT: li a0, 51
1983 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
1984 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
1985 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
1986 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
1987 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
1988 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
1989 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
1990 ; CHECK-ZVE64X-NEXT: ret
1991 ;
1992 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i8:
1993 ; CHECK-F: # %bb.0:
1994 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m1, ta, ma
1995 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
1996 ; CHECK-F-NEXT: vand.vv v8, v8, v9
1997 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m2, ta, ma
1998 ; CHECK-F-NEXT: vzext.vf2 v10, v8
1999 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v10
2000 ; CHECK-F-NEXT: vnsrl.wi v8, v12, 23
2001 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m1, ta, ma
2002 ; CHECK-F-NEXT: vnsrl.wi v10, v8, 0
2003 ; CHECK-F-NEXT: li a0, 127
2004 ; CHECK-F-NEXT: vsub.vx v8, v10, a0
2005 ; CHECK-F-NEXT: ret
2006 ;
2007 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i8:
2008 ; CHECK-D: # %bb.0:
2009 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m1, ta, ma
2010 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2011 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2012 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m2, ta, ma
2013 ; CHECK-D-NEXT: vzext.vf2 v10, v8
2014 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v10
2015 ; CHECK-D-NEXT: vnsrl.wi v8, v12, 23
2016 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m1, ta, ma
2017 ; CHECK-D-NEXT: vnsrl.wi v10, v8, 0
2018 ; CHECK-D-NEXT: li a0, 127
2019 ; CHECK-D-NEXT: vsub.vx v8, v10, a0
2020 ; CHECK-D-NEXT: ret
2021 ;
2022 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i8:
2023 ; CHECK-ZVBB: # %bb.0:
2024 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m1, ta, ma
2025 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2026 ; CHECK-ZVBB-NEXT: ret
2027 %a = call <vscale x 8 x i8> @llvm.cttz.nxv8i8(<vscale x 8 x i8> %va, i1 true)
2028 ret <vscale x 8 x i8> %a
2029 }
2031 define <vscale x 16 x i8> @cttz_zero_undef_nxv16i8(<vscale x 16 x i8> %va) {
2032 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i8:
2033 ; CHECK-ZVE64X: # %bb.0:
2034 ; CHECK-ZVE64X-NEXT: li a0, 1
2035 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e8, m2, ta, ma
2036 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
2037 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2038 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
2039 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
2040 ; CHECK-ZVE64X-NEXT: li a0, 85
2041 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
2042 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
2043 ; CHECK-ZVE64X-NEXT: li a0, 51
2044 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
2045 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2046 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2047 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
2048 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
2049 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
2050 ; CHECK-ZVE64X-NEXT: vand.vi v8, v8, 15
2051 ; CHECK-ZVE64X-NEXT: ret
2052 ;
2053 ; CHECK-F-LABEL: cttz_zero_undef_nxv16i8:
2054 ; CHECK-F: # %bb.0:
2055 ; CHECK-F-NEXT: vsetvli a0, zero, e8, m2, ta, ma
2056 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
2057 ; CHECK-F-NEXT: vand.vv v8, v8, v10
2058 ; CHECK-F-NEXT: vsetvli zero, zero, e16, m4, ta, ma
2059 ; CHECK-F-NEXT: vzext.vf2 v12, v8
2060 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v12
2061 ; CHECK-F-NEXT: vnsrl.wi v8, v16, 23
2062 ; CHECK-F-NEXT: vsetvli zero, zero, e8, m2, ta, ma
2063 ; CHECK-F-NEXT: vnsrl.wi v12, v8, 0
2064 ; CHECK-F-NEXT: li a0, 127
2065 ; CHECK-F-NEXT: vsub.vx v8, v12, a0
2066 ; CHECK-F-NEXT: ret
2067 ;
2068 ; CHECK-D-LABEL: cttz_zero_undef_nxv16i8:
2069 ; CHECK-D: # %bb.0:
2070 ; CHECK-D-NEXT: vsetvli a0, zero, e8, m2, ta, ma
2071 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
2072 ; CHECK-D-NEXT: vand.vv v8, v8, v10
2073 ; CHECK-D-NEXT: vsetvli zero, zero, e16, m4, ta, ma
2074 ; CHECK-D-NEXT: vzext.vf2 v12, v8
2075 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v12
2076 ; CHECK-D-NEXT: vnsrl.wi v8, v16, 23
2077 ; CHECK-D-NEXT: vsetvli zero, zero, e8, m2, ta, ma
2078 ; CHECK-D-NEXT: vnsrl.wi v12, v8, 0
2079 ; CHECK-D-NEXT: li a0, 127
2080 ; CHECK-D-NEXT: vsub.vx v8, v12, a0
2081 ; CHECK-D-NEXT: ret
2082 ;
2083 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i8:
2084 ; CHECK-ZVBB: # %bb.0:
2085 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m2, ta, ma
2086 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2087 ; CHECK-ZVBB-NEXT: ret
2088 %a = call <vscale x 16 x i8> @llvm.cttz.nxv16i8(<vscale x 16 x i8> %va, i1 true)
2089 ret <vscale x 16 x i8> %a
2090 }
2092 define <vscale x 32 x i8> @cttz_zero_undef_nxv32i8(<vscale x 32 x i8> %va) {
2093 ; CHECK-LABEL: cttz_zero_undef_nxv32i8:
2094 ; CHECK: # %bb.0:
2095 ; CHECK-NEXT: li a0, 1
2096 ; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
2097 ; CHECK-NEXT: vsub.vx v12, v8, a0
2098 ; CHECK-NEXT: vnot.v v8, v8
2099 ; CHECK-NEXT: vand.vv v8, v8, v12
2100 ; CHECK-NEXT: vsrl.vi v12, v8, 1
2101 ; CHECK-NEXT: li a0, 85
2102 ; CHECK-NEXT: vand.vx v12, v12, a0
2103 ; CHECK-NEXT: vsub.vv v8, v8, v12
2104 ; CHECK-NEXT: li a0, 51
2105 ; CHECK-NEXT: vand.vx v12, v8, a0
2106 ; CHECK-NEXT: vsrl.vi v8, v8, 2
2107 ; CHECK-NEXT: vand.vx v8, v8, a0
2108 ; CHECK-NEXT: vadd.vv v8, v12, v8
2109 ; CHECK-NEXT: vsrl.vi v12, v8, 4
2110 ; CHECK-NEXT: vadd.vv v8, v8, v12
2111 ; CHECK-NEXT: vand.vi v8, v8, 15
2112 ; CHECK-NEXT: ret
2113 ;
2114 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv32i8:
2115 ; CHECK-ZVBB: # %bb.0:
2116 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m4, ta, ma
2117 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2118 ; CHECK-ZVBB-NEXT: ret
2119 %a = call <vscale x 32 x i8> @llvm.cttz.nxv32i8(<vscale x 32 x i8> %va, i1 true)
2120 ret <vscale x 32 x i8> %a
2121 }
2123 define <vscale x 64 x i8> @cttz_zero_undef_nxv64i8(<vscale x 64 x i8> %va) {
2124 ; CHECK-LABEL: cttz_zero_undef_nxv64i8:
2125 ; CHECK: # %bb.0:
2126 ; CHECK-NEXT: li a0, 1
2127 ; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
2128 ; CHECK-NEXT: vsub.vx v16, v8, a0
2129 ; CHECK-NEXT: vnot.v v8, v8
2130 ; CHECK-NEXT: vand.vv v8, v8, v16
2131 ; CHECK-NEXT: vsrl.vi v16, v8, 1
2132 ; CHECK-NEXT: li a0, 85
2133 ; CHECK-NEXT: vand.vx v16, v16, a0
2134 ; CHECK-NEXT: vsub.vv v8, v8, v16
2135 ; CHECK-NEXT: li a0, 51
2136 ; CHECK-NEXT: vand.vx v16, v8, a0
2137 ; CHECK-NEXT: vsrl.vi v8, v8, 2
2138 ; CHECK-NEXT: vand.vx v8, v8, a0
2139 ; CHECK-NEXT: vadd.vv v8, v16, v8
2140 ; CHECK-NEXT: vsrl.vi v16, v8, 4
2141 ; CHECK-NEXT: vadd.vv v8, v8, v16
2142 ; CHECK-NEXT: vand.vi v8, v8, 15
2143 ; CHECK-NEXT: ret
2144 ;
2145 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv64i8:
2146 ; CHECK-ZVBB: # %bb.0:
2147 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e8, m8, ta, ma
2148 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2149 ; CHECK-ZVBB-NEXT: ret
2150 %a = call <vscale x 64 x i8> @llvm.cttz.nxv64i8(<vscale x 64 x i8> %va, i1 true)
2151 ret <vscale x 64 x i8> %a
2152 }
2154 define <vscale x 1 x i16> @cttz_zero_undef_nxv1i16(<vscale x 1 x i16> %va) {
2155 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i16:
2156 ; CHECK-ZVE64X: # %bb.0:
2157 ; CHECK-ZVE64X-NEXT: li a0, 1
2158 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
2159 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2160 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2161 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2162 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2163 ; CHECK-ZVE64X-NEXT: lui a0, 5
2164 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2165 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2166 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2167 ; CHECK-ZVE64X-NEXT: lui a0, 3
2168 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2169 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2170 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2171 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2172 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2173 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2174 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2175 ; CHECK-ZVE64X-NEXT: lui a0, 1
2176 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2177 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2178 ; CHECK-ZVE64X-NEXT: li a0, 257
2179 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2180 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2181 ; CHECK-ZVE64X-NEXT: ret
2182 ;
2183 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i16:
2184 ; CHECK-F: # %bb.0:
2185 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2186 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2187 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2188 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v8
2189 ; CHECK-F-NEXT: vnsrl.wi v8, v9, 23
2190 ; CHECK-F-NEXT: li a0, 127
2191 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2192 ; CHECK-F-NEXT: ret
2193 ;
2194 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i16:
2195 ; CHECK-D: # %bb.0:
2196 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2197 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2198 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2199 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
2200 ; CHECK-D-NEXT: vnsrl.wi v8, v9, 23
2201 ; CHECK-D-NEXT: li a0, 127
2202 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2203 ; CHECK-D-NEXT: ret
2204 ;
2205 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i16:
2206 ; CHECK-ZVBB: # %bb.0:
2207 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
2208 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2209 ; CHECK-ZVBB-NEXT: ret
2210 %a = call <vscale x 1 x i16> @llvm.cttz.nxv1i16(<vscale x 1 x i16> %va, i1 true)
2211 ret <vscale x 1 x i16> %a
2212 }
2214 define <vscale x 2 x i16> @cttz_zero_undef_nxv2i16(<vscale x 2 x i16> %va) {
2215 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i16:
2216 ; CHECK-ZVE64X: # %bb.0:
2217 ; CHECK-ZVE64X-NEXT: li a0, 1
2218 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
2219 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2220 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2221 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2222 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2223 ; CHECK-ZVE64X-NEXT: lui a0, 5
2224 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2225 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2226 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2227 ; CHECK-ZVE64X-NEXT: lui a0, 3
2228 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2229 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2230 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2231 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2232 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2233 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2234 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2235 ; CHECK-ZVE64X-NEXT: lui a0, 1
2236 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2237 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2238 ; CHECK-ZVE64X-NEXT: li a0, 257
2239 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2240 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2241 ; CHECK-ZVE64X-NEXT: ret
2242 ;
2243 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i16:
2244 ; CHECK-F: # %bb.0:
2245 ; CHECK-F-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
2246 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2247 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2248 ; CHECK-F-NEXT: vfwcvt.f.xu.v v9, v8
2249 ; CHECK-F-NEXT: vnsrl.wi v8, v9, 23
2250 ; CHECK-F-NEXT: li a0, 127
2251 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2252 ; CHECK-F-NEXT: ret
2253 ;
2254 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i16:
2255 ; CHECK-D: # %bb.0:
2256 ; CHECK-D-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
2257 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2258 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2259 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
2260 ; CHECK-D-NEXT: vnsrl.wi v8, v9, 23
2261 ; CHECK-D-NEXT: li a0, 127
2262 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2263 ; CHECK-D-NEXT: ret
2264 ;
2265 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i16:
2266 ; CHECK-ZVBB: # %bb.0:
2267 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
2268 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2269 ; CHECK-ZVBB-NEXT: ret
2270 %a = call <vscale x 2 x i16> @llvm.cttz.nxv2i16(<vscale x 2 x i16> %va, i1 true)
2271 ret <vscale x 2 x i16> %a
2272 }
2274 define <vscale x 4 x i16> @cttz_zero_undef_nxv4i16(<vscale x 4 x i16> %va) {
2275 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i16:
2276 ; CHECK-ZVE64X: # %bb.0:
2277 ; CHECK-ZVE64X-NEXT: li a0, 1
2278 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m1, ta, ma
2279 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2280 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2281 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2282 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2283 ; CHECK-ZVE64X-NEXT: lui a0, 5
2284 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2285 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2286 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2287 ; CHECK-ZVE64X-NEXT: lui a0, 3
2288 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2289 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2290 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2291 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2292 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2293 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2294 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2295 ; CHECK-ZVE64X-NEXT: lui a0, 1
2296 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2297 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2298 ; CHECK-ZVE64X-NEXT: li a0, 257
2299 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2300 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2301 ; CHECK-ZVE64X-NEXT: ret
2302 ;
2303 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i16:
2304 ; CHECK-F: # %bb.0:
2305 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m1, ta, ma
2306 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2307 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2308 ; CHECK-F-NEXT: vfwcvt.f.xu.v v10, v8
2309 ; CHECK-F-NEXT: vnsrl.wi v8, v10, 23
2310 ; CHECK-F-NEXT: li a0, 127
2311 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2312 ; CHECK-F-NEXT: ret
2313 ;
2314 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i16:
2315 ; CHECK-D: # %bb.0:
2316 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m1, ta, ma
2317 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2318 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2319 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
2320 ; CHECK-D-NEXT: vnsrl.wi v8, v10, 23
2321 ; CHECK-D-NEXT: li a0, 127
2322 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2323 ; CHECK-D-NEXT: ret
2324 ;
2325 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i16:
2326 ; CHECK-ZVBB: # %bb.0:
2327 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m1, ta, ma
2328 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2329 ; CHECK-ZVBB-NEXT: ret
2330 %a = call <vscale x 4 x i16> @llvm.cttz.nxv4i16(<vscale x 4 x i16> %va, i1 true)
2331 ret <vscale x 4 x i16> %a
2332 }
2334 define <vscale x 8 x i16> @cttz_zero_undef_nxv8i16(<vscale x 8 x i16> %va) {
2335 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i16:
2336 ; CHECK-ZVE64X: # %bb.0:
2337 ; CHECK-ZVE64X-NEXT: li a0, 1
2338 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m2, ta, ma
2339 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
2340 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2341 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
2342 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
2343 ; CHECK-ZVE64X-NEXT: lui a0, 5
2344 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2345 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
2346 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
2347 ; CHECK-ZVE64X-NEXT: lui a0, 3
2348 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2349 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
2350 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2351 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2352 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
2353 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
2354 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
2355 ; CHECK-ZVE64X-NEXT: lui a0, 1
2356 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2357 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2358 ; CHECK-ZVE64X-NEXT: li a0, 257
2359 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2360 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2361 ; CHECK-ZVE64X-NEXT: ret
2362 ;
2363 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i16:
2364 ; CHECK-F: # %bb.0:
2365 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m2, ta, ma
2366 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
2367 ; CHECK-F-NEXT: vand.vv v8, v8, v10
2368 ; CHECK-F-NEXT: vfwcvt.f.xu.v v12, v8
2369 ; CHECK-F-NEXT: vnsrl.wi v8, v12, 23
2370 ; CHECK-F-NEXT: li a0, 127
2371 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2372 ; CHECK-F-NEXT: ret
2373 ;
2374 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i16:
2375 ; CHECK-D: # %bb.0:
2376 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m2, ta, ma
2377 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
2378 ; CHECK-D-NEXT: vand.vv v8, v8, v10
2379 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
2380 ; CHECK-D-NEXT: vnsrl.wi v8, v12, 23
2381 ; CHECK-D-NEXT: li a0, 127
2382 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2383 ; CHECK-D-NEXT: ret
2384 ;
2385 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i16:
2386 ; CHECK-ZVBB: # %bb.0:
2387 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m2, ta, ma
2388 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2389 ; CHECK-ZVBB-NEXT: ret
2390 %a = call <vscale x 8 x i16> @llvm.cttz.nxv8i16(<vscale x 8 x i16> %va, i1 true)
2391 ret <vscale x 8 x i16> %a
2392 }
2394 define <vscale x 16 x i16> @cttz_zero_undef_nxv16i16(<vscale x 16 x i16> %va) {
2395 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i16:
2396 ; CHECK-ZVE64X: # %bb.0:
2397 ; CHECK-ZVE64X-NEXT: li a0, 1
2398 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e16, m4, ta, ma
2399 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
2400 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2401 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
2402 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
2403 ; CHECK-ZVE64X-NEXT: lui a0, 5
2404 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2405 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
2406 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
2407 ; CHECK-ZVE64X-NEXT: lui a0, 3
2408 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2409 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
2410 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2411 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2412 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
2413 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
2414 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
2415 ; CHECK-ZVE64X-NEXT: lui a0, 1
2416 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2417 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2418 ; CHECK-ZVE64X-NEXT: li a0, 257
2419 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2420 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 8
2421 ; CHECK-ZVE64X-NEXT: ret
2422 ;
2423 ; CHECK-F-LABEL: cttz_zero_undef_nxv16i16:
2424 ; CHECK-F: # %bb.0:
2425 ; CHECK-F-NEXT: vsetvli a0, zero, e16, m4, ta, ma
2426 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
2427 ; CHECK-F-NEXT: vand.vv v8, v8, v12
2428 ; CHECK-F-NEXT: vfwcvt.f.xu.v v16, v8
2429 ; CHECK-F-NEXT: vnsrl.wi v8, v16, 23
2430 ; CHECK-F-NEXT: li a0, 127
2431 ; CHECK-F-NEXT: vsub.vx v8, v8, a0
2432 ; CHECK-F-NEXT: ret
2433 ;
2434 ; CHECK-D-LABEL: cttz_zero_undef_nxv16i16:
2435 ; CHECK-D: # %bb.0:
2436 ; CHECK-D-NEXT: vsetvli a0, zero, e16, m4, ta, ma
2437 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
2438 ; CHECK-D-NEXT: vand.vv v8, v8, v12
2439 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
2440 ; CHECK-D-NEXT: vnsrl.wi v8, v16, 23
2441 ; CHECK-D-NEXT: li a0, 127
2442 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2443 ; CHECK-D-NEXT: ret
2444 ;
2445 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i16:
2446 ; CHECK-ZVBB: # %bb.0:
2447 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m4, ta, ma
2448 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2449 ; CHECK-ZVBB-NEXT: ret
2450 %a = call <vscale x 16 x i16> @llvm.cttz.nxv16i16(<vscale x 16 x i16> %va, i1 true)
2451 ret <vscale x 16 x i16> %a
2452 }
2454 define <vscale x 32 x i16> @cttz_zero_undef_nxv32i16(<vscale x 32 x i16> %va) {
2455 ; CHECK-LABEL: cttz_zero_undef_nxv32i16:
2456 ; CHECK: # %bb.0:
2457 ; CHECK-NEXT: li a0, 1
2458 ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
2459 ; CHECK-NEXT: vsub.vx v16, v8, a0
2460 ; CHECK-NEXT: vnot.v v8, v8
2461 ; CHECK-NEXT: vand.vv v8, v8, v16
2462 ; CHECK-NEXT: vsrl.vi v16, v8, 1
2463 ; CHECK-NEXT: lui a0, 5
2464 ; CHECK-NEXT: addi a0, a0, 1365
2465 ; CHECK-NEXT: vand.vx v16, v16, a0
2466 ; CHECK-NEXT: vsub.vv v8, v8, v16
2467 ; CHECK-NEXT: lui a0, 3
2468 ; CHECK-NEXT: addi a0, a0, 819
2469 ; CHECK-NEXT: vand.vx v16, v8, a0
2470 ; CHECK-NEXT: vsrl.vi v8, v8, 2
2471 ; CHECK-NEXT: vand.vx v8, v8, a0
2472 ; CHECK-NEXT: vadd.vv v8, v16, v8
2473 ; CHECK-NEXT: vsrl.vi v16, v8, 4
2474 ; CHECK-NEXT: vadd.vv v8, v8, v16
2475 ; CHECK-NEXT: lui a0, 1
2476 ; CHECK-NEXT: addi a0, a0, -241
2477 ; CHECK-NEXT: vand.vx v8, v8, a0
2478 ; CHECK-NEXT: li a0, 257
2479 ; CHECK-NEXT: vmul.vx v8, v8, a0
2480 ; CHECK-NEXT: vsrl.vi v8, v8, 8
2481 ; CHECK-NEXT: ret
2482 ;
2483 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv32i16:
2484 ; CHECK-ZVBB: # %bb.0:
2485 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e16, m8, ta, ma
2486 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2487 ; CHECK-ZVBB-NEXT: ret
2488 %a = call <vscale x 32 x i16> @llvm.cttz.nxv32i16(<vscale x 32 x i16> %va, i1 true)
2489 ret <vscale x 32 x i16> %a
2490 }
2492 define <vscale x 1 x i32> @cttz_zero_undef_nxv1i32(<vscale x 1 x i32> %va) {
2493 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv1i32:
2494 ; CHECK-ZVE64X: # %bb.0:
2495 ; CHECK-ZVE64X-NEXT: li a0, 1
2496 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
2497 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2498 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2499 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2500 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2501 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2502 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2503 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2504 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2505 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2506 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2507 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2508 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2509 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2510 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2511 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2512 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2513 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2514 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2515 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2516 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2517 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2518 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2519 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2520 ; CHECK-ZVE64X-NEXT: ret
2521 ;
2522 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i32:
2523 ; CHECK-F: # %bb.0:
2524 ; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
2525 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2526 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2527 ; CHECK-F-NEXT: fsrmi a0, 1
2528 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2529 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2530 ; CHECK-F-NEXT: li a1, 127
2531 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2532 ; CHECK-F-NEXT: fsrm a0
2533 ; CHECK-F-NEXT: ret
2534 ;
2535 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i32:
2536 ; CHECK-D: # %bb.0:
2537 ; CHECK-D-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
2538 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2539 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2540 ; CHECK-D-NEXT: vfwcvt.f.xu.v v9, v8
2541 ; CHECK-D-NEXT: li a0, 52
2542 ; CHECK-D-NEXT: vnsrl.wx v8, v9, a0
2543 ; CHECK-D-NEXT: li a0, 1023
2544 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2545 ; CHECK-D-NEXT: ret
2546 ;
2547 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i32:
2548 ; CHECK-ZVBB: # %bb.0:
2549 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
2550 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2551 ; CHECK-ZVBB-NEXT: ret
2552 %a = call <vscale x 1 x i32> @llvm.cttz.nxv1i32(<vscale x 1 x i32> %va, i1 true)
2553 ret <vscale x 1 x i32> %a
2554 }
2556 define <vscale x 2 x i32> @cttz_zero_undef_nxv2i32(<vscale x 2 x i32> %va) {
2557 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv2i32:
2558 ; CHECK-ZVE64X: # %bb.0:
2559 ; CHECK-ZVE64X-NEXT: li a0, 1
2560 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2561 ; CHECK-ZVE64X-NEXT: vsub.vx v9, v8, a0
2562 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2563 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v9
2564 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 1
2565 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2566 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2567 ; CHECK-ZVE64X-NEXT: vand.vx v9, v9, a0
2568 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v9
2569 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2570 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2571 ; CHECK-ZVE64X-NEXT: vand.vx v9, v8, a0
2572 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2573 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2574 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v9, v8
2575 ; CHECK-ZVE64X-NEXT: vsrl.vi v9, v8, 4
2576 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v9
2577 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2578 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2579 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2580 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2581 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2582 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2583 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2584 ; CHECK-ZVE64X-NEXT: ret
2585 ;
2586 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i32:
2587 ; CHECK-F: # %bb.0:
2588 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
2589 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2590 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2591 ; CHECK-F-NEXT: fsrmi a0, 1
2592 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2593 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2594 ; CHECK-F-NEXT: li a1, 127
2595 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2596 ; CHECK-F-NEXT: fsrm a0
2597 ; CHECK-F-NEXT: ret
2598 ;
2599 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i32:
2600 ; CHECK-D: # %bb.0:
2601 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m1, ta, ma
2602 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2603 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2604 ; CHECK-D-NEXT: vfwcvt.f.xu.v v10, v8
2605 ; CHECK-D-NEXT: li a0, 52
2606 ; CHECK-D-NEXT: vnsrl.wx v8, v10, a0
2607 ; CHECK-D-NEXT: li a0, 1023
2608 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2609 ; CHECK-D-NEXT: ret
2610 ;
2611 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i32:
2612 ; CHECK-ZVBB: # %bb.0:
2613 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
2614 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2615 ; CHECK-ZVBB-NEXT: ret
2616 %a = call <vscale x 2 x i32> @llvm.cttz.nxv2i32(<vscale x 2 x i32> %va, i1 true)
2617 ret <vscale x 2 x i32> %a
2618 }
2620 define <vscale x 4 x i32> @cttz_zero_undef_nxv4i32(<vscale x 4 x i32> %va) {
2621 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv4i32:
2622 ; CHECK-ZVE64X: # %bb.0:
2623 ; CHECK-ZVE64X-NEXT: li a0, 1
2624 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2625 ; CHECK-ZVE64X-NEXT: vsub.vx v10, v8, a0
2626 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2627 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v10
2628 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 1
2629 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2630 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2631 ; CHECK-ZVE64X-NEXT: vand.vx v10, v10, a0
2632 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v10
2633 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2634 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2635 ; CHECK-ZVE64X-NEXT: vand.vx v10, v8, a0
2636 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2637 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2638 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v10, v8
2639 ; CHECK-ZVE64X-NEXT: vsrl.vi v10, v8, 4
2640 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v10
2641 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2642 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2643 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2644 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2645 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2646 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2647 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2648 ; CHECK-ZVE64X-NEXT: ret
2649 ;
2650 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i32:
2651 ; CHECK-F: # %bb.0:
2652 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
2653 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
2654 ; CHECK-F-NEXT: vand.vv v8, v8, v10
2655 ; CHECK-F-NEXT: fsrmi a0, 1
2656 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2657 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2658 ; CHECK-F-NEXT: li a1, 127
2659 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2660 ; CHECK-F-NEXT: fsrm a0
2661 ; CHECK-F-NEXT: ret
2662 ;
2663 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i32:
2664 ; CHECK-D: # %bb.0:
2665 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m2, ta, ma
2666 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
2667 ; CHECK-D-NEXT: vand.vv v8, v8, v10
2668 ; CHECK-D-NEXT: vfwcvt.f.xu.v v12, v8
2669 ; CHECK-D-NEXT: li a0, 52
2670 ; CHECK-D-NEXT: vnsrl.wx v8, v12, a0
2671 ; CHECK-D-NEXT: li a0, 1023
2672 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2673 ; CHECK-D-NEXT: ret
2674 ;
2675 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i32:
2676 ; CHECK-ZVBB: # %bb.0:
2677 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m2, ta, ma
2678 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2679 ; CHECK-ZVBB-NEXT: ret
2680 %a = call <vscale x 4 x i32> @llvm.cttz.nxv4i32(<vscale x 4 x i32> %va, i1 true)
2681 ret <vscale x 4 x i32> %a
2682 }
2684 define <vscale x 8 x i32> @cttz_zero_undef_nxv8i32(<vscale x 8 x i32> %va) {
2685 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv8i32:
2686 ; CHECK-ZVE64X: # %bb.0:
2687 ; CHECK-ZVE64X-NEXT: li a0, 1
2688 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m4, ta, ma
2689 ; CHECK-ZVE64X-NEXT: vsub.vx v12, v8, a0
2690 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2691 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v12
2692 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 1
2693 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2694 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2695 ; CHECK-ZVE64X-NEXT: vand.vx v12, v12, a0
2696 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v12
2697 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2698 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2699 ; CHECK-ZVE64X-NEXT: vand.vx v12, v8, a0
2700 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2701 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2702 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v12, v8
2703 ; CHECK-ZVE64X-NEXT: vsrl.vi v12, v8, 4
2704 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v12
2705 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2706 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2707 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2708 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2709 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2710 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2711 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2712 ; CHECK-ZVE64X-NEXT: ret
2713 ;
2714 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i32:
2715 ; CHECK-F: # %bb.0:
2716 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
2717 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
2718 ; CHECK-F-NEXT: vand.vv v8, v8, v12
2719 ; CHECK-F-NEXT: fsrmi a0, 1
2720 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2721 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2722 ; CHECK-F-NEXT: li a1, 127
2723 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2724 ; CHECK-F-NEXT: fsrm a0
2725 ; CHECK-F-NEXT: ret
2726 ;
2727 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i32:
2728 ; CHECK-D: # %bb.0:
2729 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m4, ta, ma
2730 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
2731 ; CHECK-D-NEXT: vand.vv v8, v8, v12
2732 ; CHECK-D-NEXT: vfwcvt.f.xu.v v16, v8
2733 ; CHECK-D-NEXT: li a0, 52
2734 ; CHECK-D-NEXT: vnsrl.wx v8, v16, a0
2735 ; CHECK-D-NEXT: li a0, 1023
2736 ; CHECK-D-NEXT: vsub.vx v8, v8, a0
2737 ; CHECK-D-NEXT: ret
2738 ;
2739 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i32:
2740 ; CHECK-ZVBB: # %bb.0:
2741 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m4, ta, ma
2742 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2743 ; CHECK-ZVBB-NEXT: ret
2744 %a = call <vscale x 8 x i32> @llvm.cttz.nxv8i32(<vscale x 8 x i32> %va, i1 true)
2745 ret <vscale x 8 x i32> %a
2746 }
2748 define <vscale x 16 x i32> @cttz_zero_undef_nxv16i32(<vscale x 16 x i32> %va) {
2749 ; CHECK-ZVE64X-LABEL: cttz_zero_undef_nxv16i32:
2750 ; CHECK-ZVE64X: # %bb.0:
2751 ; CHECK-ZVE64X-NEXT: li a0, 1
2752 ; CHECK-ZVE64X-NEXT: vsetvli a1, zero, e32, m8, ta, ma
2753 ; CHECK-ZVE64X-NEXT: vsub.vx v16, v8, a0
2754 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
2755 ; CHECK-ZVE64X-NEXT: vand.vv v8, v8, v16
2756 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 1
2757 ; CHECK-ZVE64X-NEXT: lui a0, 349525
2758 ; CHECK-ZVE64X-NEXT: addi a0, a0, 1365
2759 ; CHECK-ZVE64X-NEXT: vand.vx v16, v16, a0
2760 ; CHECK-ZVE64X-NEXT: vsub.vv v8, v8, v16
2761 ; CHECK-ZVE64X-NEXT: lui a0, 209715
2762 ; CHECK-ZVE64X-NEXT: addi a0, a0, 819
2763 ; CHECK-ZVE64X-NEXT: vand.vx v16, v8, a0
2764 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 2
2765 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2766 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v16, v8
2767 ; CHECK-ZVE64X-NEXT: vsrl.vi v16, v8, 4
2768 ; CHECK-ZVE64X-NEXT: vadd.vv v8, v8, v16
2769 ; CHECK-ZVE64X-NEXT: lui a0, 61681
2770 ; CHECK-ZVE64X-NEXT: addi a0, a0, -241
2771 ; CHECK-ZVE64X-NEXT: vand.vx v8, v8, a0
2772 ; CHECK-ZVE64X-NEXT: lui a0, 4112
2773 ; CHECK-ZVE64X-NEXT: addi a0, a0, 257
2774 ; CHECK-ZVE64X-NEXT: vmul.vx v8, v8, a0
2775 ; CHECK-ZVE64X-NEXT: vsrl.vi v8, v8, 24
2776 ; CHECK-ZVE64X-NEXT: ret
2777 ;
2778 ; CHECK-F-LABEL: cttz_zero_undef_nxv16i32:
2779 ; CHECK-F: # %bb.0:
2780 ; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
2781 ; CHECK-F-NEXT: vrsub.vi v16, v8, 0
2782 ; CHECK-F-NEXT: vand.vv v8, v8, v16
2783 ; CHECK-F-NEXT: fsrmi a0, 1
2784 ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
2785 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23
2786 ; CHECK-F-NEXT: li a1, 127
2787 ; CHECK-F-NEXT: vsub.vx v8, v8, a1
2788 ; CHECK-F-NEXT: fsrm a0
2789 ; CHECK-F-NEXT: ret
2790 ;
2791 ; CHECK-D-LABEL: cttz_zero_undef_nxv16i32:
2792 ; CHECK-D: # %bb.0:
2793 ; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
2794 ; CHECK-D-NEXT: vrsub.vi v16, v8, 0
2795 ; CHECK-D-NEXT: vand.vv v8, v8, v16
2796 ; CHECK-D-NEXT: fsrmi a0, 1
2797 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
2798 ; CHECK-D-NEXT: vsrl.vi v8, v8, 23
2799 ; CHECK-D-NEXT: li a1, 127
2800 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
2801 ; CHECK-D-NEXT: fsrm a0
2802 ; CHECK-D-NEXT: ret
2803 ;
2804 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv16i32:
2805 ; CHECK-ZVBB: # %bb.0:
2806 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m8, ta, ma
2807 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2808 ; CHECK-ZVBB-NEXT: ret
2809 %a = call <vscale x 16 x i32> @llvm.cttz.nxv16i32(<vscale x 16 x i32> %va, i1 true)
2810 ret <vscale x 16 x i32> %a
2811 }
2813 define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
2814 ; RV32I-LABEL: cttz_zero_undef_nxv1i64:
2815 ; RV32I: # %bb.0:
2816 ; RV32I-NEXT: li a0, 1
2817 ; RV32I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2818 ; RV32I-NEXT: vsub.vx v9, v8, a0
2819 ; RV32I-NEXT: vnot.v v8, v8
2820 ; RV32I-NEXT: vand.vv v8, v8, v9
2821 ; RV32I-NEXT: vsrl.vi v9, v8, 1
2822 ; RV32I-NEXT: lui a0, 349525
2823 ; RV32I-NEXT: addi a0, a0, 1365
2824 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2825 ; RV32I-NEXT: vmv.v.x v10, a0
2826 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2827 ; RV32I-NEXT: vand.vv v9, v9, v10
2828 ; RV32I-NEXT: vsub.vv v8, v8, v9
2829 ; RV32I-NEXT: lui a0, 209715
2830 ; RV32I-NEXT: addi a0, a0, 819
2831 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2832 ; RV32I-NEXT: vmv.v.x v9, a0
2833 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2834 ; RV32I-NEXT: vand.vv v10, v8, v9
2835 ; RV32I-NEXT: vsrl.vi v8, v8, 2
2836 ; RV32I-NEXT: vand.vv v8, v8, v9
2837 ; RV32I-NEXT: vadd.vv v8, v10, v8
2838 ; RV32I-NEXT: vsrl.vi v9, v8, 4
2839 ; RV32I-NEXT: vadd.vv v8, v8, v9
2840 ; RV32I-NEXT: lui a0, 61681
2841 ; RV32I-NEXT: addi a0, a0, -241
2842 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2843 ; RV32I-NEXT: vmv.v.x v9, a0
2844 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2845 ; RV32I-NEXT: vand.vv v8, v8, v9
2846 ; RV32I-NEXT: lui a0, 4112
2847 ; RV32I-NEXT: addi a0, a0, 257
2848 ; RV32I-NEXT: vsetvli a1, zero, e32, m1, ta, ma
2849 ; RV32I-NEXT: vmv.v.x v9, a0
2850 ; RV32I-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2851 ; RV32I-NEXT: vmul.vv v8, v8, v9
2852 ; RV32I-NEXT: li a0, 56
2853 ; RV32I-NEXT: vsrl.vx v8, v8, a0
2854 ; RV32I-NEXT: ret
2855 ;
2856 ; RV64I-LABEL: cttz_zero_undef_nxv1i64:
2857 ; RV64I: # %bb.0:
2858 ; RV64I-NEXT: li a0, 1
2859 ; RV64I-NEXT: vsetvli a1, zero, e64, m1, ta, ma
2860 ; RV64I-NEXT: vsub.vx v9, v8, a0
2861 ; RV64I-NEXT: vnot.v v8, v8
2862 ; RV64I-NEXT: vand.vv v8, v8, v9
2863 ; RV64I-NEXT: vsrl.vi v9, v8, 1
2864 ; RV64I-NEXT: lui a0, 349525
2865 ; RV64I-NEXT: addiw a0, a0, 1365
2866 ; RV64I-NEXT: slli a1, a0, 32
2867 ; RV64I-NEXT: add a0, a0, a1
2868 ; RV64I-NEXT: vand.vx v9, v9, a0
2869 ; RV64I-NEXT: vsub.vv v8, v8, v9
2870 ; RV64I-NEXT: lui a0, 209715
2871 ; RV64I-NEXT: addiw a0, a0, 819
2872 ; RV64I-NEXT: slli a1, a0, 32
2873 ; RV64I-NEXT: add a0, a0, a1
2874 ; RV64I-NEXT: vand.vx v9, v8, a0
2875 ; RV64I-NEXT: vsrl.vi v8, v8, 2
2876 ; RV64I-NEXT: vand.vx v8, v8, a0
2877 ; RV64I-NEXT: vadd.vv v8, v9, v8
2878 ; RV64I-NEXT: vsrl.vi v9, v8, 4
2879 ; RV64I-NEXT: vadd.vv v8, v8, v9
2880 ; RV64I-NEXT: lui a0, 61681
2881 ; RV64I-NEXT: addiw a0, a0, -241
2882 ; RV64I-NEXT: slli a1, a0, 32
2883 ; RV64I-NEXT: add a0, a0, a1
2884 ; RV64I-NEXT: vand.vx v8, v8, a0
2885 ; RV64I-NEXT: lui a0, 4112
2886 ; RV64I-NEXT: addiw a0, a0, 257
2887 ; RV64I-NEXT: slli a1, a0, 32
2888 ; RV64I-NEXT: add a0, a0, a1
2889 ; RV64I-NEXT: vmul.vx v8, v8, a0
2890 ; RV64I-NEXT: li a0, 56
2891 ; RV64I-NEXT: vsrl.vx v8, v8, a0
2892 ; RV64I-NEXT: ret
2893 ;
2894 ; CHECK-F-LABEL: cttz_zero_undef_nxv1i64:
2895 ; CHECK-F: # %bb.0:
2896 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2897 ; CHECK-F-NEXT: vrsub.vi v9, v8, 0
2898 ; CHECK-F-NEXT: vand.vv v8, v8, v9
2899 ; CHECK-F-NEXT: fsrmi a0, 1
2900 ; CHECK-F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
2901 ; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8
2902 ; CHECK-F-NEXT: vsrl.vi v8, v9, 23
2903 ; CHECK-F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
2904 ; CHECK-F-NEXT: vzext.vf2 v9, v8
2905 ; CHECK-F-NEXT: li a1, 127
2906 ; CHECK-F-NEXT: vsub.vx v8, v9, a1
2907 ; CHECK-F-NEXT: fsrm a0
2908 ; CHECK-F-NEXT: ret
2909 ;
2910 ; CHECK-D-LABEL: cttz_zero_undef_nxv1i64:
2911 ; CHECK-D: # %bb.0:
2912 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2913 ; CHECK-D-NEXT: vrsub.vi v9, v8, 0
2914 ; CHECK-D-NEXT: vand.vv v8, v8, v9
2915 ; CHECK-D-NEXT: fsrmi a0, 1
2916 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
2917 ; CHECK-D-NEXT: li a1, 52
2918 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
2919 ; CHECK-D-NEXT: li a1, 1023
2920 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
2921 ; CHECK-D-NEXT: fsrm a0
2922 ; CHECK-D-NEXT: ret
2923 ;
2924 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv1i64:
2925 ; CHECK-ZVBB: # %bb.0:
2926 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
2927 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
2928 ; CHECK-ZVBB-NEXT: ret
2929 %a = call <vscale x 1 x i64> @llvm.cttz.nxv1i64(<vscale x 1 x i64> %va, i1 true)
2930 ret <vscale x 1 x i64> %a
2931 }
2933 define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
2934 ; RV32I-LABEL: cttz_zero_undef_nxv2i64:
2935 ; RV32I: # %bb.0:
2936 ; RV32I-NEXT: li a0, 1
2937 ; RV32I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
2938 ; RV32I-NEXT: vsub.vx v10, v8, a0
2939 ; RV32I-NEXT: vnot.v v8, v8
2940 ; RV32I-NEXT: vand.vv v8, v8, v10
2941 ; RV32I-NEXT: vsrl.vi v10, v8, 1
2942 ; RV32I-NEXT: lui a0, 349525
2943 ; RV32I-NEXT: addi a0, a0, 1365
2944 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2945 ; RV32I-NEXT: vmv.v.x v12, a0
2946 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2947 ; RV32I-NEXT: vand.vv v10, v10, v12
2948 ; RV32I-NEXT: vsub.vv v8, v8, v10
2949 ; RV32I-NEXT: lui a0, 209715
2950 ; RV32I-NEXT: addi a0, a0, 819
2951 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2952 ; RV32I-NEXT: vmv.v.x v10, a0
2953 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2954 ; RV32I-NEXT: vand.vv v12, v8, v10
2955 ; RV32I-NEXT: vsrl.vi v8, v8, 2
2956 ; RV32I-NEXT: vand.vv v8, v8, v10
2957 ; RV32I-NEXT: vadd.vv v8, v12, v8
2958 ; RV32I-NEXT: vsrl.vi v10, v8, 4
2959 ; RV32I-NEXT: vadd.vv v8, v8, v10
2960 ; RV32I-NEXT: lui a0, 61681
2961 ; RV32I-NEXT: addi a0, a0, -241
2962 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2963 ; RV32I-NEXT: vmv.v.x v10, a0
2964 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2965 ; RV32I-NEXT: vand.vv v8, v8, v10
2966 ; RV32I-NEXT: lui a0, 4112
2967 ; RV32I-NEXT: addi a0, a0, 257
2968 ; RV32I-NEXT: vsetvli a1, zero, e32, m2, ta, ma
2969 ; RV32I-NEXT: vmv.v.x v10, a0
2970 ; RV32I-NEXT: vsetvli a0, zero, e64, m2, ta, ma
2971 ; RV32I-NEXT: vmul.vv v8, v8, v10
2972 ; RV32I-NEXT: li a0, 56
2973 ; RV32I-NEXT: vsrl.vx v8, v8, a0
2974 ; RV32I-NEXT: ret
2975 ;
2976 ; RV64I-LABEL: cttz_zero_undef_nxv2i64:
2977 ; RV64I: # %bb.0:
2978 ; RV64I-NEXT: li a0, 1
2979 ; RV64I-NEXT: vsetvli a1, zero, e64, m2, ta, ma
2980 ; RV64I-NEXT: vsub.vx v10, v8, a0
2981 ; RV64I-NEXT: vnot.v v8, v8
2982 ; RV64I-NEXT: vand.vv v8, v8, v10
2983 ; RV64I-NEXT: vsrl.vi v10, v8, 1
2984 ; RV64I-NEXT: lui a0, 349525
2985 ; RV64I-NEXT: addiw a0, a0, 1365
2986 ; RV64I-NEXT: slli a1, a0, 32
2987 ; RV64I-NEXT: add a0, a0, a1
2988 ; RV64I-NEXT: vand.vx v10, v10, a0
2989 ; RV64I-NEXT: vsub.vv v8, v8, v10
2990 ; RV64I-NEXT: lui a0, 209715
2991 ; RV64I-NEXT: addiw a0, a0, 819
2992 ; RV64I-NEXT: slli a1, a0, 32
2993 ; RV64I-NEXT: add a0, a0, a1
2994 ; RV64I-NEXT: vand.vx v10, v8, a0
2995 ; RV64I-NEXT: vsrl.vi v8, v8, 2
2996 ; RV64I-NEXT: vand.vx v8, v8, a0
2997 ; RV64I-NEXT: vadd.vv v8, v10, v8
2998 ; RV64I-NEXT: vsrl.vi v10, v8, 4
2999 ; RV64I-NEXT: vadd.vv v8, v8, v10
3000 ; RV64I-NEXT: lui a0, 61681
3001 ; RV64I-NEXT: addiw a0, a0, -241
3002 ; RV64I-NEXT: slli a1, a0, 32
3003 ; RV64I-NEXT: add a0, a0, a1
3004 ; RV64I-NEXT: vand.vx v8, v8, a0
3005 ; RV64I-NEXT: lui a0, 4112
3006 ; RV64I-NEXT: addiw a0, a0, 257
3007 ; RV64I-NEXT: slli a1, a0, 32
3008 ; RV64I-NEXT: add a0, a0, a1
3009 ; RV64I-NEXT: vmul.vx v8, v8, a0
3010 ; RV64I-NEXT: li a0, 56
3011 ; RV64I-NEXT: vsrl.vx v8, v8, a0
3012 ; RV64I-NEXT: ret
3013 ;
3014 ; CHECK-F-LABEL: cttz_zero_undef_nxv2i64:
3015 ; CHECK-F: # %bb.0:
3016 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
3017 ; CHECK-F-NEXT: vrsub.vi v10, v8, 0
3018 ; CHECK-F-NEXT: vand.vv v8, v8, v10
3019 ; CHECK-F-NEXT: fsrmi a0, 1
3020 ; CHECK-F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
3021 ; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8
3022 ; CHECK-F-NEXT: vsrl.vi v8, v10, 23
3023 ; CHECK-F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
3024 ; CHECK-F-NEXT: vzext.vf2 v10, v8
3025 ; CHECK-F-NEXT: li a1, 127
3026 ; CHECK-F-NEXT: vsub.vx v8, v10, a1
3027 ; CHECK-F-NEXT: fsrm a0
3028 ; CHECK-F-NEXT: ret
3029 ;
3030 ; CHECK-D-LABEL: cttz_zero_undef_nxv2i64:
3031 ; CHECK-D: # %bb.0:
3032 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
3033 ; CHECK-D-NEXT: vrsub.vi v10, v8, 0
3034 ; CHECK-D-NEXT: vand.vv v8, v8, v10
3035 ; CHECK-D-NEXT: fsrmi a0, 1
3036 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
3037 ; CHECK-D-NEXT: li a1, 52
3038 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
3039 ; CHECK-D-NEXT: li a1, 1023
3040 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
3041 ; CHECK-D-NEXT: fsrm a0
3042 ; CHECK-D-NEXT: ret
3043 ;
3044 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv2i64:
3045 ; CHECK-ZVBB: # %bb.0:
3046 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
3047 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3048 ; CHECK-ZVBB-NEXT: ret
3049 %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 true)
3050 ret <vscale x 2 x i64> %a
3051 }
3053 define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
3054 ; RV32I-LABEL: cttz_zero_undef_nxv4i64:
3055 ; RV32I: # %bb.0:
3056 ; RV32I-NEXT: li a0, 1
3057 ; RV32I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
3058 ; RV32I-NEXT: vsub.vx v12, v8, a0
3059 ; RV32I-NEXT: vnot.v v8, v8
3060 ; RV32I-NEXT: vand.vv v8, v8, v12
3061 ; RV32I-NEXT: vsrl.vi v12, v8, 1
3062 ; RV32I-NEXT: lui a0, 349525
3063 ; RV32I-NEXT: addi a0, a0, 1365
3064 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
3065 ; RV32I-NEXT: vmv.v.x v16, a0
3066 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3067 ; RV32I-NEXT: vand.vv v12, v12, v16
3068 ; RV32I-NEXT: vsub.vv v8, v8, v12
3069 ; RV32I-NEXT: lui a0, 209715
3070 ; RV32I-NEXT: addi a0, a0, 819
3071 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
3072 ; RV32I-NEXT: vmv.v.x v12, a0
3073 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3074 ; RV32I-NEXT: vand.vv v16, v8, v12
3075 ; RV32I-NEXT: vsrl.vi v8, v8, 2
3076 ; RV32I-NEXT: vand.vv v8, v8, v12
3077 ; RV32I-NEXT: vadd.vv v8, v16, v8
3078 ; RV32I-NEXT: vsrl.vi v12, v8, 4
3079 ; RV32I-NEXT: vadd.vv v8, v8, v12
3080 ; RV32I-NEXT: lui a0, 61681
3081 ; RV32I-NEXT: addi a0, a0, -241
3082 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
3083 ; RV32I-NEXT: vmv.v.x v12, a0
3084 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3085 ; RV32I-NEXT: vand.vv v8, v8, v12
3086 ; RV32I-NEXT: lui a0, 4112
3087 ; RV32I-NEXT: addi a0, a0, 257
3088 ; RV32I-NEXT: vsetvli a1, zero, e32, m4, ta, ma
3089 ; RV32I-NEXT: vmv.v.x v12, a0
3090 ; RV32I-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3091 ; RV32I-NEXT: vmul.vv v8, v8, v12
3092 ; RV32I-NEXT: li a0, 56
3093 ; RV32I-NEXT: vsrl.vx v8, v8, a0
3094 ; RV32I-NEXT: ret
3095 ;
3096 ; RV64I-LABEL: cttz_zero_undef_nxv4i64:
3097 ; RV64I: # %bb.0:
3098 ; RV64I-NEXT: li a0, 1
3099 ; RV64I-NEXT: vsetvli a1, zero, e64, m4, ta, ma
3100 ; RV64I-NEXT: vsub.vx v12, v8, a0
3101 ; RV64I-NEXT: vnot.v v8, v8
3102 ; RV64I-NEXT: vand.vv v8, v8, v12
3103 ; RV64I-NEXT: vsrl.vi v12, v8, 1
3104 ; RV64I-NEXT: lui a0, 349525
3105 ; RV64I-NEXT: addiw a0, a0, 1365
3106 ; RV64I-NEXT: slli a1, a0, 32
3107 ; RV64I-NEXT: add a0, a0, a1
3108 ; RV64I-NEXT: vand.vx v12, v12, a0
3109 ; RV64I-NEXT: vsub.vv v8, v8, v12
3110 ; RV64I-NEXT: lui a0, 209715
3111 ; RV64I-NEXT: addiw a0, a0, 819
3112 ; RV64I-NEXT: slli a1, a0, 32
3113 ; RV64I-NEXT: add a0, a0, a1
3114 ; RV64I-NEXT: vand.vx v12, v8, a0
3115 ; RV64I-NEXT: vsrl.vi v8, v8, 2
3116 ; RV64I-NEXT: vand.vx v8, v8, a0
3117 ; RV64I-NEXT: vadd.vv v8, v12, v8
3118 ; RV64I-NEXT: vsrl.vi v12, v8, 4
3119 ; RV64I-NEXT: vadd.vv v8, v8, v12
3120 ; RV64I-NEXT: lui a0, 61681
3121 ; RV64I-NEXT: addiw a0, a0, -241
3122 ; RV64I-NEXT: slli a1, a0, 32
3123 ; RV64I-NEXT: add a0, a0, a1
3124 ; RV64I-NEXT: vand.vx v8, v8, a0
3125 ; RV64I-NEXT: lui a0, 4112
3126 ; RV64I-NEXT: addiw a0, a0, 257
3127 ; RV64I-NEXT: slli a1, a0, 32
3128 ; RV64I-NEXT: add a0, a0, a1
3129 ; RV64I-NEXT: vmul.vx v8, v8, a0
3130 ; RV64I-NEXT: li a0, 56
3131 ; RV64I-NEXT: vsrl.vx v8, v8, a0
3132 ; RV64I-NEXT: ret
3133 ;
3134 ; CHECK-F-LABEL: cttz_zero_undef_nxv4i64:
3135 ; CHECK-F: # %bb.0:
3136 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3137 ; CHECK-F-NEXT: vrsub.vi v12, v8, 0
3138 ; CHECK-F-NEXT: vand.vv v8, v8, v12
3139 ; CHECK-F-NEXT: fsrmi a0, 1
3140 ; CHECK-F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
3141 ; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8
3142 ; CHECK-F-NEXT: vsrl.vi v8, v12, 23
3143 ; CHECK-F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
3144 ; CHECK-F-NEXT: vzext.vf2 v12, v8
3145 ; CHECK-F-NEXT: li a1, 127
3146 ; CHECK-F-NEXT: vsub.vx v8, v12, a1
3147 ; CHECK-F-NEXT: fsrm a0
3148 ; CHECK-F-NEXT: ret
3149 ;
3150 ; CHECK-D-LABEL: cttz_zero_undef_nxv4i64:
3151 ; CHECK-D: # %bb.0:
3152 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3153 ; CHECK-D-NEXT: vrsub.vi v12, v8, 0
3154 ; CHECK-D-NEXT: vand.vv v8, v8, v12
3155 ; CHECK-D-NEXT: fsrmi a0, 1
3156 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
3157 ; CHECK-D-NEXT: li a1, 52
3158 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
3159 ; CHECK-D-NEXT: li a1, 1023
3160 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
3161 ; CHECK-D-NEXT: fsrm a0
3162 ; CHECK-D-NEXT: ret
3163 ;
3164 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv4i64:
3165 ; CHECK-ZVBB: # %bb.0:
3166 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
3167 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3168 ; CHECK-ZVBB-NEXT: ret
3169 %a = call <vscale x 4 x i64> @llvm.cttz.nxv4i64(<vscale x 4 x i64> %va, i1 true)
3170 ret <vscale x 4 x i64> %a
3171 }
3173 define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
3174 ; RV32I-LABEL: cttz_zero_undef_nxv8i64:
3175 ; RV32I: # %bb.0:
3176 ; RV32I-NEXT: li a0, 1
3177 ; RV32I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
3178 ; RV32I-NEXT: vsub.vx v16, v8, a0
3179 ; RV32I-NEXT: vnot.v v8, v8
3180 ; RV32I-NEXT: vand.vv v8, v8, v16
3181 ; RV32I-NEXT: vsrl.vi v16, v8, 1
3182 ; RV32I-NEXT: lui a0, 349525
3183 ; RV32I-NEXT: addi a0, a0, 1365
3184 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3185 ; RV32I-NEXT: vmv.v.x v24, a0
3186 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3187 ; RV32I-NEXT: vand.vv v16, v16, v24
3188 ; RV32I-NEXT: vsub.vv v8, v8, v16
3189 ; RV32I-NEXT: lui a0, 209715
3190 ; RV32I-NEXT: addi a0, a0, 819
3191 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3192 ; RV32I-NEXT: vmv.v.x v16, a0
3193 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3194 ; RV32I-NEXT: vand.vv v24, v8, v16
3195 ; RV32I-NEXT: vsrl.vi v8, v8, 2
3196 ; RV32I-NEXT: vand.vv v8, v8, v16
3197 ; RV32I-NEXT: vadd.vv v8, v24, v8
3198 ; RV32I-NEXT: vsrl.vi v16, v8, 4
3199 ; RV32I-NEXT: vadd.vv v8, v8, v16
3200 ; RV32I-NEXT: lui a0, 61681
3201 ; RV32I-NEXT: addi a0, a0, -241
3202 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3203 ; RV32I-NEXT: vmv.v.x v16, a0
3204 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3205 ; RV32I-NEXT: vand.vv v8, v8, v16
3206 ; RV32I-NEXT: lui a0, 4112
3207 ; RV32I-NEXT: addi a0, a0, 257
3208 ; RV32I-NEXT: vsetvli a1, zero, e32, m8, ta, ma
3209 ; RV32I-NEXT: vmv.v.x v16, a0
3210 ; RV32I-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3211 ; RV32I-NEXT: vmul.vv v8, v8, v16
3212 ; RV32I-NEXT: li a0, 56
3213 ; RV32I-NEXT: vsrl.vx v8, v8, a0
3214 ; RV32I-NEXT: ret
3215 ;
3216 ; RV64I-LABEL: cttz_zero_undef_nxv8i64:
3217 ; RV64I: # %bb.0:
3218 ; RV64I-NEXT: li a0, 1
3219 ; RV64I-NEXT: vsetvli a1, zero, e64, m8, ta, ma
3220 ; RV64I-NEXT: vsub.vx v16, v8, a0
3221 ; RV64I-NEXT: vnot.v v8, v8
3222 ; RV64I-NEXT: vand.vv v8, v8, v16
3223 ; RV64I-NEXT: vsrl.vi v16, v8, 1
3224 ; RV64I-NEXT: lui a0, 349525
3225 ; RV64I-NEXT: addiw a0, a0, 1365
3226 ; RV64I-NEXT: slli a1, a0, 32
3227 ; RV64I-NEXT: add a0, a0, a1
3228 ; RV64I-NEXT: vand.vx v16, v16, a0
3229 ; RV64I-NEXT: vsub.vv v8, v8, v16
3230 ; RV64I-NEXT: lui a0, 209715
3231 ; RV64I-NEXT: addiw a0, a0, 819
3232 ; RV64I-NEXT: slli a1, a0, 32
3233 ; RV64I-NEXT: add a0, a0, a1
3234 ; RV64I-NEXT: vand.vx v16, v8, a0
3235 ; RV64I-NEXT: vsrl.vi v8, v8, 2
3236 ; RV64I-NEXT: vand.vx v8, v8, a0
3237 ; RV64I-NEXT: vadd.vv v8, v16, v8
3238 ; RV64I-NEXT: vsrl.vi v16, v8, 4
3239 ; RV64I-NEXT: vadd.vv v8, v8, v16
3240 ; RV64I-NEXT: lui a0, 61681
3241 ; RV64I-NEXT: addiw a0, a0, -241
3242 ; RV64I-NEXT: slli a1, a0, 32
3243 ; RV64I-NEXT: add a0, a0, a1
3244 ; RV64I-NEXT: vand.vx v8, v8, a0
3245 ; RV64I-NEXT: lui a0, 4112
3246 ; RV64I-NEXT: addiw a0, a0, 257
3247 ; RV64I-NEXT: slli a1, a0, 32
3248 ; RV64I-NEXT: add a0, a0, a1
3249 ; RV64I-NEXT: vmul.vx v8, v8, a0
3250 ; RV64I-NEXT: li a0, 56
3251 ; RV64I-NEXT: vsrl.vx v8, v8, a0
3252 ; RV64I-NEXT: ret
3253 ;
3254 ; CHECK-F-LABEL: cttz_zero_undef_nxv8i64:
3255 ; CHECK-F: # %bb.0:
3256 ; CHECK-F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3257 ; CHECK-F-NEXT: vrsub.vi v16, v8, 0
3258 ; CHECK-F-NEXT: vand.vv v8, v8, v16
3259 ; CHECK-F-NEXT: fsrmi a0, 1
3260 ; CHECK-F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
3261 ; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8
3262 ; CHECK-F-NEXT: vsrl.vi v8, v16, 23
3263 ; CHECK-F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
3264 ; CHECK-F-NEXT: vzext.vf2 v16, v8
3265 ; CHECK-F-NEXT: li a1, 127
3266 ; CHECK-F-NEXT: vsub.vx v8, v16, a1
3267 ; CHECK-F-NEXT: fsrm a0
3268 ; CHECK-F-NEXT: ret
3269 ;
3270 ; CHECK-D-LABEL: cttz_zero_undef_nxv8i64:
3271 ; CHECK-D: # %bb.0:
3272 ; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3273 ; CHECK-D-NEXT: vrsub.vi v16, v8, 0
3274 ; CHECK-D-NEXT: vand.vv v8, v8, v16
3275 ; CHECK-D-NEXT: fsrmi a0, 1
3276 ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
3277 ; CHECK-D-NEXT: li a1, 52
3278 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1
3279 ; CHECK-D-NEXT: li a1, 1023
3280 ; CHECK-D-NEXT: vsub.vx v8, v8, a1
3281 ; CHECK-D-NEXT: fsrm a0
3282 ; CHECK-D-NEXT: ret
3283 ;
3284 ; CHECK-ZVBB-LABEL: cttz_zero_undef_nxv8i64:
3285 ; CHECK-ZVBB: # %bb.0:
3286 ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
3287 ; CHECK-ZVBB-NEXT: vctz.v v8, v8
3288 ; CHECK-ZVBB-NEXT: ret
3289 %a = call <vscale x 8 x i64> @llvm.cttz.nxv8i64(<vscale x 8 x i64> %va, i1 true)
3290 ret <vscale x 8 x i64> %a
3291 }
3292 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
3293 ; RV32: {{.*}}
3294 ; RV64: {{.*}}