| blob | a1c36db5cfc318e9d799b9b1f8f845e3eb12aaf7 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
3 ; RUN: -verify-machineinstrs < %s | FileCheck %s
4 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
5 ; RUN: -verify-machineinstrs < %s | FileCheck %s
7 define <2 x i1> @isnan_v2f16(<2 x half> %x) {
8 ; CHECK-LABEL: isnan_v2f16:
9 ; CHECK: # %bb.0:
10 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
11 ; CHECK-NEXT: vfclass.v v8, v8
12 ; CHECK-NEXT: li a0, 768
13 ; CHECK-NEXT: vand.vx v8, v8, a0
14 ; CHECK-NEXT: vmsne.vi v0, v8, 0
15 ; CHECK-NEXT: ret
16 %1 = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 3) ; nan
17 ret <2 x i1> %1
18 }
20 define <2 x i1> @isnan_v2f32(<2 x float> %x) {
21 ; CHECK-LABEL: isnan_v2f32:
22 ; CHECK: # %bb.0:
23 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
24 ; CHECK-NEXT: vfclass.v v8, v8
25 ; CHECK-NEXT: li a0, 927
26 ; CHECK-NEXT: vand.vx v8, v8, a0
27 ; CHECK-NEXT: vmsne.vi v0, v8, 0
28 ; CHECK-NEXT: ret
29 %1 = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 639)
30 ret <2 x i1> %1
31 }
34 define <4 x i1> @isnan_v4f32(<4 x float> %x) {
35 ; CHECK-LABEL: isnan_v4f32:
36 ; CHECK: # %bb.0:
37 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
38 ; CHECK-NEXT: vfclass.v v8, v8
39 ; CHECK-NEXT: li a0, 768
40 ; CHECK-NEXT: vand.vx v8, v8, a0
41 ; CHECK-NEXT: vmsne.vi v0, v8, 0
42 ; CHECK-NEXT: ret
43 %1 = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 3) ; nan
44 ret <4 x i1> %1
45 }
47 define <8 x i1> @isnan_v8f32(<8 x float> %x) {
48 ; CHECK-LABEL: isnan_v8f32:
49 ; CHECK: # %bb.0:
50 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
51 ; CHECK-NEXT: vfclass.v v8, v8
52 ; CHECK-NEXT: li a0, 512
53 ; CHECK-NEXT: vmseq.vx v0, v8, a0
54 ; CHECK-NEXT: ret
55 %1 = call <8 x i1> @llvm.is.fpclass.v8f32(<8 x float> %x, i32 2)
56 ret <8 x i1> %1
57 }
59 define <16 x i1> @isnan_v16f32(<16 x float> %x) {
60 ; CHECK-LABEL: isnan_v16f32:
61 ; CHECK: # %bb.0:
62 ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
63 ; CHECK-NEXT: vfclass.v v8, v8
64 ; CHECK-NEXT: li a0, 256
65 ; CHECK-NEXT: vmseq.vx v0, v8, a0
66 ; CHECK-NEXT: ret
67 %1 = call <16 x i1> @llvm.is.fpclass.v16f32(<16 x float> %x, i32 1)
68 ret <16 x i1> %1
69 }
71 define <2 x i1> @isnormal_v2f64(<2 x double> %x) {
72 ; CHECK-LABEL: isnormal_v2f64:
73 ; CHECK: # %bb.0:
74 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
75 ; CHECK-NEXT: vfclass.v v8, v8
76 ; CHECK-NEXT: li a0, 129
77 ; CHECK-NEXT: vand.vx v8, v8, a0
78 ; CHECK-NEXT: vmsne.vi v0, v8, 0
79 ; CHECK-NEXT: ret
80 %1 = call <2 x i1> @llvm.is.fpclass.v2f64(<2 x double> %x, i32 516) ; 0x204 = "inf"
81 ret <2 x i1> %1
82 }
84 define <4 x i1> @isposinf_v4f64(<4 x double> %x) {
85 ; CHECK-LABEL: isposinf_v4f64:
86 ; CHECK: # %bb.0:
87 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
88 ; CHECK-NEXT: vfclass.v v8, v8
89 ; CHECK-NEXT: li a0, 128
90 ; CHECK-NEXT: vmseq.vx v0, v8, a0
91 ; CHECK-NEXT: ret
92 %1 = call <4 x i1> @llvm.is.fpclass.v4f64(<4 x double> %x, i32 512) ; 0x200 = "+inf"
93 ret <4 x i1> %1
94 }
96 define <8 x i1> @isneginf_v8f64(<8 x double> %x) {
97 ; CHECK-LABEL: isneginf_v8f64:
98 ; CHECK: # %bb.0:
99 ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
100 ; CHECK-NEXT: vfclass.v v8, v8
101 ; CHECK-NEXT: vmseq.vi v0, v8, 1
102 ; CHECK-NEXT: ret
103 %1 = call <8 x i1> @llvm.is.fpclass.v8f64(<8 x double> %x, i32 4) ; "-inf"
104 ret <8 x i1> %1
105 }
107 define <16 x i1> @isfinite_v16f64(<16 x double> %x) {
108 ; CHECK-LABEL: isfinite_v16f64:
109 ; CHECK: # %bb.0:
110 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
111 ; CHECK-NEXT: vfclass.v v8, v8
112 ; CHECK-NEXT: li a0, 126
113 ; CHECK-NEXT: vand.vx v8, v8, a0
114 ; CHECK-NEXT: vmsne.vi v0, v8, 0
115 ; CHECK-NEXT: ret
116 %1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 504) ; 0x1f8 = "finite"
117 ret <16 x i1> %1
118 }
120 define <16 x i1> @isposfinite_v16f64(<16 x double> %x) {
121 ; CHECK-LABEL: isposfinite_v16f64:
122 ; CHECK: # %bb.0:
123 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
124 ; CHECK-NEXT: vfclass.v v8, v8
125 ; CHECK-NEXT: li a0, 112
126 ; CHECK-NEXT: vand.vx v8, v8, a0
127 ; CHECK-NEXT: vmsne.vi v0, v8, 0
128 ; CHECK-NEXT: ret
129 %1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 448) ; 0x1c0 = "+finite"
130 ret <16 x i1> %1
131 }
133 define <16 x i1> @isnegfinite_v16f64(<16 x double> %x) {
134 ; CHECK-LABEL: isnegfinite_v16f64:
135 ; CHECK: # %bb.0:
136 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
137 ; CHECK-NEXT: vfclass.v v8, v8
138 ; CHECK-NEXT: vand.vi v8, v8, 14
139 ; CHECK-NEXT: vmsne.vi v0, v8, 0
140 ; CHECK-NEXT: ret
141 %1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 56) ; 0x38 = "-finite"
142 ret <16 x i1> %1
143 }
145 define <16 x i1> @isnotfinite_v16f64(<16 x double> %x) {
146 ; CHECK-LABEL: isnotfinite_v16f64:
147 ; CHECK: # %bb.0:
148 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
149 ; CHECK-NEXT: vfclass.v v8, v8
150 ; CHECK-NEXT: li a0, 897
151 ; CHECK-NEXT: vand.vx v8, v8, a0
152 ; CHECK-NEXT: vmsne.vi v0, v8, 0
153 ; CHECK-NEXT: ret
154 %1 = call <16 x i1> @llvm.is.fpclass.v16f64(<16 x double> %x, i32 519) ; 0x207 = "inf|nan"
155 ret <16 x i1> %1
156 }
158 declare <2 x i1> @llvm.is.fpclass.v2f16(<2 x half>, i32)
159 declare <2 x i1> @llvm.is.fpclass.v2f32(<2 x float>, i32)
160 declare <4 x i1> @llvm.is.fpclass.v4f32(<4 x float>, i32)
161 declare <8 x i1> @llvm.is.fpclass.v8f32(<8 x float>, i32)
162 declare <16 x i1> @llvm.is.fpclass.v16f32(<16 x float>, i32)
163 declare <2 x i1> @llvm.is.fpclass.v2f64(<2 x double>, i32)
164 declare <4 x i1> @llvm.is.fpclass.v4f64(<4 x double>, i32)
165 declare <8 x i1> @llvm.is.fpclass.v8f64(<8 x double>, i32)
166 declare <16 x i1> @llvm.is.fpclass.v16f64(<16 x double>, i32)