1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s
4 define <vscale x 1 x i8> @vpmerge_mf8(<vscale x 1 x i8> %x, <vscale x 1 x i8> %y, i32 zeroext %vl) {
5 ; CHECK-LABEL: vpmerge_mf8:
7 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
8 ; CHECK-NEXT: vmv.v.v v8, v9
10 %splat = insertelement <vscale x 1 x i1> poison, i1 -1, i8 0
11 %allones = shufflevector <vscale x 1 x i1> %splat, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer
12 %1 = call <vscale x 1 x i8> @llvm.vp.merge.nxv1i8(<vscale x 1 x i1> %allones, <vscale x 1 x i8> %y, <vscale x 1 x i8> %x, i32 %vl)
13 ret <vscale x 1 x i8> %1
16 define <vscale x 2 x i8> @vpmerge_mf4(<vscale x 2 x i8> %x, <vscale x 2 x i8> %y, i32 zeroext %vl) {
17 ; CHECK-LABEL: vpmerge_mf4:
19 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
20 ; CHECK-NEXT: vmv.v.v v8, v9
22 %splat = insertelement <vscale x 2 x i1> poison, i1 -1, i8 0
23 %allones = shufflevector <vscale x 2 x i1> %splat, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer
24 %1 = call <vscale x 2 x i8> @llvm.vp.merge.nxv2i8(<vscale x 2 x i1> %allones, <vscale x 2 x i8> %y, <vscale x 2 x i8> %x, i32 %vl)
25 ret <vscale x 2 x i8> %1
28 define <vscale x 4 x i8> @vpmerge_mf2(<vscale x 4 x i8> %x, <vscale x 4 x i8> %y, i32 zeroext %vl) {
29 ; CHECK-LABEL: vpmerge_mf2:
31 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
32 ; CHECK-NEXT: vmv.v.v v8, v9
34 %splat = insertelement <vscale x 4 x i1> poison, i1 -1, i8 0
35 %allones = shufflevector <vscale x 4 x i1> %splat, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
36 %1 = call <vscale x 4 x i8> @llvm.vp.merge.nxv4i8(<vscale x 4 x i1> %allones, <vscale x 4 x i8> %y, <vscale x 4 x i8> %x, i32 %vl)
37 ret <vscale x 4 x i8> %1
40 define <vscale x 8 x i8> @vpmerge_m1(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y, i32 zeroext %vl) {
41 ; CHECK-LABEL: vpmerge_m1:
43 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
44 ; CHECK-NEXT: vmv.v.v v8, v9
46 %splat = insertelement <vscale x 8 x i1> poison, i1 -1, i8 0
47 %allones = shufflevector <vscale x 8 x i1> %splat, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
48 %1 = call <vscale x 8 x i8> @llvm.vp.merge.nxv8i8(<vscale x 8 x i1> %allones, <vscale x 8 x i8> %y, <vscale x 8 x i8> %x, i32 %vl)
49 ret <vscale x 8 x i8> %1
52 define <vscale x 8 x i16> @vpmerge_m2(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, i32 zeroext %vl) {
53 ; CHECK-LABEL: vpmerge_m2:
55 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
56 ; CHECK-NEXT: vmv.v.v v8, v10
58 %splat = insertelement <vscale x 8 x i1> poison, i1 -1, i16 0
59 %allones = shufflevector <vscale x 8 x i1> %splat, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
60 %1 = call <vscale x 8 x i16> @llvm.vp.merge.nxv8i16(<vscale x 8 x i1> %allones, <vscale x 8 x i16> %y, <vscale x 8 x i16> %x, i32 %vl)
61 ret <vscale x 8 x i16> %1
64 define <vscale x 8 x i32> @vpmerge_m4(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, i32 zeroext %vl) {
65 ; CHECK-LABEL: vpmerge_m4:
67 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
68 ; CHECK-NEXT: vmv.v.v v8, v12
70 %splat = insertelement <vscale x 8 x i1> poison, i1 -1, i32 0
71 %allones = shufflevector <vscale x 8 x i1> %splat, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
72 %1 = call <vscale x 8 x i32> @llvm.vp.merge.nxv8i32(<vscale x 8 x i1> %allones, <vscale x 8 x i32> %y, <vscale x 8 x i32> %x, i32 %vl)
73 ret <vscale x 8 x i32> %1
76 define <vscale x 8 x i64> @vpmerge_m8(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y, i32 zeroext %vl) {
77 ; CHECK-LABEL: vpmerge_m8:
79 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
80 ; CHECK-NEXT: vmv.v.v v8, v16
82 %splat = insertelement <vscale x 8 x i1> poison, i1 -1, i64 0
83 %allones = shufflevector <vscale x 8 x i1> %splat, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer
84 %1 = call <vscale x 8 x i64> @llvm.vp.merge.nxv8i64(<vscale x 8 x i1> %allones, <vscale x 8 x i64> %y, <vscale x 8 x i64> %x, i32 %vl)
85 ret <vscale x 8 x i64> %1
88 declare <vscale x 1 x i8> @llvm.vp.merge.nxv1i8(<vscale x 1 x i1>, <vscale x 1 x i8>, <vscale x 1 x i8>, i32)
89 declare <vscale x 2 x i8> @llvm.vp.merge.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>, <vscale x 2 x i8>, i32)
90 declare <vscale x 4 x i8> @llvm.vp.merge.nxv4i8(<vscale x 4 x i1>, <vscale x 4 x i8>, <vscale x 4 x i8>, i32)
91 declare <vscale x 8 x i8> @llvm.vp.merge.nxv8i8(<vscale x 8 x i1>, <vscale x 8 x i8>, <vscale x 8 x i8>, i32)
92 declare <vscale x 8 x i16> @llvm.vp.merge.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, i32)
93 declare <vscale x 8 x i32> @llvm.vp.merge.nxv8i32(<vscale x 8 x i1>, <vscale x 8 x i32>, <vscale x 8 x i32>, i32)
94 declare <vscale x 8 x i64> @llvm.vp.merge.nxv8i64(<vscale x 8 x i1>, <vscale x 8 x i64>, <vscale x 8 x i64>, i32)