| blob | 115f3863afc312f4290ef24f45b416452b444253 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,CHECK-NOBMI,CHECK-NOBMI-SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2 | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-BMI2-SSE2
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2,+avx2 | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-AVX,CHECK-AVX2
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi2,+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK,CHECK-BMI2,CHECK-AVX,CHECK-AVX512
6 declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
7 declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
8 declare <16 x i16> @llvm.fshl.v16i16(<16 x i16>, <16 x i16>, <16 x i16>)
9 declare <16 x i16> @llvm.fshr.v16i16(<16 x i16>, <16 x i16>, <16 x i16>)
10 declare i64 @llvm.fshl.i64(i64, i64, i64)
11 declare i64 @llvm.fshr.i64(i64, i64, i64)
12 declare i32 @llvm.fshl.i32(i32, i32, i32)
13 declare i32 @llvm.fshr.i32(i32, i32, i32)
14 declare i16 @llvm.fshl.i16(i16, i16, i16)
15 declare i16 @llvm.fshr.i16(i16, i16, i16)
16 declare i8 @llvm.fshl.i8(i8, i8, i8)
17 declare i8 @llvm.fshr.i8(i8, i8, i8)
19 define i1 @shr_to_shl_eq_i8_s2(i8 %x) {
20 ; CHECK-LABEL: shr_to_shl_eq_i8_s2:
21 ; CHECK: # %bb.0:
22 ; CHECK-NEXT: movl %edi, %eax
23 ; CHECK-NEXT: rolb $2, %al
24 ; CHECK-NEXT: cmpb %al, %dil
25 ; CHECK-NEXT: sete %al
26 ; CHECK-NEXT: retq
27 %and = and i8 %x, 63
28 %shr = lshr i8 %x, 2
29 %r = icmp eq i8 %and, %shr
30 ret i1 %r
31 }
33 define i1 @shl_to_shr_ne_i8_s7(i8 %x) {
34 ; CHECK-LABEL: shl_to_shr_ne_i8_s7:
35 ; CHECK: # %bb.0:
36 ; CHECK-NEXT: movl %edi, %eax
37 ; CHECK-NEXT: shrb $7, %al
38 ; CHECK-NEXT: andb $1, %dil
39 ; CHECK-NEXT: cmpb %al, %dil
40 ; CHECK-NEXT: setne %al
41 ; CHECK-NEXT: retq
42 %shl = shl i8 %x, 7
43 %and = and i8 %x, 128
44 %r = icmp ne i8 %shl, %and
45 ret i1 %r
46 }
48 define i1 @rorl_to_srl_ne_i8_s5_fail(i8 %x) {
49 ; CHECK-LABEL: rorl_to_srl_ne_i8_s5_fail:
50 ; CHECK: # %bb.0:
51 ; CHECK-NEXT: movl %edi, %eax
52 ; CHECK-NEXT: rolb $5, %al
53 ; CHECK-NEXT: cmpb %dil, %al
54 ; CHECK-NEXT: setne %al
55 ; CHECK-NEXT: retq
56 %ror = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 5)
57 %r = icmp ne i8 %ror, %x
58 ret i1 %r
59 }
61 define i1 @shr_to_shl_eq_i8_s1(i8 %x) {
62 ; CHECK-LABEL: shr_to_shl_eq_i8_s1:
63 ; CHECK: # %bb.0:
64 ; CHECK-NEXT: movl %edi, %eax
65 ; CHECK-NEXT: rolb %al
66 ; CHECK-NEXT: cmpb %al, %dil
67 ; CHECK-NEXT: sete %al
68 ; CHECK-NEXT: retq
69 %and = and i8 %x, 127
70 %shr = lshr i8 %x, 1
71 %r = icmp eq i8 %and, %shr
72 ret i1 %r
73 }
75 define i1 @shr_to_shl_eq_i32_s3(i32 %x) {
76 ; CHECK-LABEL: shr_to_shl_eq_i32_s3:
77 ; CHECK: # %bb.0:
78 ; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
79 ; CHECK-NEXT: leal (,%rdi,8), %eax
80 ; CHECK-NEXT: andl $-8, %edi
81 ; CHECK-NEXT: cmpl %eax, %edi
82 ; CHECK-NEXT: sete %al
83 ; CHECK-NEXT: retq
84 %and = and i32 %x, 536870911
85 %shr = lshr i32 %x, 3
86 %r = icmp eq i32 %and, %shr
87 ret i1 %r
88 }
90 define i1 @shl_to_shr_eq_i32_s3_fail(i32 %x) {
91 ; CHECK-LABEL: shl_to_shr_eq_i32_s3_fail:
92 ; CHECK: # %bb.0:
93 ; CHECK-NEXT: movl %edi, %eax
94 ; CHECK-NEXT: andl $536870911, %eax # imm = 0x1FFFFFFF
95 ; CHECK-NEXT: shll $3, %edi
96 ; CHECK-NEXT: cmpl %edi, %eax
97 ; CHECK-NEXT: sete %al
98 ; CHECK-NEXT: retq
99 %and = and i32 %x, 536870911
100 %shr = shl i32 %x, 3
101 %r = icmp eq i32 %and, %shr
102 ret i1 %r
103 }
105 define i1 @shl_to_shr_ne_i32_s16(i32 %x) {
106 ; CHECK-NOBMI-LABEL: shl_to_shr_ne_i32_s16:
107 ; CHECK-NOBMI: # %bb.0:
108 ; CHECK-NOBMI-NEXT: movzwl %di, %eax
109 ; CHECK-NOBMI-NEXT: shrl $16, %edi
110 ; CHECK-NOBMI-NEXT: cmpl %edi, %eax
111 ; CHECK-NOBMI-NEXT: setne %al
112 ; CHECK-NOBMI-NEXT: retq
113 ;
114 ; CHECK-BMI2-LABEL: shl_to_shr_ne_i32_s16:
115 ; CHECK-BMI2: # %bb.0:
116 ; CHECK-BMI2-NEXT: rorxl $16, %edi, %eax
117 ; CHECK-BMI2-NEXT: cmpl %eax, %edi
118 ; CHECK-BMI2-NEXT: setne %al
119 ; CHECK-BMI2-NEXT: retq
120 %shl = shl i32 %x, 16
121 %and = and i32 %x, 4294901760
122 %r = icmp ne i32 %shl, %and
123 ret i1 %r
124 }
126 define i1 @shl_to_shr_ne_i32_s16_fail(i32 %x) {
127 ; CHECK-LABEL: shl_to_shr_ne_i32_s16_fail:
128 ; CHECK: # %bb.0:
129 ; CHECK-NEXT: movl %edi, %eax
130 ; CHECK-NEXT: shll $16, %eax
131 ; CHECK-NEXT: andl $2147450880, %edi # imm = 0x7FFF8000
132 ; CHECK-NEXT: cmpl %edi, %eax
133 ; CHECK-NEXT: setne %al
134 ; CHECK-NEXT: retq
135 %shl = shl i32 %x, 16
136 %and = and i32 %x, 2147450880
137 %r = icmp ne i32 %shl, %and
138 ret i1 %r
139 }
141 define i1 @shr_to_shl_eq_i16_s1(i16 %x) {
142 ; CHECK-LABEL: shr_to_shl_eq_i16_s1:
143 ; CHECK: # %bb.0:
144 ; CHECK-NEXT: movl %edi, %eax
145 ; CHECK-NEXT: rolw %ax
146 ; CHECK-NEXT: cmpw %ax, %di
147 ; CHECK-NEXT: sete %al
148 ; CHECK-NEXT: retq
149 %and = and i16 %x, 32767
150 %shr = lshr i16 %x, 1
151 %r = icmp eq i16 %and, %shr
152 ret i1 %r
153 }
155 define i1 @shr_to_shl_eq_i16_s1_fail(i16 %x) {
156 ; CHECK-LABEL: shr_to_shl_eq_i16_s1_fail:
157 ; CHECK: # %bb.0:
158 ; CHECK-NEXT: movzwl %di, %eax
159 ; CHECK-NEXT: andl $32766, %edi # imm = 0x7FFE
160 ; CHECK-NEXT: shrl %eax
161 ; CHECK-NEXT: cmpw %ax, %di
162 ; CHECK-NEXT: sete %al
163 ; CHECK-NEXT: retq
164 %and = and i16 %x, 32766
165 %shr = lshr i16 %x, 1
166 %r = icmp eq i16 %and, %shr
167 ret i1 %r
168 }
170 define i1 @shl_to_shr_eq_i64_s44(i64 %x) {
171 ; CHECK-LABEL: shl_to_shr_eq_i64_s44:
172 ; CHECK: # %bb.0:
173 ; CHECK-NEXT: movq %rdi, %rax
174 ; CHECK-NEXT: shrq $44, %rax
175 ; CHECK-NEXT: andl $1048575, %edi # imm = 0xFFFFF
176 ; CHECK-NEXT: cmpq %rax, %rdi
177 ; CHECK-NEXT: sete %al
178 ; CHECK-NEXT: retq
179 %shl = shl i64 %x, 44
180 %and = and i64 %x, 18446726481523507200
181 %r = icmp eq i64 %shl, %and
182 ret i1 %r
183 }
185 define i1 @shr_to_shl_ne_i64_s32(i64 %x) {
186 ; CHECK-NOBMI-LABEL: shr_to_shl_ne_i64_s32:
187 ; CHECK-NOBMI: # %bb.0:
188 ; CHECK-NOBMI-NEXT: movl %edi, %eax
189 ; CHECK-NOBMI-NEXT: shrq $32, %rdi
190 ; CHECK-NOBMI-NEXT: cmpq %rdi, %rax
191 ; CHECK-NOBMI-NEXT: setne %al
192 ; CHECK-NOBMI-NEXT: retq
193 ;
194 ; CHECK-BMI2-LABEL: shr_to_shl_ne_i64_s32:
195 ; CHECK-BMI2: # %bb.0:
196 ; CHECK-BMI2-NEXT: rorxq $32, %rdi, %rax
197 ; CHECK-BMI2-NEXT: cmpq %rax, %rdi
198 ; CHECK-BMI2-NEXT: setne %al
199 ; CHECK-BMI2-NEXT: retq
200 %and = and i64 %x, 4294967295
201 %shr = lshr i64 %x, 32
202 %r = icmp ne i64 %and, %shr
203 ret i1 %r
204 }
206 define i1 @rorl_to_shl_eq_i64_s16(i64 %x) {
207 ; CHECK-NOBMI-LABEL: rorl_to_shl_eq_i64_s16:
208 ; CHECK-NOBMI: # %bb.0:
209 ; CHECK-NOBMI-NEXT: movq %rdi, %rax
210 ; CHECK-NOBMI-NEXT: rolq $16, %rax
211 ; CHECK-NOBMI-NEXT: cmpq %rdi, %rax
212 ; CHECK-NOBMI-NEXT: sete %al
213 ; CHECK-NOBMI-NEXT: retq
214 ;
215 ; CHECK-BMI2-LABEL: rorl_to_shl_eq_i64_s16:
216 ; CHECK-BMI2: # %bb.0:
217 ; CHECK-BMI2-NEXT: rorxq $48, %rdi, %rax
218 ; CHECK-BMI2-NEXT: cmpq %rdi, %rax
219 ; CHECK-BMI2-NEXT: sete %al
220 ; CHECK-BMI2-NEXT: retq
221 %ror = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 16)
222 %r = icmp eq i64 %ror, %x
223 ret i1 %r
224 }
226 define i1 @ashr_to_shl_ne_i64_s32_fail(i64 %x) {
227 ; CHECK-LABEL: ashr_to_shl_ne_i64_s32_fail:
228 ; CHECK: # %bb.0:
229 ; CHECK-NEXT: movl %edi, %eax
230 ; CHECK-NEXT: sarq $32, %rdi
231 ; CHECK-NEXT: cmpq %rdi, %rax
232 ; CHECK-NEXT: setne %al
233 ; CHECK-NEXT: retq
234 %and = and i64 %x, 4294967295
235 %shr = ashr i64 %x, 32
236 %r = icmp ne i64 %and, %shr
237 ret i1 %r
238 }
240 define i1 @shl_to_shr_eq_i64_s63(i64 %x) {
241 ; CHECK-LABEL: shl_to_shr_eq_i64_s63:
242 ; CHECK: # %bb.0:
243 ; CHECK-NEXT: movq %rdi, %rax
244 ; CHECK-NEXT: shrq $63, %rax
245 ; CHECK-NEXT: andl $1, %edi
246 ; CHECK-NEXT: cmpq %rax, %rdi
247 ; CHECK-NEXT: sete %al
248 ; CHECK-NEXT: retq
249 %shl = shl i64 %x, 63
250 %and = and i64 %x, 9223372036854775808
251 %r = icmp eq i64 %shl, %and
252 ret i1 %r
253 }
255 define i1 @shl_to_shr_eq_i64_s63_fail(i64 %x) {
256 ; CHECK-LABEL: shl_to_shr_eq_i64_s63_fail:
257 ; CHECK: # %bb.0:
258 ; CHECK-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
259 ; CHECK-NEXT: andq %rdi, %rax
260 ; CHECK-NEXT: shlq $63, %rdi
261 ; CHECK-NEXT: cmpq %rax, %rdi
262 ; CHECK-NEXT: seta %al
263 ; CHECK-NEXT: retq
264 %shl = shl i64 %x, 63
265 %and = and i64 %x, 9223372036854775808
266 %r = icmp ugt i64 %shl, %and
267 ret i1 %r
268 }
270 define i1 @shr_to_shl_eq_i64_s7(i64 %x) {
271 ; CHECK-LABEL: shr_to_shl_eq_i64_s7:
272 ; CHECK: # %bb.0:
273 ; CHECK-NEXT: movq %rdi, %rax
274 ; CHECK-NEXT: shlq $7, %rax
275 ; CHECK-NEXT: andq $-128, %rdi
276 ; CHECK-NEXT: cmpq %rax, %rdi
277 ; CHECK-NEXT: sete %al
278 ; CHECK-NEXT: retq
279 %and = and i64 %x, 144115188075855871
280 %shr = lshr i64 %x, 7
281 %r = icmp eq i64 %and, %shr
282 ret i1 %r
283 }
285 define i1 @shl_to_shr_ne_i32_s24(i32 %x) {
286 ; CHECK-LABEL: shl_to_shr_ne_i32_s24:
287 ; CHECK: # %bb.0:
288 ; CHECK-NEXT: movzbl %dil, %eax
289 ; CHECK-NEXT: shrl $24, %edi
290 ; CHECK-NEXT: cmpl %edi, %eax
291 ; CHECK-NEXT: setne %al
292 ; CHECK-NEXT: retq
293 %shl = shl i32 %x, 24
294 %and = and i32 %x, 4278190080
295 %r = icmp ne i32 %shl, %and
296 ret i1 %r
297 }
299 define i1 @shr_to_shl_ne_i32_s24_fail(i32 %x) {
300 ; CHECK-LABEL: shr_to_shl_ne_i32_s24_fail:
301 ; CHECK: # %bb.0:
302 ; CHECK-NEXT: movl %edi, %eax
303 ; CHECK-NEXT: shrl $24, %eax
304 ; CHECK-NEXT: andl $-16777216, %edi # imm = 0xFF000000
305 ; CHECK-NEXT: cmpl %edi, %eax
306 ; CHECK-NEXT: setne %al
307 ; CHECK-NEXT: retq
308 %shl = lshr i32 %x, 24
309 %and = and i32 %x, 4278190080
310 %r = icmp ne i32 %shl, %and
311 ret i1 %r
312 }
314 define i1 @shr_to_shl_ne_i32_s8(i32 %x) {
315 ; CHECK-NOBMI-LABEL: shr_to_shl_ne_i32_s8:
316 ; CHECK-NOBMI: # %bb.0:
317 ; CHECK-NOBMI-NEXT: movl %edi, %eax
318 ; CHECK-NOBMI-NEXT: roll $8, %eax
319 ; CHECK-NOBMI-NEXT: cmpl %eax, %edi
320 ; CHECK-NOBMI-NEXT: setne %al
321 ; CHECK-NOBMI-NEXT: retq
322 ;
323 ; CHECK-BMI2-LABEL: shr_to_shl_ne_i32_s8:
324 ; CHECK-BMI2: # %bb.0:
325 ; CHECK-BMI2-NEXT: rorxl $24, %edi, %eax
326 ; CHECK-BMI2-NEXT: cmpl %eax, %edi
327 ; CHECK-BMI2-NEXT: setne %al
328 ; CHECK-BMI2-NEXT: retq
329 %and = and i32 %x, 16777215
330 %shr = lshr i32 %x, 8
331 %r = icmp ne i32 %and, %shr
332 ret i1 %r
333 }
335 define <4 x i1> @shr_to_ror_eq_4xi32_s4(<4 x i32> %x) {
336 ; CHECK-NOBMI-LABEL: shr_to_ror_eq_4xi32_s4:
337 ; CHECK-NOBMI: # %bb.0:
338 ; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm1
339 ; CHECK-NOBMI-NEXT: psrld $4, %xmm1
340 ; CHECK-NOBMI-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
341 ; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm0
342 ; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm1
343 ; CHECK-NOBMI-NEXT: pxor %xmm1, %xmm0
344 ; CHECK-NOBMI-NEXT: retq
345 ;
346 ; CHECK-BMI2-SSE2-LABEL: shr_to_ror_eq_4xi32_s4:
347 ; CHECK-BMI2-SSE2: # %bb.0:
348 ; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm1
349 ; CHECK-BMI2-SSE2-NEXT: psrld $4, %xmm1
350 ; CHECK-BMI2-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
351 ; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
352 ; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
353 ; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0
354 ; CHECK-BMI2-SSE2-NEXT: retq
355 ;
356 ; CHECK-AVX2-LABEL: shr_to_ror_eq_4xi32_s4:
357 ; CHECK-AVX2: # %bb.0:
358 ; CHECK-AVX2-NEXT: vpsrld $4, %xmm0, %xmm1
359 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [268435455,268435455,268435455,268435455]
360 ; CHECK-AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
361 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
362 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
363 ; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
364 ; CHECK-AVX2-NEXT: retq
365 ;
366 ; CHECK-AVX512-LABEL: shr_to_ror_eq_4xi32_s4:
367 ; CHECK-AVX512: # %bb.0:
368 ; CHECK-AVX512-NEXT: vprold $4, %xmm0, %xmm1
369 ; CHECK-AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
370 ; CHECK-AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
371 ; CHECK-AVX512-NEXT: retq
372 %shr = lshr <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4>
373 %and = and <4 x i32> %x, <i32 268435455, i32 268435455, i32 268435455, i32 268435455>
374 %r = icmp ne <4 x i32> %shr, %and
375 ret <4 x i1> %r
376 }
378 define <4 x i1> @shl_to_ror_eq_4xi32_s8(<4 x i32> %x) {
379 ; CHECK-NOBMI-LABEL: shl_to_ror_eq_4xi32_s8:
380 ; CHECK-NOBMI: # %bb.0:
381 ; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm1
382 ; CHECK-NOBMI-NEXT: pslld $8, %xmm1
383 ; CHECK-NOBMI-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
384 ; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm0
385 ; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm1
386 ; CHECK-NOBMI-NEXT: pxor %xmm1, %xmm0
387 ; CHECK-NOBMI-NEXT: retq
388 ;
389 ; CHECK-BMI2-SSE2-LABEL: shl_to_ror_eq_4xi32_s8:
390 ; CHECK-BMI2-SSE2: # %bb.0:
391 ; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm1
392 ; CHECK-BMI2-SSE2-NEXT: pslld $8, %xmm1
393 ; CHECK-BMI2-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
394 ; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
395 ; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
396 ; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0
397 ; CHECK-BMI2-SSE2-NEXT: retq
398 ;
399 ; CHECK-AVX2-LABEL: shl_to_ror_eq_4xi32_s8:
400 ; CHECK-AVX2: # %bb.0:
401 ; CHECK-AVX2-NEXT: vpslld $8, %xmm0, %xmm1
402 ; CHECK-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
403 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
404 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
405 ; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
406 ; CHECK-AVX2-NEXT: retq
407 ;
408 ; CHECK-AVX512-LABEL: shl_to_ror_eq_4xi32_s8:
409 ; CHECK-AVX512: # %bb.0:
410 ; CHECK-AVX512-NEXT: vprold $8, %xmm0, %xmm1
411 ; CHECK-AVX512-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
412 ; CHECK-AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
413 ; CHECK-AVX512-NEXT: retq
414 %shr = shl <4 x i32> %x, <i32 8, i32 8, i32 8, i32 8>
415 %and = and <4 x i32> %x, <i32 4294967040, i32 4294967040, i32 4294967040, i32 4294967040>
416 %r = icmp ne <4 x i32> %shr, %and
417 ret <4 x i1> %r
418 }
420 define <4 x i1> @shl_to_ror_eq_4xi32_s7_fail_no_p2(<4 x i32> %x) {
421 ; CHECK-NOBMI-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2:
422 ; CHECK-NOBMI: # %bb.0:
423 ; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm1
424 ; CHECK-NOBMI-NEXT: pslld $7, %xmm1
425 ; CHECK-NOBMI-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
426 ; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm0
427 ; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm1
428 ; CHECK-NOBMI-NEXT: pxor %xmm1, %xmm0
429 ; CHECK-NOBMI-NEXT: retq
430 ;
431 ; CHECK-BMI2-SSE2-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2:
432 ; CHECK-BMI2-SSE2: # %bb.0:
433 ; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm1
434 ; CHECK-BMI2-SSE2-NEXT: pslld $7, %xmm1
435 ; CHECK-BMI2-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
436 ; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
437 ; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
438 ; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0
439 ; CHECK-BMI2-SSE2-NEXT: retq
440 ;
441 ; CHECK-AVX2-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2:
442 ; CHECK-AVX2: # %bb.0:
443 ; CHECK-AVX2-NEXT: vpslld $7, %xmm0, %xmm1
444 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [4294967168,4294967168,4294967168,4294967168]
445 ; CHECK-AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
446 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
447 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
448 ; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
449 ; CHECK-AVX2-NEXT: retq
450 ;
451 ; CHECK-AVX512-LABEL: shl_to_ror_eq_4xi32_s7_fail_no_p2:
452 ; CHECK-AVX512: # %bb.0:
453 ; CHECK-AVX512-NEXT: vpslld $7, %xmm0, %xmm1
454 ; CHECK-AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
455 ; CHECK-AVX512-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
456 ; CHECK-AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
457 ; CHECK-AVX512-NEXT: retq
458 %shr = shl <4 x i32> %x, <i32 7, i32 7, i32 7, i32 7>
459 %and = and <4 x i32> %x, <i32 4294967168, i32 4294967168, i32 4294967168, i32 4294967168>
460 %r = icmp ne <4 x i32> %shr, %and
461 ret <4 x i1> %r
462 }
464 define <4 x i1> @shr_to_ror_eq_4xi32_s4_fail_no_splat(<4 x i32> %x) {
465 ; CHECK-NOBMI-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat:
466 ; CHECK-NOBMI: # %bb.0:
467 ; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm1
468 ; CHECK-NOBMI-NEXT: psrld $4, %xmm1
469 ; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm2
470 ; CHECK-NOBMI-NEXT: psrld $8, %xmm2
471 ; CHECK-NOBMI-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm1[2,0]
472 ; CHECK-NOBMI-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0]
473 ; CHECK-NOBMI-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
474 ; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm0
475 ; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm1
476 ; CHECK-NOBMI-NEXT: pxor %xmm1, %xmm0
477 ; CHECK-NOBMI-NEXT: retq
478 ;
479 ; CHECK-BMI2-SSE2-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat:
480 ; CHECK-BMI2-SSE2: # %bb.0:
481 ; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm1
482 ; CHECK-BMI2-SSE2-NEXT: psrld $4, %xmm1
483 ; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm2
484 ; CHECK-BMI2-SSE2-NEXT: psrld $8, %xmm2
485 ; CHECK-BMI2-SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm1[2,0]
486 ; CHECK-BMI2-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,0]
487 ; CHECK-BMI2-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
488 ; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
489 ; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
490 ; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0
491 ; CHECK-BMI2-SSE2-NEXT: retq
492 ;
493 ; CHECK-AVX2-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat:
494 ; CHECK-AVX2: # %bb.0:
495 ; CHECK-AVX2-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
496 ; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [268435455,268435455,268435455,268435455]
497 ; CHECK-AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
498 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
499 ; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
500 ; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
501 ; CHECK-AVX2-NEXT: retq
502 ;
503 ; CHECK-AVX512-LABEL: shr_to_ror_eq_4xi32_s4_fail_no_splat:
504 ; CHECK-AVX512: # %bb.0:
505 ; CHECK-AVX512-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
506 ; CHECK-AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
507 ; CHECK-AVX512-NEXT: vpcmpeqd %xmm0, %xmm1, %xmm0
508 ; CHECK-AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
509 ; CHECK-AVX512-NEXT: retq
510 %shr = lshr <4 x i32> %x, <i32 4, i32 4, i32 4, i32 8>
511 %and = and <4 x i32> %x, <i32 268435455, i32 268435455, i32 268435455, i32 268435455>
512 %r = icmp ne <4 x i32> %shr, %and
513 ret <4 x i1> %r
514 }
516 define <16 x i1> @shl_to_ror_eq_16xi16_s8_fail_preserve_i16(<16 x i16> %x) {
517 ; CHECK-NOBMI-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16:
518 ; CHECK-NOBMI: # %bb.0:
519 ; CHECK-NOBMI-NEXT: movdqa %xmm0, %xmm2
520 ; CHECK-NOBMI-NEXT: psllw $8, %xmm2
521 ; CHECK-NOBMI-NEXT: movdqa %xmm1, %xmm3
522 ; CHECK-NOBMI-NEXT: psllw $8, %xmm3
523 ; CHECK-NOBMI-NEXT: movdqa {{.*#+}} xmm4 = [0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255]
524 ; CHECK-NOBMI-NEXT: pand %xmm4, %xmm0
525 ; CHECK-NOBMI-NEXT: pcmpeqw %xmm2, %xmm0
526 ; CHECK-NOBMI-NEXT: pand %xmm4, %xmm1
527 ; CHECK-NOBMI-NEXT: pcmpeqw %xmm3, %xmm1
528 ; CHECK-NOBMI-NEXT: packsswb %xmm1, %xmm0
529 ; CHECK-NOBMI-NEXT: pcmpeqd %xmm1, %xmm1
530 ; CHECK-NOBMI-NEXT: pxor %xmm1, %xmm0
531 ; CHECK-NOBMI-NEXT: retq
532 ;
533 ; CHECK-BMI2-SSE2-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16:
534 ; CHECK-BMI2-SSE2: # %bb.0:
535 ; CHECK-BMI2-SSE2-NEXT: movdqa %xmm0, %xmm2
536 ; CHECK-BMI2-SSE2-NEXT: psllw $8, %xmm2
537 ; CHECK-BMI2-SSE2-NEXT: movdqa %xmm1, %xmm3
538 ; CHECK-BMI2-SSE2-NEXT: psllw $8, %xmm3
539 ; CHECK-BMI2-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [0,255,0,255,0,255,0,255,0,255,0,255,0,255,0,255]
540 ; CHECK-BMI2-SSE2-NEXT: pand %xmm4, %xmm0
541 ; CHECK-BMI2-SSE2-NEXT: pcmpeqw %xmm2, %xmm0
542 ; CHECK-BMI2-SSE2-NEXT: pand %xmm4, %xmm1
543 ; CHECK-BMI2-SSE2-NEXT: pcmpeqw %xmm3, %xmm1
544 ; CHECK-BMI2-SSE2-NEXT: packsswb %xmm1, %xmm0
545 ; CHECK-BMI2-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
546 ; CHECK-BMI2-SSE2-NEXT: pxor %xmm1, %xmm0
547 ; CHECK-BMI2-SSE2-NEXT: retq
548 ;
549 ; CHECK-AVX2-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16:
550 ; CHECK-AVX2: # %bb.0:
551 ; CHECK-AVX2-NEXT: vpsllw $8, %ymm0, %ymm1
552 ; CHECK-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
553 ; CHECK-AVX2-NEXT: vpcmpeqw %ymm0, %ymm1, %ymm0
554 ; CHECK-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
555 ; CHECK-AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
556 ; CHECK-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
557 ; CHECK-AVX2-NEXT: vpacksswb %xmm1, %xmm0, %xmm0
558 ; CHECK-AVX2-NEXT: vzeroupper
559 ; CHECK-AVX2-NEXT: retq
560 ;
561 ; CHECK-AVX512-LABEL: shl_to_ror_eq_16xi16_s8_fail_preserve_i16:
562 ; CHECK-AVX512: # %bb.0:
563 ; CHECK-AVX512-NEXT: vpsllw $8, %ymm0, %ymm1
564 ; CHECK-AVX512-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
565 ; CHECK-AVX512-NEXT: vpcmpeqw %ymm0, %ymm1, %ymm0
566 ; CHECK-AVX512-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
567 ; CHECK-AVX512-NEXT: vpmovdb %zmm0, %xmm0
568 ; CHECK-AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
569 ; CHECK-AVX512-NEXT: vzeroupper
570 ; CHECK-AVX512-NEXT: retq
571 %shr = shl <16 x i16> %x, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
572 %and = and <16 x i16> %x, <i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040, i16 4294967040>
573 %r = icmp ne <16 x i16> %shr, %and
574 ret <16 x i1> %r
575 }
577 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
578 ; CHECK-AVX: {{.*}}
579 ; CHECK-NOBMI-SSE2: {{.*}}