1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX1
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=ADL
6 declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>)
7 declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>)
9 ; Use widest possible vector for movmsk comparisons (PR37087)
11 define i1 @movmskps_noneof_bitcast_v4f64(<4 x double> %a0) {
12 ; CHECK-LABEL: movmskps_noneof_bitcast_v4f64:
14 ; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1
15 ; CHECK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
16 ; CHECK-NEXT: vtestpd %ymm0, %ymm0
17 ; CHECK-NEXT: sete %al
18 ; CHECK-NEXT: vzeroupper
21 ; ADL-LABEL: movmskps_noneof_bitcast_v4f64:
23 ; ADL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
24 ; ADL-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
25 ; ADL-NEXT: vmovmskpd %ymm0, %eax
26 ; ADL-NEXT: testl %eax, %eax
28 ; ADL-NEXT: vzeroupper
30 %1 = fcmp oeq <4 x double> %a0, zeroinitializer
31 %2 = sext <4 x i1> %1 to <4 x i64>
32 %3 = bitcast <4 x i64> %2 to <8 x float>
33 %4 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %3)
34 %5 = icmp eq i32 %4, 0
38 define i1 @movmskps_allof_bitcast_v4f64(<4 x double> %a0) {
39 ; AVX1-LABEL: movmskps_allof_bitcast_v4f64:
41 ; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1
42 ; AVX1-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
43 ; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
44 ; AVX1-NEXT: vtestpd %ymm1, %ymm0
46 ; AVX1-NEXT: vzeroupper
49 ; AVX2-LABEL: movmskps_allof_bitcast_v4f64:
51 ; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1
52 ; AVX2-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
53 ; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1
54 ; AVX2-NEXT: vtestpd %ymm1, %ymm0
56 ; AVX2-NEXT: vzeroupper
59 ; ADL-LABEL: movmskps_allof_bitcast_v4f64:
61 ; ADL-NEXT: vxorpd %xmm1, %xmm1, %xmm1
62 ; ADL-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0
63 ; ADL-NEXT: vmovmskpd %ymm0, %eax
64 ; ADL-NEXT: cmpl $15, %eax
66 ; ADL-NEXT: vzeroupper
68 %1 = fcmp oeq <4 x double> %a0, zeroinitializer
69 %2 = sext <4 x i1> %1 to <4 x i64>
70 %3 = bitcast <4 x i64> %2 to <8 x float>
71 %4 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %3)
72 %5 = icmp eq i32 %4, 255
77 ; TODO - Avoid sign extension ops when just extracting the sign bits.
80 define i32 @movmskpd_cmpgt_v4i64(<4 x i64> %a0) {
81 ; AVX1-LABEL: movmskpd_cmpgt_v4i64:
83 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
84 ; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm1
85 ; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3]
86 ; AVX1-NEXT: vmovmskpd %ymm0, %eax
87 ; AVX1-NEXT: vzeroupper
90 ; AVX2-LABEL: movmskpd_cmpgt_v4i64:
92 ; AVX2-NEXT: vmovmskpd %ymm0, %eax
93 ; AVX2-NEXT: vzeroupper
96 ; ADL-LABEL: movmskpd_cmpgt_v4i64:
98 ; ADL-NEXT: vmovmskpd %ymm0, %eax
99 ; ADL-NEXT: vzeroupper
101 %1 = icmp sgt <4 x i64> zeroinitializer, %a0
102 %2 = sext <4 x i1> %1 to <4 x i64>
103 %3 = bitcast <4 x i64> %2 to <4 x double>
104 %4 = tail call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %3)
108 define i32 @movmskps_ashr_v8i32(<8 x i32> %a0) {
109 ; AVX1-LABEL: movmskps_ashr_v8i32:
111 ; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
112 ; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7]
113 ; AVX1-NEXT: vmovmskps %ymm0, %eax
114 ; AVX1-NEXT: vzeroupper
117 ; AVX2-LABEL: movmskps_ashr_v8i32:
119 ; AVX2-NEXT: vmovmskps %ymm0, %eax
120 ; AVX2-NEXT: vzeroupper
123 ; ADL-LABEL: movmskps_ashr_v8i32:
125 ; ADL-NEXT: vmovmskps %ymm0, %eax
126 ; ADL-NEXT: vzeroupper
128 %1 = ashr <8 x i32> %a0, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
129 %2 = bitcast <8 x i32> %1 to <8 x float>
130 %3 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %2)
134 define i32 @movmskps_sext_v4i64(<4 x i32> %a0) {
135 ; AVX1-LABEL: movmskps_sext_v4i64:
137 ; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1
138 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
139 ; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0
140 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
141 ; AVX1-NEXT: vmovmskpd %ymm0, %eax
142 ; AVX1-NEXT: vzeroupper
145 ; AVX2-LABEL: movmskps_sext_v4i64:
147 ; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0
148 ; AVX2-NEXT: vmovmskpd %ymm0, %eax
149 ; AVX2-NEXT: vzeroupper
152 ; ADL-LABEL: movmskps_sext_v4i64:
154 ; ADL-NEXT: vpmovsxdq %xmm0, %ymm0
155 ; ADL-NEXT: vmovmskpd %ymm0, %eax
156 ; ADL-NEXT: vzeroupper
158 %1 = sext <4 x i32> %a0 to <4 x i64>
159 %2 = bitcast <4 x i64> %1 to <4 x double>
160 %3 = tail call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %2)
164 define i32 @movmskps_sext_v8i32(<8 x i16> %a0) {
165 ; AVX1-LABEL: movmskps_sext_v8i32:
167 ; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1
168 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
169 ; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0
170 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
171 ; AVX1-NEXT: vmovmskps %ymm0, %eax
172 ; AVX1-NEXT: vzeroupper
175 ; AVX2-LABEL: movmskps_sext_v8i32:
177 ; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0
178 ; AVX2-NEXT: vmovmskps %ymm0, %eax
179 ; AVX2-NEXT: vzeroupper
182 ; ADL-LABEL: movmskps_sext_v8i32:
184 ; ADL-NEXT: vpmovsxwd %xmm0, %ymm0
185 ; ADL-NEXT: vmovmskps %ymm0, %eax
186 ; ADL-NEXT: vzeroupper
188 %1 = sext <8 x i16> %a0 to <8 x i32>
189 %2 = bitcast <8 x i32> %1 to <8 x float>
190 %3 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %2)
194 define i32 @movmskps_concat_v4f32(<4 x float> %a0, <4 x float> %a1) {
195 ; CHECK-LABEL: movmskps_concat_v4f32:
197 ; CHECK-NEXT: vorps %xmm1, %xmm0, %xmm0
198 ; CHECK-NEXT: xorl %eax, %eax
199 ; CHECK-NEXT: vtestps %xmm0, %xmm0
200 ; CHECK-NEXT: setne %al
201 ; CHECK-NEXT: negl %eax
204 ; ADL-LABEL: movmskps_concat_v4f32:
206 ; ADL-NEXT: vorps %xmm1, %xmm0, %xmm0
207 ; ADL-NEXT: vmovmskps %xmm0, %ecx
208 ; ADL-NEXT: xorl %eax, %eax
209 ; ADL-NEXT: negl %ecx
210 ; ADL-NEXT: sbbl %eax, %eax
212 %1 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
213 %2 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %1)
214 %3 = icmp ne i32 %2, 0
215 %4 = sext i1 %3 to i32
219 define i32 @movmskps_demanded_concat_v4f32(<4 x float> %a0, <4 x float> %a1) {
220 ; CHECK-LABEL: movmskps_demanded_concat_v4f32:
222 ; CHECK-NEXT: vmovmskps %xmm0, %ecx
223 ; CHECK-NEXT: andl $3, %ecx
224 ; CHECK-NEXT: xorl %eax, %eax
225 ; CHECK-NEXT: negl %ecx
226 ; CHECK-NEXT: sbbl %eax, %eax
229 ; ADL-LABEL: movmskps_demanded_concat_v4f32:
231 ; ADL-NEXT: vmovmskps %xmm0, %ecx
232 ; ADL-NEXT: andl $3, %ecx
233 ; ADL-NEXT: xorl %eax, %eax
234 ; ADL-NEXT: negl %ecx
235 ; ADL-NEXT: sbbl %eax, %eax
237 %1 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
238 %2 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %1)
240 %4 = icmp ne i32 %3, 0
241 %5 = sext i1 %4 to i32