| blob | 52bb9ee7fcb9f5948f2c4e5f06dcce8178a3c17a |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE42
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1OR2
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX1OR2
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512F
8 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512BW
10 define <8 x i16> @test_v8i16_nosignbit(<8 x i16> %a, <8 x i16> %b) {
11 ; SSE2-LABEL: test_v8i16_nosignbit:
12 ; SSE2: # %bb.0:
13 ; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
14 ; SSE2-NEXT: psrlw $1, %xmm1
15 ; SSE2-NEXT: pminsw %xmm1, %xmm0
16 ; SSE2-NEXT: retq
17 ;
18 ; SSE41-LABEL: test_v8i16_nosignbit:
19 ; SSE41: # %bb.0:
20 ; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
21 ; SSE41-NEXT: psrlw $1, %xmm1
22 ; SSE41-NEXT: pminuw %xmm1, %xmm0
23 ; SSE41-NEXT: retq
24 ;
25 ; SSE42-LABEL: test_v8i16_nosignbit:
26 ; SSE42: # %bb.0:
27 ; SSE42-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
28 ; SSE42-NEXT: psrlw $1, %xmm1
29 ; SSE42-NEXT: pminuw %xmm1, %xmm0
30 ; SSE42-NEXT: retq
31 ;
32 ; AVX-LABEL: test_v8i16_nosignbit:
33 ; AVX: # %bb.0:
34 ; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
35 ; AVX-NEXT: vpsrlw $1, %xmm1, %xmm1
36 ; AVX-NEXT: vpminuw %xmm1, %xmm0, %xmm0
37 ; AVX-NEXT: retq
38 %1 = and <8 x i16> %a, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
39 %2 = lshr <8 x i16> %b, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
40 %3 = icmp ult <8 x i16> %1, %2
41 %4 = select <8 x i1> %3, <8 x i16> %1, <8 x i16> %2
42 ret <8 x i16> %4
43 }
45 define <16 x i8> @test_v16i8_reassociation(<16 x i8> %a) {
46 ; SSE-LABEL: test_v16i8_reassociation:
47 ; SSE: # %bb.0:
48 ; SSE-NEXT: movdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
49 ; SSE-NEXT: pmaxub %xmm1, %xmm0
50 ; SSE-NEXT: pmaxub %xmm1, %xmm0
51 ; SSE-NEXT: retq
52 ;
53 ; AVX-LABEL: test_v16i8_reassociation:
54 ; AVX: # %bb.0:
55 ; AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
56 ; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
57 ; AVX-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
58 ; AVX-NEXT: retq
59 %1 = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
60 %2 = call <16 x i8> @llvm.umax.v16i8(<16 x i8> %1, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>)
61 ret <16 x i8> %2
62 }
64 define <16 x i8> @test_v16i8_demandedbits(<16 x i8> %x, <16 x i8> %y, <16 x i8> %a, <16 x i8> %b) {
65 ; SSE2-LABEL: test_v16i8_demandedbits:
66 ; SSE2: # %bb.0:
67 ; SSE2-NEXT: pmaxub %xmm1, %xmm0
68 ; SSE2-NEXT: pxor %xmm1, %xmm1
69 ; SSE2-NEXT: pcmpgtb %xmm0, %xmm1
70 ; SSE2-NEXT: pand %xmm1, %xmm3
71 ; SSE2-NEXT: pandn %xmm2, %xmm1
72 ; SSE2-NEXT: por %xmm3, %xmm1
73 ; SSE2-NEXT: movdqa %xmm1, %xmm0
74 ; SSE2-NEXT: retq
75 ;
76 ; SSE41-LABEL: test_v16i8_demandedbits:
77 ; SSE41: # %bb.0:
78 ; SSE41-NEXT: orps %xmm1, %xmm0
79 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
80 ; SSE41-NEXT: movdqa %xmm2, %xmm0
81 ; SSE41-NEXT: retq
82 ;
83 ; SSE42-LABEL: test_v16i8_demandedbits:
84 ; SSE42: # %bb.0:
85 ; SSE42-NEXT: orps %xmm1, %xmm0
86 ; SSE42-NEXT: pblendvb %xmm0, %xmm3, %xmm2
87 ; SSE42-NEXT: movdqa %xmm2, %xmm0
88 ; SSE42-NEXT: retq
89 ;
90 ; AVX1OR2-LABEL: test_v16i8_demandedbits:
91 ; AVX1OR2: # %bb.0:
92 ; AVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0
93 ; AVX1OR2-NEXT: vpblendvb %xmm0, %xmm3, %xmm2, %xmm0
94 ; AVX1OR2-NEXT: retq
95 ;
96 ; AVX512F-LABEL: test_v16i8_demandedbits:
97 ; AVX512F: # %bb.0:
98 ; AVX512F-NEXT: vpor %xmm1, %xmm0, %xmm0
99 ; AVX512F-NEXT: vpblendvb %xmm0, %xmm3, %xmm2, %xmm0
100 ; AVX512F-NEXT: retq
101 ;
102 ; AVX512BW-LABEL: test_v16i8_demandedbits:
103 ; AVX512BW: # %bb.0:
104 ; AVX512BW-NEXT: # kill: def $xmm3 killed $xmm3 def $zmm3
105 ; AVX512BW-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
106 ; AVX512BW-NEXT: vpmaxub %xmm1, %xmm0, %xmm0
107 ; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1
108 ; AVX512BW-NEXT: vpcmpnltb %zmm1, %zmm0, %k1
109 ; AVX512BW-NEXT: vpblendmb %zmm2, %zmm3, %zmm0 {%k1}
110 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
111 ; AVX512BW-NEXT: vzeroupper
112 ; AVX512BW-NEXT: retq
113 %umax = tail call <16 x i8> @llvm.umax.v16i8(<16 x i8> %x, <16 x i8> %y)
114 %cmp = icmp sge <16 x i8> %umax, zeroinitializer
115 %res = select <16 x i1> %cmp, <16 x i8> %a, <16 x i8> %b
116 ret <16 x i8> %res
117 }
119 declare <16 x i8> @llvm.umax.v16i8(<16 x i8> %x, <16 x i8> %y)