| blob | 9c49ff8e573e9831750d5e1a880537bfe87b0249 |
1 # RUN: llc -mtriple=x86_64-- -run-pass x86-evex-to-vex-compress -verify-machineinstrs -mcpu=skx -o - %s | FileCheck %s
2 # This test verifies VEX encoding for AVX-512 instructions that use registers of low indexes and
3 # do not use zmm or mask registers and have a corresponding AVX/AVX2 opcode
5 --- |
6 define void @evex_z256_to_vex_test() { ret void }
7 define void @evex_z128_to_vex_test() { ret void }
8 define void @evex_scalar_to_vex_test() { ret void }
9 define void @evex_z256_to_evex_test() { ret void }
10 define void @evex_z128_to_evex_test() { ret void }
11 define void @evex_scalar_to_evex_test() { ret void }
12 ...
13 ---
14 # CHECK-LABEL: name: evex_z256_to_vex_test
15 # CHECK: bb.0:
17 name: evex_z256_to_vex_test
18 body: |
19 bb.0:
20 ; CHECK: VMOVAPDYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
21 VMOVAPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
22 ; CHECK: $ymm0 = VMOVAPDYrm $rip, 1, $noreg, 0, $noreg
23 $ymm0 = VMOVAPDZ256rm $rip, 1, $noreg, 0, $noreg
24 ; CHECK: $ymm0 = VMOVAPDYrr $ymm0
25 $ymm0 = VMOVAPDZ256rr $ymm0
26 ; CHECK: VMOVAPSYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
27 VMOVAPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
28 ; CHECK: $ymm0 = VMOVAPSYrm $rip, 1, $noreg, 0, $noreg
29 $ymm0 = VMOVAPSZ256rm $rip, 1, $noreg, 0, $noreg
30 ; CHECK: $ymm0 = VMOVAPSYrr $ymm0
31 $ymm0 = VMOVAPSZ256rr $ymm0
32 ; CHECK: $ymm0 = VMOVDDUPYrm $rip, 1, $noreg, 0, $noreg
33 $ymm0 = VMOVDDUPZ256rm $rip, 1, $noreg, 0, $noreg
34 ; CHECK: $ymm0 = VMOVDDUPYrr $ymm0
35 $ymm0 = VMOVDDUPZ256rr $ymm0
36 ; CHECK: VMOVDQAYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
37 VMOVDQA32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
38 ; CHECK: $ymm0 = VMOVDQAYrm $rip, 1, $noreg, 0, $noreg
39 $ymm0 = VMOVDQA32Z256rm $rip, 1, $noreg, 0, $noreg
40 ; CHECK: $ymm0 = VMOVDQAYrr $ymm0
41 $ymm0 = VMOVDQA32Z256rr $ymm0
42 ; CHECK: VMOVDQAYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
43 VMOVDQA64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
44 ; CHECK: $ymm0 = VMOVDQAYrm $rip, 1, $noreg, 0, $noreg
45 $ymm0 = VMOVDQA64Z256rm $rip, 1, $noreg, 0, $noreg
46 ; CHECK: $ymm0 = VMOVDQAYrr $ymm0
47 $ymm0 = VMOVDQA64Z256rr $ymm0
48 ; CHECK: VMOVDQUYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
49 VMOVDQU16Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
50 ; CHECK: $ymm0 = VMOVDQUYrm $rip, 1, $noreg, 0, $noreg
51 $ymm0 = VMOVDQU16Z256rm $rip, 1, $noreg, 0, $noreg
52 ; CHECK: $ymm0 = VMOVDQUYrr $ymm0
53 $ymm0 = VMOVDQU16Z256rr $ymm0
54 ; CHECK: VMOVDQUYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
55 VMOVDQU32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
56 ; CHECK: $ymm0 = VMOVDQUYrm $rip, 1, $noreg, 0, $noreg
57 $ymm0 = VMOVDQU32Z256rm $rip, 1, $noreg, 0, $noreg
58 ; CHECK: $ymm0 = VMOVDQUYrr $ymm0
59 $ymm0 = VMOVDQU32Z256rr $ymm0
60 ; CHECK: VMOVDQUYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
61 VMOVDQU64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
62 ; CHECK: $ymm0 = VMOVDQUYrm $rip, 1, $noreg, 0, $noreg
63 $ymm0 = VMOVDQU64Z256rm $rip, 1, $noreg, 0, $noreg
64 ; CHECK: $ymm0 = VMOVDQUYrr $ymm0
65 $ymm0 = VMOVDQU64Z256rr $ymm0
66 ; CHECK: VMOVDQUYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
67 VMOVDQU8Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
68 ; CHECK: $ymm0 = VMOVDQUYrm $rip, 1, $noreg, 0, $noreg
69 $ymm0 = VMOVDQU8Z256rm $rip, 1, $noreg, 0, $noreg
70 ; CHECK: $ymm0 = VMOVDQUYrr $ymm0
71 $ymm0 = VMOVDQU8Z256rr $ymm0
72 ; CHECK: $ymm0 = VMOVNTDQAYrm $rip, 1, $noreg, 0, $noreg
73 $ymm0 = VMOVNTDQAZ256rm $rip, 1, $noreg, 0, $noreg
74 ; CHECK: VMOVNTDQYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
75 VMOVNTDQZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
76 ; CHECK: VMOVNTPDYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
77 VMOVNTPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
78 ; CHECK: VMOVNTPSYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
79 VMOVNTPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
80 ; CHECK: $ymm0 = VMOVSHDUPYrm $rip, 1, $noreg, 0, $noreg
81 $ymm0 = VMOVSHDUPZ256rm $rip, 1, $noreg, 0, $noreg
82 ; CHECK: $ymm0 = VMOVSHDUPYrr $ymm0
83 $ymm0 = VMOVSHDUPZ256rr $ymm0
84 ; CHECK: $ymm0 = VMOVSLDUPYrm $rip, 1, $noreg, 0, $noreg
85 $ymm0 = VMOVSLDUPZ256rm $rip, 1, $noreg, 0, $noreg
86 ; CHECK: $ymm0 = VMOVSLDUPYrr $ymm0
87 $ymm0 = VMOVSLDUPZ256rr $ymm0
88 ; CHECK: VMOVUPDYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
89 VMOVUPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
90 ; CHECK: $ymm0 = VMOVUPDYrm $rip, 1, $noreg, 0, $noreg
91 $ymm0 = VMOVUPDZ256rm $rip, 1, $noreg, 0, $noreg
92 ; CHECK: $ymm0 = VMOVUPDYrr $ymm0
93 $ymm0 = VMOVUPDZ256rr $ymm0
94 ; CHECK: VMOVUPSYmr $rdi, 1, $noreg, 0, $noreg, $ymm0
95 VMOVUPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm0
96 ; CHECK: $ymm0 = VPANDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
97 $ymm0 = VPANDDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
98 ; CHECK: $ymm0 = VPANDYrr $ymm0, $ymm1
99 $ymm0 = VPANDDZ256rr $ymm0, $ymm1
100 ; CHECK: $ymm0 = VPANDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
101 $ymm0 = VPANDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
102 ; CHECK: $ymm0 = VPANDYrr $ymm0, $ymm1
103 $ymm0 = VPANDQZ256rr $ymm0, $ymm1
104 ; CHECK: $ymm0 = VPANDNYrm $ymm0, $rip, 1, $noreg, 0, $noreg
105 $ymm0 = VPANDNDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
106 ; CHECK: $ymm0 = VPANDNYrr $ymm0, $ymm1
107 $ymm0 = VPANDNDZ256rr $ymm0, $ymm1
108 ; CHECK: $ymm0 = VPANDNYrm $ymm0, $rip, 1, $noreg, 0, $noreg
109 $ymm0 = VPANDNQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
110 ; CHECK: $ymm0 = VPANDNYrr $ymm0, $ymm1
111 $ymm0 = VPANDNQZ256rr $ymm0, $ymm1
112 ; CHECK: $ymm0 = VPAVGBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
113 $ymm0 = VPAVGBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
114 ; CHECK: $ymm0 = VPAVGBYrr $ymm0, $ymm1
115 $ymm0 = VPAVGBZ256rr $ymm0, $ymm1
116 ; CHECK: $ymm0 = VPAVGWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
117 $ymm0 = VPAVGWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
118 ; CHECK: $ymm0 = VPAVGWYrr $ymm0, $ymm1
119 $ymm0 = VPAVGWZ256rr $ymm0, $ymm1
120 ; CHECK: $ymm0 = VPADDBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
121 $ymm0 = VPADDBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
122 ; CHECK: $ymm0 = VPADDBYrr $ymm0, $ymm1
123 $ymm0 = VPADDBZ256rr $ymm0, $ymm1
124 ; CHECK: $ymm0 = VPADDDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
125 $ymm0 = VPADDDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
126 ; CHECK: $ymm0 = VPADDDYrr $ymm0, $ymm1
127 $ymm0 = VPADDDZ256rr $ymm0, $ymm1
128 ; CHECK: $ymm0 = VPADDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
129 $ymm0 = VPADDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
130 ; CHECK: $ymm0 = VPADDQYrr $ymm0, $ymm1
131 $ymm0 = VPADDQZ256rr $ymm0, $ymm1
132 ; CHECK: $ymm0 = VPADDSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
133 $ymm0 = VPADDSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
134 ; CHECK: $ymm0 = VPADDSBYrr $ymm0, $ymm1
135 $ymm0 = VPADDSBZ256rr $ymm0, $ymm1
136 ; CHECK: $ymm0 = VPADDSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
137 $ymm0 = VPADDSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
138 ; CHECK: $ymm0 = VPADDSWYrr $ymm0, $ymm1
139 $ymm0 = VPADDSWZ256rr $ymm0, $ymm1
140 ; CHECK: $ymm0 = VPADDUSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
141 $ymm0 = VPADDUSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
142 ; CHECK: $ymm0 = VPADDUSBYrr $ymm0, $ymm1
143 $ymm0 = VPADDUSBZ256rr $ymm0, $ymm1
144 ; CHECK: $ymm0 = VPADDUSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
145 $ymm0 = VPADDUSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
146 ; CHECK: $ymm0 = VPADDUSWYrr $ymm0, $ymm1
147 $ymm0 = VPADDUSWZ256rr $ymm0, $ymm1
148 ; CHECK: $ymm0 = VPADDWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
149 $ymm0 = VPADDWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
150 ; CHECK: $ymm0 = VPADDWYrr $ymm0, $ymm1
151 $ymm0 = VPADDWZ256rr $ymm0, $ymm1
152 ; CHECK: $ymm0 = VMULPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
153 $ymm0 = VMULPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
154 ; CHECK: $ymm0 = VMULPDYrr $ymm0, $ymm1, implicit $mxcsr
155 $ymm0 = VMULPDZ256rr $ymm0, $ymm1, implicit $mxcsr
156 ; CHECK: $ymm0 = VMULPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
157 $ymm0 = VMULPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
158 ; CHECK: $ymm0 = VMULPSYrr $ymm0, $ymm1, implicit $mxcsr
159 $ymm0 = VMULPSZ256rr $ymm0, $ymm1, implicit $mxcsr
160 ; CHECK: $ymm0 = VORPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
161 $ymm0 = VORPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
162 ; CHECK: $ymm0 = VORPDYrr $ymm0, $ymm1
163 $ymm0 = VORPDZ256rr $ymm0, $ymm1
164 ; CHECK: $ymm0 = VORPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg
165 $ymm0 = VORPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
166 ; CHECK: $ymm0 = VORPSYrr $ymm0, $ymm1
167 $ymm0 = VORPSZ256rr $ymm0, $ymm1
168 ; CHECK: $ymm0 = VPMADDUBSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
169 $ymm0 = VPMADDUBSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
170 ; CHECK: $ymm0 = VPMADDUBSWYrr $ymm0, $ymm1
171 $ymm0 = VPMADDUBSWZ256rr $ymm0, $ymm1
172 ; CHECK: $ymm0 = VPMADDWDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
173 $ymm0 = VPMADDWDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
174 ; CHECK: $ymm0 = VPMADDWDYrr $ymm0, $ymm1
175 $ymm0 = VPMADDWDZ256rr $ymm0, $ymm1
176 ; CHECK: $ymm0 = VPMAXSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
177 $ymm0 = VPMAXSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
178 ; CHECK: $ymm0 = VPMAXSBYrr $ymm0, $ymm1
179 $ymm0 = VPMAXSBZ256rr $ymm0, $ymm1
180 ; CHECK: $ymm0 = VPMAXSDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
181 $ymm0 = VPMAXSDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
182 ; CHECK: $ymm0 = VPMAXSDYrr $ymm0, $ymm1
183 $ymm0 = VPMAXSDZ256rr $ymm0, $ymm1
184 ; CHECK: $ymm0 = VPMAXSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
185 $ymm0 = VPMAXSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
186 ; CHECK: $ymm0 = VPMAXSWYrr $ymm0, $ymm1
187 $ymm0 = VPMAXSWZ256rr $ymm0, $ymm1
188 ; CHECK: $ymm0 = VPMAXUBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
189 $ymm0 = VPMAXUBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
190 ; CHECK: $ymm0 = VPMAXUBYrr $ymm0, $ymm1
191 $ymm0 = VPMAXUBZ256rr $ymm0, $ymm1
192 ; CHECK: $ymm0 = VPMAXUDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
193 $ymm0 = VPMAXUDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
194 ; CHECK: $ymm0 = VPMAXUDYrr $ymm0, $ymm1
195 $ymm0 = VPMAXUDZ256rr $ymm0, $ymm1
196 ; CHECK: $ymm0 = VPMAXUWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
197 $ymm0 = VPMAXUWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
198 ; CHECK: $ymm0 = VPMAXUWYrr $ymm0, $ymm1
199 $ymm0 = VPMAXUWZ256rr $ymm0, $ymm1
200 ; CHECK: $ymm0 = VPMINSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
201 $ymm0 = VPMINSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
202 ; CHECK: $ymm0 = VPMINSBYrr $ymm0, $ymm1
203 $ymm0 = VPMINSBZ256rr $ymm0, $ymm1
204 ; CHECK: $ymm0 = VPMINSDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
205 $ymm0 = VPMINSDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
206 ; CHECK: $ymm0 = VPMINSDYrr $ymm0, $ymm1
207 $ymm0 = VPMINSDZ256rr $ymm0, $ymm1
208 ; CHECK: $ymm0 = VPMINSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
209 $ymm0 = VPMINSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
210 ; CHECK: $ymm0 = VPMINSWYrr $ymm0, $ymm1
211 $ymm0 = VPMINSWZ256rr $ymm0, $ymm1
212 ; CHECK: $ymm0 = VPMINUBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
213 $ymm0 = VPMINUBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
214 ; CHECK: $ymm0 = VPMINUBYrr $ymm0, $ymm1
215 $ymm0 = VPMINUBZ256rr $ymm0, $ymm1
216 ; CHECK: $ymm0 = VPMINUDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
217 $ymm0 = VPMINUDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
218 ; CHECK: $ymm0 = VPMINUDYrr $ymm0, $ymm1
219 $ymm0 = VPMINUDZ256rr $ymm0, $ymm1
220 ; CHECK: $ymm0 = VPMINUWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
221 $ymm0 = VPMINUWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
222 ; CHECK: $ymm0 = VPMINUWYrr $ymm0, $ymm1
223 $ymm0 = VPMINUWZ256rr $ymm0, $ymm1
224 ; CHECK: $ymm0 = VPMULDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
225 $ymm0 = VPMULDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
226 ; CHECK: $ymm0 = VPMULDQYrr $ymm0, $ymm1
227 $ymm0 = VPMULDQZ256rr $ymm0, $ymm1
228 ; CHECK: $ymm0 = VPMULHRSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
229 $ymm0 = VPMULHRSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
230 ; CHECK: $ymm0 = VPMULHRSWYrr $ymm0, $ymm1
231 $ymm0 = VPMULHRSWZ256rr $ymm0, $ymm1
232 ; CHECK: $ymm0 = VPMULHUWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
233 $ymm0 = VPMULHUWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
234 ; CHECK: $ymm0 = VPMULHUWYrr $ymm0, $ymm1
235 $ymm0 = VPMULHUWZ256rr $ymm0, $ymm1
236 ; CHECK: $ymm0 = VPMULHWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
237 $ymm0 = VPMULHWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
238 ; CHECK: $ymm0 = VPMULHWYrr $ymm0, $ymm1
239 $ymm0 = VPMULHWZ256rr $ymm0, $ymm1
240 ; CHECK: $ymm0 = VPMULLDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
241 $ymm0 = VPMULLDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
242 ; CHECK: $ymm0 = VPMULLDYrr $ymm0, $ymm1
243 $ymm0 = VPMULLDZ256rr $ymm0, $ymm1
244 ; CHECK: $ymm0 = VPMULLWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
245 $ymm0 = VPMULLWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
246 ; CHECK: $ymm0 = VPMULLWYrr $ymm0, $ymm1
247 $ymm0 = VPMULLWZ256rr $ymm0, $ymm1
248 ; CHECK: $ymm0 = VPMULUDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
249 $ymm0 = VPMULUDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
250 ; CHECK: $ymm0 = VPMULUDQYrr $ymm0, $ymm1
251 $ymm0 = VPMULUDQZ256rr $ymm0, $ymm1
252 ; CHECK: $ymm0 = VPORYrm $ymm0, $rip, 1, $noreg, 0, $noreg
253 $ymm0 = VPORDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
254 ; CHECK: $ymm0 = VPORYrr $ymm0, $ymm1
255 $ymm0 = VPORDZ256rr $ymm0, $ymm1
256 ; CHECK: $ymm0 = VPORYrm $ymm0, $rip, 1, $noreg, 0, $noreg
257 $ymm0 = VPORQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
258 ; CHECK: $ymm0 = VPORYrr $ymm0, $ymm1
259 $ymm0 = VPORQZ256rr $ymm0, $ymm1
260 ; CHECK: $ymm0 = VPSUBBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
261 $ymm0 = VPSUBBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
262 ; CHECK: $ymm0 = VPSUBBYrr $ymm0, $ymm1
263 $ymm0 = VPSUBBZ256rr $ymm0, $ymm1
264 ; CHECK: $ymm0 = VPSUBDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
265 $ymm0 = VPSUBDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
266 ; CHECK: $ymm0 = VPSUBDYrr $ymm0, $ymm1
267 $ymm0 = VPSUBDZ256rr $ymm0, $ymm1
268 ; CHECK: $ymm0 = VPSUBQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
269 $ymm0 = VPSUBQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
270 ; CHECK: $ymm0 = VPSUBQYrr $ymm0, $ymm1
271 $ymm0 = VPSUBQZ256rr $ymm0, $ymm1
272 ; CHECK: $ymm0 = VPSUBSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
273 $ymm0 = VPSUBSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
274 ; CHECK: $ymm0 = VPSUBSBYrr $ymm0, $ymm1
275 $ymm0 = VPSUBSBZ256rr $ymm0, $ymm1
276 ; CHECK: $ymm0 = VPSUBSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
277 $ymm0 = VPSUBSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
278 ; CHECK: $ymm0 = VPSUBSWYrr $ymm0, $ymm1
279 $ymm0 = VPSUBSWZ256rr $ymm0, $ymm1
280 ; CHECK: $ymm0 = VPSUBUSBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
281 $ymm0 = VPSUBUSBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
282 ; CHECK: $ymm0 = VPSUBUSBYrr $ymm0, $ymm1
283 $ymm0 = VPSUBUSBZ256rr $ymm0, $ymm1
284 ; CHECK: $ymm0 = VPSUBUSWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
285 $ymm0 = VPSUBUSWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
286 ; CHECK: $ymm0 = VPSUBUSWYrr $ymm0, $ymm1
287 $ymm0 = VPSUBUSWZ256rr $ymm0, $ymm1
288 ; CHECK: $ymm0 = VPSUBWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
289 $ymm0 = VPSUBWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
290 ; CHECK: $ymm0 = VPSUBWYrr $ymm0, $ymm1
291 $ymm0 = VPSUBWZ256rr $ymm0, $ymm1
292 ; CHECK: $ymm0 = VPXORYrm $ymm0, $rip, 1, $noreg, 0, $noreg
293 $ymm0 = VPXORDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
294 ; CHECK: $ymm0 = VPXORYrr $ymm0, $ymm1
295 $ymm0 = VPXORDZ256rr $ymm0, $ymm1
296 ; CHECK: $ymm0 = VPXORYrm $ymm0, $rip, 1, $noreg, 0, $noreg
297 $ymm0 = VPXORQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
298 ; CHECK: $ymm0 = VPXORYrr $ymm0, $ymm1
299 $ymm0 = VPXORQZ256rr $ymm0, $ymm1
300 ; CHECK: $ymm0 = VADDPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
301 $ymm0 = VADDPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
302 ; CHECK: $ymm0 = VADDPDYrr $ymm0, $ymm1, implicit $mxcsr
303 $ymm0 = VADDPDZ256rr $ymm0, $ymm1, implicit $mxcsr
304 ; CHECK: $ymm0 = VADDPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
305 $ymm0 = VADDPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
306 ; CHECK: $ymm0 = VADDPSYrr $ymm0, $ymm1, implicit $mxcsr
307 $ymm0 = VADDPSZ256rr $ymm0, $ymm1, implicit $mxcsr
308 ; CHECK: $ymm0 = VANDNPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
309 $ymm0 = VANDNPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
310 ; CHECK: $ymm0 = VANDNPDYrr $ymm0, $ymm1
311 $ymm0 = VANDNPDZ256rr $ymm0, $ymm1
312 ; CHECK: $ymm0 = VANDNPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg
313 $ymm0 = VANDNPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
314 ; CHECK: $ymm0 = VANDNPSYrr $ymm0, $ymm1
315 $ymm0 = VANDNPSZ256rr $ymm0, $ymm1
316 ; CHECK: $ymm0 = VANDPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
317 $ymm0 = VANDPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
318 ; CHECK: $ymm0 = VANDPDYrr $ymm0, $ymm1
319 $ymm0 = VANDPDZ256rr $ymm0, $ymm1
320 ; CHECK: $ymm0 = VANDPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg
321 $ymm0 = VANDPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
322 ; CHECK: $ymm0 = VANDPSYrr $ymm0, $ymm1
323 $ymm0 = VANDPSZ256rr $ymm0, $ymm1
324 ; CHECK: $ymm0 = VDIVPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
325 $ymm0 = VDIVPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
326 ; CHECK: $ymm0 = VDIVPDYrr $ymm0, $ymm1, implicit $mxcsr
327 $ymm0 = VDIVPDZ256rr $ymm0, $ymm1, implicit $mxcsr
328 ; CHECK: $ymm0 = VDIVPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
329 $ymm0 = VDIVPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
330 ; CHECK: $ymm0 = VDIVPSYrr $ymm0, $ymm1, implicit $mxcsr
331 $ymm0 = VDIVPSZ256rr $ymm0, $ymm1, implicit $mxcsr
332 ; CHECK: $ymm0 = VMAXCPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
333 $ymm0 = VMAXCPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
334 ; CHECK: $ymm0 = VMAXCPDYrr $ymm0, $ymm1, implicit $mxcsr
335 $ymm0 = VMAXCPDZ256rr $ymm0, $ymm1, implicit $mxcsr
336 ; CHECK: $ymm0 = VMAXCPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
337 $ymm0 = VMAXCPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
338 ; CHECK: $ymm0 = VMAXCPSYrr $ymm0, $ymm1, implicit $mxcsr
339 $ymm0 = VMAXCPSZ256rr $ymm0, $ymm1, implicit $mxcsr
340 ; CHECK: $ymm0 = VMAXPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
341 $ymm0 = VMAXPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
342 ; CHECK: $ymm0 = VMAXPDYrr $ymm0, $ymm1, implicit $mxcsr
343 $ymm0 = VMAXPDZ256rr $ymm0, $ymm1, implicit $mxcsr
344 ; CHECK: $ymm0 = VMAXPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
345 $ymm0 = VMAXPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
346 ; CHECK: $ymm0 = VMAXPSYrr $ymm0, $ymm1, implicit $mxcsr
347 $ymm0 = VMAXPSZ256rr $ymm0, $ymm1, implicit $mxcsr
348 ; CHECK: $ymm0 = VMINCPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
349 $ymm0 = VMINCPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
350 ; CHECK: $ymm0 = VMINCPDYrr $ymm0, $ymm1, implicit $mxcsr
351 $ymm0 = VMINCPDZ256rr $ymm0, $ymm1, implicit $mxcsr
352 ; CHECK: $ymm0 = VMINCPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
353 $ymm0 = VMINCPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
354 ; CHECK: $ymm0 = VMINCPSYrr $ymm0, $ymm1, implicit $mxcsr
355 $ymm0 = VMINCPSZ256rr $ymm0, $ymm1, implicit $mxcsr
356 ; CHECK: $ymm0 = VMINPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
357 $ymm0 = VMINPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
358 ; CHECK: $ymm0 = VMINPDYrr $ymm0, $ymm1, implicit $mxcsr
359 $ymm0 = VMINPDZ256rr $ymm0, $ymm1, implicit $mxcsr
360 ; CHECK: $ymm0 = VMINPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
361 $ymm0 = VMINPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
362 ; CHECK: $ymm0 = VMINPSYrr $ymm0, $ymm1, implicit $mxcsr
363 $ymm0 = VMINPSZ256rr $ymm0, $ymm1, implicit $mxcsr
364 ; CHECK: $ymm0 = VXORPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
365 $ymm0 = VXORPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
366 ; CHECK: $ymm0 = VXORPDYrr $ymm0, $ymm1
367 $ymm0 = VXORPDZ256rr $ymm0, $ymm1
368 ; CHECK: $ymm0 = VXORPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg
369 $ymm0 = VXORPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
370 ; CHECK: $ymm0 = VXORPSYrr $ymm0, $ymm1
371 $ymm0 = VXORPSZ256rr $ymm0, $ymm1
372 ; CHECK: $ymm0 = VPACKSSDWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
373 $ymm0 = VPACKSSDWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
374 ; CHECK: $ymm0 = VPACKSSDWYrr $ymm0, $ymm1
375 $ymm0 = VPACKSSDWZ256rr $ymm0, $ymm1
376 ; CHECK: $ymm0 = VPACKSSWBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
377 $ymm0 = VPACKSSWBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
378 ; CHECK: $ymm0 = VPACKSSWBYrr $ymm0, $ymm1
379 $ymm0 = VPACKSSWBZ256rr $ymm0, $ymm1
380 ; CHECK: $ymm0 = VPACKUSDWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
381 $ymm0 = VPACKUSDWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
382 ; CHECK: $ymm0 = VPACKUSDWYrr $ymm0, $ymm1
383 $ymm0 = VPACKUSDWZ256rr $ymm0, $ymm1
384 ; CHECK: $ymm0 = VPACKUSWBYrm $ymm0, $rip, 1, $noreg, 0, $noreg
385 $ymm0 = VPACKUSWBZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
386 ; CHECK: $ymm0 = VPACKUSWBYrr $ymm0, $ymm1
387 $ymm0 = VPACKUSWBZ256rr $ymm0, $ymm1
388 ; CHECK: $ymm0 = VUNPCKHPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
389 $ymm0 = VUNPCKHPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
390 ; CHECK: $ymm0 = VUNPCKHPDYrr $ymm0, $ymm1
391 $ymm0 = VUNPCKHPDZ256rr $ymm0, $ymm1
392 ; CHECK: $ymm0 = VUNPCKHPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg
393 $ymm0 = VUNPCKHPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
394 ; CHECK: $ymm0 = VUNPCKHPSYrr $ymm0, $ymm1
395 $ymm0 = VUNPCKHPSZ256rr $ymm0, $ymm1
396 ; CHECK: $ymm0 = VUNPCKLPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
397 $ymm0 = VUNPCKLPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
398 ; CHECK: $ymm0 = VUNPCKLPDYrr $ymm0, $ymm1
399 $ymm0 = VUNPCKLPDZ256rr $ymm0, $ymm1
400 ; CHECK: $ymm0 = VUNPCKLPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg
401 $ymm0 = VUNPCKLPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
402 ; CHECK: $ymm0 = VUNPCKLPSYrr $ymm0, $ymm1
403 $ymm0 = VUNPCKLPSZ256rr $ymm0, $ymm1
404 ; CHECK: $ymm0 = VSUBPDYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
405 $ymm0 = VSUBPDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
406 ; CHECK: $ymm0 = VSUBPDYrr $ymm0, $ymm1, implicit $mxcsr
407 $ymm0 = VSUBPDZ256rr $ymm0, $ymm1, implicit $mxcsr
408 ; CHECK: $ymm0 = VSUBPSYrm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
409 $ymm0 = VSUBPSZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
410 ; CHECK: $ymm0 = VSUBPSYrr $ymm0, $ymm1, implicit $mxcsr
411 $ymm0 = VSUBPSZ256rr $ymm0, $ymm1, implicit $mxcsr
412 ; CHECK: $ymm0 = VPUNPCKHBWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
413 $ymm0 = VPUNPCKHBWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
414 ; CHECK: $ymm0 = VPUNPCKHBWYrr $ymm0, $ymm1
415 $ymm0 = VPUNPCKHBWZ256rr $ymm0, $ymm1
416 ; CHECK: $ymm0 = VPUNPCKHDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
417 $ymm0 = VPUNPCKHDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
418 ; CHECK: $ymm0 = VPUNPCKHDQYrr $ymm0, $ymm1
419 $ymm0 = VPUNPCKHDQZ256rr $ymm0, $ymm1
420 ; CHECK: $ymm0 = VPUNPCKHQDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
421 $ymm0 = VPUNPCKHQDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
422 ; CHECK: $ymm0 = VPUNPCKHQDQYrr $ymm0, $ymm1
423 $ymm0 = VPUNPCKHQDQZ256rr $ymm0, $ymm1
424 ; CHECK: $ymm0 = VPUNPCKHWDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
425 $ymm0 = VPUNPCKHWDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
426 ; CHECK: $ymm0 = VPUNPCKHWDYrr $ymm0, $ymm1
427 $ymm0 = VPUNPCKHWDZ256rr $ymm0, $ymm1
428 ; CHECK: $ymm0 = VPUNPCKLBWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
429 $ymm0 = VPUNPCKLBWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
430 ; CHECK: $ymm0 = VPUNPCKLBWYrr $ymm0, $ymm1
431 $ymm0 = VPUNPCKLBWZ256rr $ymm0, $ymm1
432 ; CHECK: $ymm0 = VPUNPCKLDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
433 $ymm0 = VPUNPCKLDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
434 ; CHECK: $ymm0 = VPUNPCKLDQYrr $ymm0, $ymm1
435 $ymm0 = VPUNPCKLDQZ256rr $ymm0, $ymm1
436 ; CHECK: $ymm0 = VPUNPCKLQDQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
437 $ymm0 = VPUNPCKLQDQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
438 ; CHECK: $ymm0 = VPUNPCKLQDQYrr $ymm0, $ymm1
439 $ymm0 = VPUNPCKLQDQZ256rr $ymm0, $ymm1
440 ; CHECK: $ymm0 = VPUNPCKLWDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
441 $ymm0 = VPUNPCKLWDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
442 ; CHECK: $ymm0 = VPUNPCKLWDYrr $ymm0, $ymm1
443 $ymm0 = VPUNPCKLWDZ256rr $ymm0, $ymm1
444 ; CHECK: $ymm0 = VFMADD132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
445 $ymm0 = VFMADD132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
446 ; CHECK: $ymm0 = VFMADD132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
447 $ymm0 = VFMADD132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
448 ; CHECK: $ymm0 = VFMADD132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
449 $ymm0 = VFMADD132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
450 ; CHECK: $ymm0 = VFMADD132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
451 $ymm0 = VFMADD132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
452 ; CHECK: $ymm0 = VFMADD213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
453 $ymm0 = VFMADD213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
454 ; CHECK: $ymm0 = VFMADD213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
455 $ymm0 = VFMADD213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
456 ; CHECK: $ymm0 = VFMADD213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
457 $ymm0 = VFMADD213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
458 ; CHECK: $ymm0 = VFMADD213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
459 $ymm0 = VFMADD213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
460 ; CHECK: $ymm0 = VFMADD231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
461 $ymm0 = VFMADD231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
462 ; CHECK: $ymm0 = VFMADD231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
463 $ymm0 = VFMADD231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
464 ; CHECK: $ymm0 = VFMADD231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
465 $ymm0 = VFMADD231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
466 ; CHECK: $ymm0 = VFMADD231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
467 $ymm0 = VFMADD231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
468 ; CHECK: $ymm0 = VFMADDSUB132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
469 $ymm0 = VFMADDSUB132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
470 ; CHECK: $ymm0 = VFMADDSUB132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
471 $ymm0 = VFMADDSUB132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
472 ; CHECK: $ymm0 = VFMADDSUB132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
473 $ymm0 = VFMADDSUB132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
474 ; CHECK: $ymm0 = VFMADDSUB132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
475 $ymm0 = VFMADDSUB132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
476 ; CHECK: $ymm0 = VFMADDSUB213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
477 $ymm0 = VFMADDSUB213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
478 ; CHECK: $ymm0 = VFMADDSUB213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
479 $ymm0 = VFMADDSUB213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
480 ; CHECK: $ymm0 = VFMADDSUB213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
481 $ymm0 = VFMADDSUB213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
482 ; CHECK: $ymm0 = VFMADDSUB213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
483 $ymm0 = VFMADDSUB213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
484 ; CHECK: $ymm0 = VFMADDSUB231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
485 $ymm0 = VFMADDSUB231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
486 ; CHECK: $ymm0 = VFMADDSUB231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
487 $ymm0 = VFMADDSUB231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
488 ; CHECK: $ymm0 = VFMADDSUB231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
489 $ymm0 = VFMADDSUB231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
490 ; CHECK: $ymm0 = VFMADDSUB231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
491 $ymm0 = VFMADDSUB231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
492 ; CHECK: $ymm0 = VFMSUB132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
493 $ymm0 = VFMSUB132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
494 ; CHECK: $ymm0 = VFMSUB132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
495 $ymm0 = VFMSUB132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
496 ; CHECK: $ymm0 = VFMSUB132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
497 $ymm0 = VFMSUB132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
498 ; CHECK: $ymm0 = VFMSUB132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
499 $ymm0 = VFMSUB132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
500 ; CHECK: $ymm0 = VFMSUB213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
501 $ymm0 = VFMSUB213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
502 ; CHECK: $ymm0 = VFMSUB213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
503 $ymm0 = VFMSUB213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
504 ; CHECK: $ymm0 = VFMSUB213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
505 $ymm0 = VFMSUB213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
506 ; CHECK: $ymm0 = VFMSUB213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
507 $ymm0 = VFMSUB213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
508 ; CHECK: $ymm0 = VFMSUB231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
509 $ymm0 = VFMSUB231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
510 ; CHECK: $ymm0 = VFMSUB231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
511 $ymm0 = VFMSUB231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
512 ; CHECK: $ymm0 = VFMSUB231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
513 $ymm0 = VFMSUB231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
514 ; CHECK: $ymm0 = VFMSUB231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
515 $ymm0 = VFMSUB231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
516 ; CHECK: $ymm0 = VFMSUBADD132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
517 $ymm0 = VFMSUBADD132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
518 ; CHECK: $ymm0 = VFMSUBADD132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
519 $ymm0 = VFMSUBADD132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
520 ; CHECK: $ymm0 = VFMSUBADD132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
521 $ymm0 = VFMSUBADD132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
522 ; CHECK: $ymm0 = VFMSUBADD132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
523 $ymm0 = VFMSUBADD132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
524 ; CHECK: $ymm0 = VFMSUBADD213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
525 $ymm0 = VFMSUBADD213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
526 ; CHECK: $ymm0 = VFMSUBADD213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
527 $ymm0 = VFMSUBADD213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
528 ; CHECK: $ymm0 = VFMSUBADD213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
529 $ymm0 = VFMSUBADD213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
530 ; CHECK: $ymm0 = VFMSUBADD213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
531 $ymm0 = VFMSUBADD213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
532 ; CHECK: $ymm0 = VFMSUBADD231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
533 $ymm0 = VFMSUBADD231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
534 ; CHECK: $ymm0 = VFMSUBADD231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
535 $ymm0 = VFMSUBADD231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
536 ; CHECK: $ymm0 = VFMSUBADD231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
537 $ymm0 = VFMSUBADD231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
538 ; CHECK: $ymm0 = VFMSUBADD231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
539 $ymm0 = VFMSUBADD231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
540 ; CHECK: $ymm0 = VFNMADD132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
541 $ymm0 = VFNMADD132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
542 ; CHECK: $ymm0 = VFNMADD132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
543 $ymm0 = VFNMADD132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
544 ; CHECK: $ymm0 = VFNMADD132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
545 $ymm0 = VFNMADD132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
546 ; CHECK: $ymm0 = VFNMADD132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
547 $ymm0 = VFNMADD132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
548 ; CHECK: $ymm0 = VFNMADD213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
549 $ymm0 = VFNMADD213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
550 ; CHECK: $ymm0 = VFNMADD213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
551 $ymm0 = VFNMADD213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
552 ; CHECK: $ymm0 = VFNMADD213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
553 $ymm0 = VFNMADD213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
554 ; CHECK: $ymm0 = VFNMADD213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
555 $ymm0 = VFNMADD213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
556 ; CHECK: $ymm0 = VFNMADD231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
557 $ymm0 = VFNMADD231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
558 ; CHECK: $ymm0 = VFNMADD231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
559 $ymm0 = VFNMADD231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
560 ; CHECK: $ymm0 = VFNMADD231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
561 $ymm0 = VFNMADD231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
562 ; CHECK: $ymm0 = VFNMADD231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
563 $ymm0 = VFNMADD231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
564 ; CHECK: $ymm0 = VFNMSUB132PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
565 $ymm0 = VFNMSUB132PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
566 ; CHECK: $ymm0 = VFNMSUB132PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
567 $ymm0 = VFNMSUB132PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
568 ; CHECK: $ymm0 = VFNMSUB132PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
569 $ymm0 = VFNMSUB132PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
570 ; CHECK: $ymm0 = VFNMSUB132PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
571 $ymm0 = VFNMSUB132PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
572 ; CHECK: $ymm0 = VFNMSUB213PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
573 $ymm0 = VFNMSUB213PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
574 ; CHECK: $ymm0 = VFNMSUB213PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
575 $ymm0 = VFNMSUB213PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
576 ; CHECK: $ymm0 = VFNMSUB213PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
577 $ymm0 = VFNMSUB213PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
578 ; CHECK: $ymm0 = VFNMSUB213PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
579 $ymm0 = VFNMSUB213PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
580 ; CHECK: $ymm0 = VFNMSUB231PDYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
581 $ymm0 = VFNMSUB231PDZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
582 ; CHECK: $ymm0 = VFNMSUB231PDYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
583 $ymm0 = VFNMSUB231PDZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
584 ; CHECK: $ymm0 = VFNMSUB231PSYm $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
585 $ymm0 = VFNMSUB231PSZ256m $ymm0, $ymm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
586 ; CHECK: $ymm0 = VFNMSUB231PSYr $ymm0, $ymm1, $ymm2, implicit $mxcsr
587 $ymm0 = VFNMSUB231PSZ256r $ymm0, $ymm1, $ymm2, implicit $mxcsr
588 ; CHECK: $ymm0 = VPSRADYri $ymm0, 7
589 $ymm0 = VPSRADZ256ri $ymm0, 7
590 ; CHECK: $ymm0 = VPSRADYrm $ymm0, $rip, 1, $noreg, 0, $noreg
591 $ymm0 = VPSRADZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
592 ; CHECK: $ymm0 = VPSRADYrr $ymm0, $xmm1
593 $ymm0 = VPSRADZ256rr $ymm0, $xmm1
594 ; CHECK: $ymm0 = VPSRAVDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
595 $ymm0 = VPSRAVDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
596 ; CHECK: $ymm0 = VPSRAVDYrr $ymm0, $ymm1
597 $ymm0 = VPSRAVDZ256rr $ymm0, $ymm1
598 ; CHECK: $ymm0 = VPSRAWYri $ymm0, 7
599 $ymm0 = VPSRAWZ256ri $ymm0, 7
600 ; CHECK: $ymm0 = VPSRAWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
601 $ymm0 = VPSRAWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
602 ; CHECK: $ymm0 = VPSRAWYrr $ymm0, $xmm1
603 $ymm0 = VPSRAWZ256rr $ymm0, $xmm1
604 ; CHECK: $ymm0 = VPSRLDQYri $ymm0, 7
605 $ymm0 = VPSRLDQZ256ri $ymm0, 7
606 ; CHECK: $ymm0 = VPSRLDYri $ymm0, 7
607 $ymm0 = VPSRLDZ256ri $ymm0, 7
608 ; CHECK: $ymm0 = VPSRLDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
609 $ymm0 = VPSRLDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
610 ; CHECK: $ymm0 = VPSRLDYrr $ymm0, $xmm1
611 $ymm0 = VPSRLDZ256rr $ymm0, $xmm1
612 ; CHECK: $ymm0 = VPSRLQYri $ymm0, 7
613 $ymm0 = VPSRLQZ256ri $ymm0, 7
614 ; CHECK: $ymm0 = VPSRLQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
615 $ymm0 = VPSRLQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
616 ; CHECK: $ymm0 = VPSRLQYrr $ymm0, $xmm1
617 $ymm0 = VPSRLQZ256rr $ymm0, $xmm1
618 ; CHECK: $ymm0 = VPSRLVDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
619 $ymm0 = VPSRLVDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
620 ; CHECK: $ymm0 = VPSRLVDYrr $ymm0, $ymm1
621 $ymm0 = VPSRLVDZ256rr $ymm0, $ymm1
622 ; CHECK: $ymm0 = VPSRLVQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
623 $ymm0 = VPSRLVQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
624 ; CHECK: $ymm0 = VPSRLVQYrr $ymm0, $ymm1
625 $ymm0 = VPSRLVQZ256rr $ymm0, $ymm1
626 ; CHECK: $ymm0 = VPSRLWYri $ymm0, 7
627 $ymm0 = VPSRLWZ256ri $ymm0, 7
628 ; CHECK: $ymm0 = VPSRLWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
629 $ymm0 = VPSRLWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
630 ; CHECK: $ymm0 = VPSRLWYrr $ymm0, $xmm1
631 $ymm0 = VPSRLWZ256rr $ymm0, $xmm1
632 ; CHECK: $ymm0 = VPMOVSXBDYrm $rip, 1, $noreg, 0, $noreg
633 $ymm0 = VPMOVSXBDZ256rm $rip, 1, $noreg, 0, $noreg
634 ; CHECK: $ymm0 = VPMOVSXBDYrr $xmm0
635 $ymm0 = VPMOVSXBDZ256rr $xmm0
636 ; CHECK: $ymm0 = VPMOVSXBQYrm $rip, 1, $noreg, 0, $noreg
637 $ymm0 = VPMOVSXBQZ256rm $rip, 1, $noreg, 0, $noreg
638 ; CHECK: $ymm0 = VPMOVSXBQYrr $xmm0
639 $ymm0 = VPMOVSXBQZ256rr $xmm0
640 ; CHECK: $ymm0 = VPMOVSXBWYrm $rip, 1, $noreg, 0, $noreg
641 $ymm0 = VPMOVSXBWZ256rm $rip, 1, $noreg, 0, $noreg
642 ; CHECK: $ymm0 = VPMOVSXBWYrr $xmm0
643 $ymm0 = VPMOVSXBWZ256rr $xmm0
644 ; CHECK: $ymm0 = VPMOVSXDQYrm $rip, 1, $noreg, 0, $noreg
645 $ymm0 = VPMOVSXDQZ256rm $rip, 1, $noreg, 0, $noreg
646 ; CHECK: $ymm0 = VPMOVSXDQYrr $xmm0
647 $ymm0 = VPMOVSXDQZ256rr $xmm0
648 ; CHECK: $ymm0 = VPMOVSXWDYrm $rip, 1, $noreg, 0, $noreg
649 $ymm0 = VPMOVSXWDZ256rm $rip, 1, $noreg, 0, $noreg
650 ; CHECK: $ymm0 = VPMOVSXWDYrr $xmm0
651 $ymm0 = VPMOVSXWDZ256rr $xmm0
652 ; CHECK: $ymm0 = VPMOVSXWQYrm $rip, 1, $noreg, 0, $noreg
653 $ymm0 = VPMOVSXWQZ256rm $rip, 1, $noreg, 0, $noreg
654 ; CHECK: $ymm0 = VPMOVSXWQYrr $xmm0
655 $ymm0 = VPMOVSXWQZ256rr $xmm0
656 ; CHECK: $ymm0 = VPMOVZXBDYrm $rip, 1, $noreg, 0, $noreg
657 $ymm0 = VPMOVZXBDZ256rm $rip, 1, $noreg, 0, $noreg
658 ; CHECK: $ymm0 = VPMOVZXBDYrr $xmm0
659 $ymm0 = VPMOVZXBDZ256rr $xmm0
660 ; CHECK: $ymm0 = VPMOVZXBQYrm $rip, 1, $noreg, 0, $noreg
661 $ymm0 = VPMOVZXBQZ256rm $rip, 1, $noreg, 0, $noreg
662 ; CHECK: $ymm0 = VPMOVZXBQYrr $xmm0
663 $ymm0 = VPMOVZXBQZ256rr $xmm0
664 ; CHECK: $ymm0 = VPMOVZXBWYrm $rip, 1, $noreg, 0, $noreg
665 $ymm0 = VPMOVZXBWZ256rm $rip, 1, $noreg, 0, $noreg
666 ; CHECK: $ymm0 = VPMOVZXBWYrr $xmm0
667 $ymm0 = VPMOVZXBWZ256rr $xmm0
668 ; CHECK: $ymm0 = VPMOVZXDQYrm $rip, 1, $noreg, 0, $noreg
669 $ymm0 = VPMOVZXDQZ256rm $rip, 1, $noreg, 0, $noreg
670 ; CHECK: $ymm0 = VPMOVZXDQYrr $xmm0
671 $ymm0 = VPMOVZXDQZ256rr $xmm0
672 ; CHECK: $ymm0 = VPMOVZXWDYrm $rip, 1, $noreg, 0, $noreg
673 $ymm0 = VPMOVZXWDZ256rm $rip, 1, $noreg, 0, $noreg
674 ; CHECK: $ymm0 = VPMOVZXWDYrr $xmm0
675 $ymm0 = VPMOVZXWDZ256rr $xmm0
676 ; CHECK: $ymm0 = VPMOVZXWQYrm $rip, 1, $noreg, 0, $noreg
677 $ymm0 = VPMOVZXWQZ256rm $rip, 1, $noreg, 0, $noreg
678 ; CHECK: $ymm0 = VPMOVZXWQYrr $xmm0
679 $ymm0 = VPMOVZXWQZ256rr $xmm0
680 ; CHECK: $ymm0 = VBROADCASTF128 $rip, 1, $noreg, 0, $noreg
681 $ymm0 = VBROADCASTF32X4Z256rm $rip, 1, $noreg, 0, $noreg
682 ; CHECK: $ymm0 = VBROADCASTSDYrm $rip, 1, $noreg, 0, $noreg
683 $ymm0 = VBROADCASTF32X2Z256rm $rip, 1, $noreg, 0, $noreg
684 ; CHECK: $ymm0 = VBROADCASTSDYrr $xmm0
685 $ymm0 = VBROADCASTF32X2Z256rr $xmm0
686 ; CHECK: $ymm0 = VBROADCASTSDYrm $rip, 1, $noreg, 0, $noreg
687 $ymm0 = VBROADCASTSDZ256rm $rip, 1, $noreg, 0, $noreg
688 ; CHECK: $ymm0 = VBROADCASTSDYrr $xmm0
689 $ymm0 = VBROADCASTSDZ256rr $xmm0
690 ; CHECK: $ymm0 = VBROADCASTSSYrm $rip, 1, $noreg, 0, $noreg
691 $ymm0 = VBROADCASTSSZ256rm $rip, 1, $noreg, 0, $noreg
692 ; CHECK: $ymm0 = VBROADCASTSSYrr $xmm0
693 $ymm0 = VBROADCASTSSZ256rr $xmm0
694 ; CHECK: $ymm0 = VPBROADCASTBYrm $rip, 1, $noreg, 0, $noreg
695 $ymm0 = VPBROADCASTBZ256rm $rip, 1, $noreg, 0, $noreg
696 ; CHECK: $ymm0 = VPBROADCASTBYrr $xmm0
697 $ymm0 = VPBROADCASTBZ256rr $xmm0
698 ; CHECK: $ymm0 = VPBROADCASTDYrm $rip, 1, $noreg, 0, $noreg
699 $ymm0 = VPBROADCASTDZ256rm $rip, 1, $noreg, 0, $noreg
700 ; CHECK: $ymm0 = VPBROADCASTDYrr $xmm0
701 $ymm0 = VPBROADCASTDZ256rr $xmm0
702 ; CHECK: $ymm0 = VPBROADCASTWYrm $rip, 1, $noreg, 0, $noreg
703 $ymm0 = VPBROADCASTWZ256rm $rip, 1, $noreg, 0, $noreg
704 ; CHECK: $ymm0 = VPBROADCASTWYrr $xmm0
705 $ymm0 = VPBROADCASTWZ256rr $xmm0
706 ; CHECK: $ymm0 = VBROADCASTI128 $rip, 1, $noreg, 0, $noreg
707 $ymm0 = VBROADCASTI32X4Z256rm $rip, 1, $noreg, 0, $noreg
708 ; CHECK: $ymm0 = VPBROADCASTQYrm $rip, 1, $noreg, 0, $noreg
709 $ymm0 = VBROADCASTI32X2Z256rm $rip, 1, $noreg, 0, $noreg
710 ; CHECK: $ymm0 = VPBROADCASTQYrr $xmm0
711 $ymm0 = VBROADCASTI32X2Z256rr $xmm0
712 ; CHECK: $ymm0 = VPBROADCASTQYrm $rip, 1, $noreg, 0, $noreg
713 $ymm0 = VPBROADCASTQZ256rm $rip, 1, $noreg, 0, $noreg
714 ; CHECK: $ymm0 = VPBROADCASTQYrr $xmm0
715 $ymm0 = VPBROADCASTQZ256rr $xmm0
716 ; CHECK: $ymm0 = VPABSBYrm $rip, 1, $noreg, 0, $noreg
717 $ymm0 = VPABSBZ256rm $rip, 1, $noreg, 0, $noreg
718 ; CHECK: $ymm0 = VPABSBYrr $ymm0
719 $ymm0 = VPABSBZ256rr $ymm0
720 ; CHECK: $ymm0 = VPABSDYrm $rip, 1, $noreg, 0, $noreg
721 $ymm0 = VPABSDZ256rm $rip, 1, $noreg, 0, $noreg
722 ; CHECK: $ymm0 = VPABSDYrr $ymm0
723 $ymm0 = VPABSDZ256rr $ymm0
724 ; CHECK: $ymm0 = VPABSWYrm $rip, 1, $noreg, 0, $noreg
725 $ymm0 = VPABSWZ256rm $rip, 1, $noreg, 0, $noreg
726 ; CHECK: $ymm0 = VPABSWYrr $ymm0
727 $ymm0 = VPABSWZ256rr $ymm0
728 ; CHECK: $ymm0 = VPSADBWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
729 $ymm0 = VPSADBWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
730 ; CHECK: $ymm0 = VPSADBWYrr $ymm0, $ymm1
731 $ymm0 = VPSADBWZ256rr $ymm0, $ymm1
732 ; CHECK: $ymm0 = VPERMDYrm $ymm0, $rdi, 1, $noreg, 0, $noreg
733 $ymm0 = VPERMDZ256rm $ymm0, $rdi, 1, $noreg, 0, $noreg
734 ; CHECK: $ymm0 = VPERMDYrr $ymm1, $ymm0
735 $ymm0 = VPERMDZ256rr $ymm1, $ymm0
736 ; CHECK: $ymm0 = VPERMILPDYmi $rdi, 1, $noreg, 0, $noreg, 7
737 $ymm0 = VPERMILPDZ256mi $rdi, 1, $noreg, 0, $noreg, 7
738 ; CHECK: $ymm0 = VPERMILPDYri $ymm0, 7
739 $ymm0 = VPERMILPDZ256ri $ymm0, 7
740 ; CHECK: $ymm0 = VPERMILPDYrm $ymm0, $rdi, 1, $noreg, 0, $noreg
741 $ymm0 = VPERMILPDZ256rm $ymm0, $rdi, 1, $noreg, 0, $noreg
742 ; CHECK: $ymm0 = VPERMILPDYrr $ymm1, $ymm0
743 $ymm0 = VPERMILPDZ256rr $ymm1, $ymm0
744 ; CHECK: $ymm0 = VPERMILPSYmi $rdi, 1, $noreg, 0, $noreg, 7
745 $ymm0 = VPERMILPSZ256mi $rdi, 1, $noreg, 0, $noreg, 7
746 ; CHECK: $ymm0 = VPERMILPSYri $ymm0, 7
747 $ymm0 = VPERMILPSZ256ri $ymm0, 7
748 ; CHECK: $ymm0 = VPERMILPSYrm $ymm0, $rdi, 1, $noreg, 0, $noreg
749 $ymm0 = VPERMILPSZ256rm $ymm0, $rdi, 1, $noreg, 0, $noreg
750 ; CHECK: $ymm0 = VPERMILPSYrr $ymm1, $ymm0
751 $ymm0 = VPERMILPSZ256rr $ymm1, $ymm0
752 ; CHECK: $ymm0 = VPERMPDYmi $rdi, 1, $noreg, 0, $noreg, 7
753 $ymm0 = VPERMPDZ256mi $rdi, 1, $noreg, 0, $noreg, 7
754 ; CHECK: $ymm0 = VPERMPDYri $ymm0, 7
755 $ymm0 = VPERMPDZ256ri $ymm0, 7
756 ; CHECK: $ymm0 = VPERMPSYrm $ymm0, $rdi, 1, $noreg, 0, $noreg
757 $ymm0 = VPERMPSZ256rm $ymm0, $rdi, 1, $noreg, 0, $noreg
758 ; CHECK: $ymm0 = VPERMPSYrr $ymm1, $ymm0
759 $ymm0 = VPERMPSZ256rr $ymm1, $ymm0
760 ; CHECK: $ymm0 = VPERMQYmi $rdi, 1, $noreg, 0, $noreg, 7
761 $ymm0 = VPERMQZ256mi $rdi, 1, $noreg, 0, $noreg, 7
762 ; CHECK: $ymm0 = VPERMQYri $ymm0, 7
763 $ymm0 = VPERMQZ256ri $ymm0, 7
764 ; CHECK: $ymm0 = VPSLLDQYri $ymm0, 14
765 $ymm0 = VPSLLDQZ256ri $ymm0, 14
766 ; CHECK: $ymm0 = VPSLLDYri $ymm0, 7
767 $ymm0 = VPSLLDZ256ri $ymm0, 7
768 ; CHECK: $ymm0 = VPSLLDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
769 $ymm0 = VPSLLDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
770 ; CHECK: $ymm0 = VPSLLDYrr $ymm0, $xmm0
771 $ymm0 = VPSLLDZ256rr $ymm0, $xmm0
772 ; CHECK: $ymm0 = VPSLLQYri $ymm0, 7
773 $ymm0 = VPSLLQZ256ri $ymm0, 7
774 ; CHECK: $ymm0 = VPSLLQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
775 $ymm0 = VPSLLQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
776 ; CHECK: $ymm0 = VPSLLQYrr $ymm0, $xmm0
777 $ymm0 = VPSLLQZ256rr $ymm0, $xmm0
778 ; CHECK: $ymm0 = VPSLLVDYrm $ymm0, $rip, 1, $noreg, 0, $noreg
779 $ymm0 = VPSLLVDZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
780 ; CHECK: $ymm0 = VPSLLVDYrr $ymm0, $ymm0
781 $ymm0 = VPSLLVDZ256rr $ymm0, $ymm0
782 ; CHECK: $ymm0 = VPSLLVQYrm $ymm0, $rip, 1, $noreg, 0, $noreg
783 $ymm0 = VPSLLVQZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
784 ; CHECK: $ymm0 = VPSLLVQYrr $ymm0, $ymm0
785 $ymm0 = VPSLLVQZ256rr $ymm0, $ymm0
786 ; CHECK: $ymm0 = VPSLLWYri $ymm0, 7
787 $ymm0 = VPSLLWZ256ri $ymm0, 7
788 ; CHECK: $ymm0 = VPSLLWYrm $ymm0, $rip, 1, $noreg, 0, $noreg
789 $ymm0 = VPSLLWZ256rm $ymm0, $rip, 1, $noreg, 0, $noreg
790 ; CHECK: $ymm0 = VPSLLWYrr $ymm0, $xmm0
791 $ymm0 = VPSLLWZ256rr $ymm0, $xmm0
792 ; CHECK: $ymm0 = VCVTDQ2PDYrm $rdi, 1, $noreg, 0, $noreg
793 $ymm0 = VCVTDQ2PDZ256rm $rdi, 1, $noreg, 0, $noreg
794 ; CHECK: $ymm0 = VCVTDQ2PDYrr $xmm0
795 $ymm0 = VCVTDQ2PDZ256rr $xmm0
796 ; CHECK: $ymm0 = VCVTDQ2PSYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
797 $ymm0 = VCVTDQ2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
798 ; CHECK: $ymm0 = VCVTDQ2PSYrr $ymm0, implicit $mxcsr
799 $ymm0 = VCVTDQ2PSZ256rr $ymm0, implicit $mxcsr
800 ; CHECK: $xmm0 = VCVTPD2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
801 $xmm0 = VCVTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
802 ; CHECK: $xmm0 = VCVTPD2DQYrr $ymm0, implicit $mxcsr
803 $xmm0 = VCVTPD2DQZ256rr $ymm0, implicit $mxcsr
804 ; CHECK: $xmm0 = VCVTPD2PSYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
805 $xmm0 = VCVTPD2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
806 ; CHECK: $xmm0 = VCVTPD2PSYrr $ymm0, implicit $mxcsr
807 $xmm0 = VCVTPD2PSZ256rr $ymm0, implicit $mxcsr
808 ; CHECK: $ymm0 = VCVTPS2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
809 $ymm0 = VCVTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
810 ; CHECK: $ymm0 = VCVTPS2DQYrr $ymm0, implicit $mxcsr
811 $ymm0 = VCVTPS2DQZ256rr $ymm0, implicit $mxcsr
812 ; CHECK: $ymm0 = VCVTPS2PDYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
813 $ymm0 = VCVTPS2PDZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
814 ; CHECK: $ymm0 = VCVTPS2PDYrr $xmm0, implicit $mxcsr
815 $ymm0 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
816 ; CHECK: VCVTPS2PHYmr $rdi, 1, $noreg, 0, $noreg, $ymm0, 0, implicit $mxcsr
817 VCVTPS2PHZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm0, 0, implicit $mxcsr
818 ; CHECK: $xmm0 = VCVTPS2PHYrr $ymm0, 0, implicit $mxcsr
819 $xmm0 = VCVTPS2PHZ256rr $ymm0, 0, implicit $mxcsr
820 ; CHECK: $ymm0 = VCVTPH2PSYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
821 $ymm0 = VCVTPH2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
822 ; CHECK: $ymm0 = VCVTPH2PSYrr $xmm0, implicit $mxcsr
823 $ymm0 = VCVTPH2PSZ256rr $xmm0, implicit $mxcsr
824 ; CHECK: $xmm0 = VCVTTPD2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
825 $xmm0 = VCVTTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
826 ; CHECK: $xmm0 = VCVTTPD2DQYrr $ymm0, implicit $mxcsr
827 $xmm0 = VCVTTPD2DQZ256rr $ymm0, implicit $mxcsr
828 ; CHECK: $ymm0 = VCVTTPS2DQYrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
829 $ymm0 = VCVTTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
830 ; CHECK: $ymm0 = VCVTTPS2DQYrr $ymm0, implicit $mxcsr
831 $ymm0 = VCVTTPS2DQZ256rr $ymm0, implicit $mxcsr
832 ; CHECK: $ymm0 = VSQRTPDYm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
833 $ymm0 = VSQRTPDZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
834 ; CHECK: $ymm0 = VSQRTPDYr $ymm0, implicit $mxcsr
835 $ymm0 = VSQRTPDZ256r $ymm0, implicit $mxcsr
836 ; CHECK: $ymm0 = VSQRTPSYm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
837 $ymm0 = VSQRTPSZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
838 ; CHECK: $ymm0 = VSQRTPSYr $ymm0, implicit $mxcsr
839 $ymm0 = VSQRTPSZ256r $ymm0, implicit $mxcsr
840 ; CHECK: $ymm0 = VPALIGNRYrmi $ymm0, $rdi, 1, $noreg, 0, $noreg, 1
841 $ymm0 = VPALIGNRZ256rmi $ymm0, $rdi, 1, $noreg, 0, $noreg, 1
842 ; CHECK: $ymm0 = VPALIGNRYrri $ymm0, $ymm1, 1
843 $ymm0 = VPALIGNRZ256rri $ymm0, $ymm1, 1
844 ; CHECK: $ymm0 = VMOVUPSYrm $rdi, 1, $noreg, 0, $noreg
845 $ymm0 = VMOVUPSZ256rm $rdi, 1, $noreg, 0, $noreg
846 ; CHECK: $ymm0 = VMOVUPSYrr $ymm0
847 $ymm0 = VMOVUPSZ256rr $ymm0
848 ; CHECK: $ymm0 = VPSHUFBYrm $ymm0, $rdi, 1, $noreg, 0, $noreg
849 $ymm0 = VPSHUFBZ256rm $ymm0, $rdi, 1, $noreg, 0, $noreg
850 ; CHECK: $ymm0 = VPSHUFBYrr $ymm0, $ymm1
851 $ymm0 = VPSHUFBZ256rr $ymm0, $ymm1
852 ; CHECK: $ymm0 = VPSHUFDYmi $rdi, 1, $noreg, 0, $noreg, -24
853 $ymm0 = VPSHUFDZ256mi $rdi, 1, $noreg, 0, $noreg, -24
854 ; CHECK: $ymm0 = VPSHUFDYri $ymm0, -24
855 $ymm0 = VPSHUFDZ256ri $ymm0, -24
856 ; CHECK: $ymm0 = VPSHUFHWYmi $rdi, 1, $noreg, 0, $noreg, -24
857 $ymm0 = VPSHUFHWZ256mi $rdi, 1, $noreg, 0, $noreg, -24
858 ; CHECK: $ymm0 = VPSHUFHWYri $ymm0, -24
859 $ymm0 = VPSHUFHWZ256ri $ymm0, -24
860 ; CHECK: $ymm0 = VPSHUFLWYmi $rdi, 1, $noreg, 0, $noreg, -24
861 $ymm0 = VPSHUFLWZ256mi $rdi, 1, $noreg, 0, $noreg, -24
862 ; CHECK: $ymm0 = VPSHUFLWYri $ymm0, -24
863 $ymm0 = VPSHUFLWZ256ri $ymm0, -24
864 ; CHECK: $ymm0 = VSHUFPDYrmi $ymm0, $rdi, 1, $noreg, 0, $noreg, -24
865 $ymm0 = VSHUFPDZ256rmi $ymm0, $rdi, 1, $noreg, 0, $noreg, -24
866 ; CHECK: $ymm0 = VSHUFPDYrri $ymm0, $ymm1, -24
867 $ymm0 = VSHUFPDZ256rri $ymm0, $ymm1, -24
868 ; CHECK: $ymm0 = VSHUFPSYrmi $ymm0, $rdi, 1, $noreg, 0, $noreg, -24
869 $ymm0 = VSHUFPSZ256rmi $ymm0, $rdi, 1, $noreg, 0, $noreg, -24
870 ; CHECK: $ymm0 = VSHUFPSYrri $ymm0, $ymm1, -24
871 $ymm0 = VSHUFPSZ256rri $ymm0, $ymm1, -24
872 ; CHECK: $ymm0 = VROUNDPDYm $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
873 $ymm0 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
874 ; CHECK: $ymm0 = VROUNDPDYr $ymm0, 15, implicit $mxcsr
875 $ymm0 = VRNDSCALEPDZ256rri $ymm0, 15, implicit $mxcsr
876 ; CHECK: $ymm0 = VROUNDPSYm $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
877 $ymm0 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
878 ; CHECK: $ymm0 = VROUNDPSYr $ymm0, 15, implicit $mxcsr
879 $ymm0 = VRNDSCALEPSZ256rri $ymm0, 15, implicit $mxcsr
880 ; CHECK: $ymm0 = VPERM2F128rm $ymm0, $rip, 1, $noreg, 0, $noreg, 32
881 $ymm0 = VSHUFF32X4Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228
882 ; CHECK: $ymm0 = VPERM2F128rr $ymm0, $ymm1, 32
883 $ymm0 = VSHUFF32X4Z256rri $ymm0, $ymm1, 228
884 ; CHECK: $ymm0 = VPERM2F128rm $ymm0, $rip, 1, $noreg, 0, $noreg, 32
885 $ymm0 = VSHUFF64X2Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228
886 ; CHECK: $ymm0 = VPERM2F128rr $ymm0, $ymm1, 32
887 $ymm0 = VSHUFF64X2Z256rri $ymm0, $ymm1, 228
888 ; CHECK: $ymm0 = VPERM2I128rm $ymm0, $rip, 1, $noreg, 0, $noreg, 32
889 $ymm0 = VSHUFI32X4Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228
890 ; CHECK: $ymm0 = VPERM2I128rr $ymm0, $ymm1, 32
891 $ymm0 = VSHUFI32X4Z256rri $ymm0, $ymm1, 228
892 ; CHECK: $ymm0 = VPERM2I128rm $ymm0, $rip, 1, $noreg, 0, $noreg, 32
893 $ymm0 = VSHUFI64X2Z256rmi $ymm0, $rip, 1, $noreg, 0, $noreg, 228
894 ; CHECK: $ymm0 = VPERM2I128rr $ymm0, $ymm1, 32
895 $ymm0 = VSHUFI64X2Z256rri $ymm0, $ymm1, 228
897 RET64
898 ...
899 ---
900 # CHECK-LABEL: name: evex_z128_to_vex_test
901 # CHECK: bb.0:
903 name: evex_z128_to_vex_test
904 body: |
905 bb.0:
906 ; CHECK: VMOVAPDmr $rdi, 1, $noreg, 0, $noreg, $xmm0
907 VMOVAPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
908 ; CHECK: $xmm0 = VMOVAPDrm $rip, 1, $noreg, 0, $noreg
909 $xmm0 = VMOVAPDZ128rm $rip, 1, $noreg, 0, $noreg
910 ; CHECK: $xmm0 = VMOVAPDrr $xmm0
911 $xmm0 = VMOVAPDZ128rr $xmm0
912 ; CHECK: VMOVAPSmr $rdi, 1, $noreg, 0, $noreg, $xmm0
913 VMOVAPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
914 ; CHECK: $xmm0 = VMOVAPSrm $rip, 1, $noreg, 0, $noreg
915 $xmm0 = VMOVAPSZ128rm $rip, 1, $noreg, 0, $noreg
916 ; CHECK: $xmm0 = VMOVAPSrr $xmm0
917 $xmm0 = VMOVAPSZ128rr $xmm0
918 ; CHECK: VMOVDQAmr $rdi, 1, $noreg, 0, $noreg, $xmm0
919 VMOVDQA32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
920 ; CHECK: $xmm0 = VMOVDQArm $rip, 1, $noreg, 0, $noreg
921 $xmm0 = VMOVDQA32Z128rm $rip, 1, $noreg, 0, $noreg
922 ; CHECK: $xmm0 = VMOVDQArr $xmm0
923 $xmm0 = VMOVDQA32Z128rr $xmm0
924 ; CHECK: VMOVDQAmr $rdi, 1, $noreg, 0, $noreg, $xmm0
925 VMOVDQA64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
926 ; CHECK: $xmm0 = VMOVDQArm $rip, 1, $noreg, 0, $noreg
927 $xmm0 = VMOVDQA64Z128rm $rip, 1, $noreg, 0, $noreg
928 ; CHECK: $xmm0 = VMOVDQArr $xmm0
929 $xmm0 = VMOVDQA64Z128rr $xmm0
930 ; CHECK: VMOVDQUmr $rdi, 1, $noreg, 0, $noreg, $xmm0
931 VMOVDQU16Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
932 ; CHECK: $xmm0 = VMOVDQUrm $rip, 1, $noreg, 0, $noreg
933 $xmm0 = VMOVDQU16Z128rm $rip, 1, $noreg, 0, $noreg
934 ; CHECK: $xmm0 = VMOVDQUrr $xmm0
935 $xmm0 = VMOVDQU16Z128rr $xmm0
936 ; CHECK: VMOVDQUmr $rdi, 1, $noreg, 0, $noreg, $xmm0
937 VMOVDQU32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
938 ; CHECK: $xmm0 = VMOVDQUrm $rip, 1, $noreg, 0, $noreg
939 $xmm0 = VMOVDQU32Z128rm $rip, 1, $noreg, 0, $noreg
940 ; CHECK: $xmm0 = VMOVDQUrr $xmm0
941 $xmm0 = VMOVDQU32Z128rr $xmm0
942 ; CHECK: VMOVDQUmr $rdi, 1, $noreg, 0, $noreg, $xmm0
943 VMOVDQU64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
944 ; CHECK: $xmm0 = VMOVDQUrm $rip, 1, $noreg, 0, $noreg
945 $xmm0 = VMOVDQU64Z128rm $rip, 1, $noreg, 0, $noreg
946 ; CHECK: $xmm0 = VMOVDQUrr $xmm0
947 $xmm0 = VMOVDQU64Z128rr $xmm0
948 ; CHECK: VMOVDQUmr $rdi, 1, $noreg, 0, $noreg, $xmm0
949 VMOVDQU8Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
950 ; CHECK: $xmm0 = VMOVDQUrm $rip, 1, $noreg, 0, $noreg
951 $xmm0 = VMOVDQU8Z128rm $rip, 1, $noreg, 0, $noreg
952 ; CHECK: $xmm0 = VMOVDQUrr $xmm0
953 $xmm0 = VMOVDQU8Z128rr $xmm0
954 ; CHECK: $xmm0 = VMOVNTDQArm $rip, 1, $noreg, 0, $noreg
955 $xmm0 = VMOVNTDQAZ128rm $rip, 1, $noreg, 0, $noreg
956 ; CHECK: VMOVUPDmr $rdi, 1, $noreg, 0, $noreg, $xmm0
957 VMOVUPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
958 ; CHECK: $xmm0 = VMOVUPDrm $rip, 1, $noreg, 0, $noreg
959 $xmm0 = VMOVUPDZ128rm $rip, 1, $noreg, 0, $noreg
960 ; CHECK: $xmm0 = VMOVUPDrr $xmm0
961 $xmm0 = VMOVUPDZ128rr $xmm0
962 ; CHECK: VMOVUPSmr $rdi, 1, $noreg, 0, $noreg, $xmm0
963 VMOVUPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
964 ; CHECK: $xmm0 = VMOVUPSrm $rip, 1, $noreg, 0, $noreg
965 $xmm0 = VMOVUPSZ128rm $rip, 1, $noreg, 0, $noreg
966 ; CHECK: $xmm0 = VMOVUPSrr $xmm0
967 $xmm0 = VMOVUPSZ128rr $xmm0
968 ; CHECK: VMOVNTDQmr $rdi, 1, $noreg, 0, $noreg, $xmm0
969 VMOVNTDQZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
970 ; CHECK: VMOVNTPDmr $rdi, 1, $noreg, 0, $noreg, $xmm0
971 VMOVNTPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
972 ; CHECK: VMOVNTPSmr $rdi, 1, $noreg, 0, $noreg, $xmm0
973 VMOVNTPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
974 ; CHECK: $xmm0 = VPMOVSXBDrm $rip, 1, $noreg, 0, $noreg
975 $xmm0 = VPMOVSXBDZ128rm $rip, 1, $noreg, 0, $noreg
976 ; CHECK: $xmm0 = VPMOVSXBDrr $xmm0
977 $xmm0 = VPMOVSXBDZ128rr $xmm0
978 ; CHECK: $xmm0 = VPMOVSXBQrm $rip, 1, $noreg, 0, $noreg
979 $xmm0 = VPMOVSXBQZ128rm $rip, 1, $noreg, 0, $noreg
980 ; CHECK: $xmm0 = VPMOVSXBQrr $xmm0
981 $xmm0 = VPMOVSXBQZ128rr $xmm0
982 ; CHECK: $xmm0 = VPMOVSXBWrm $rip, 1, $noreg, 0, $noreg
983 $xmm0 = VPMOVSXBWZ128rm $rip, 1, $noreg, 0, $noreg
984 ; CHECK: $xmm0 = VPMOVSXBWrr $xmm0
985 $xmm0 = VPMOVSXBWZ128rr $xmm0
986 ; CHECK: $xmm0 = VPMOVSXDQrm $rip, 1, $noreg, 0, $noreg
987 $xmm0 = VPMOVSXDQZ128rm $rip, 1, $noreg, 0, $noreg
988 ; CHECK: $xmm0 = VPMOVSXDQrr $xmm0
989 $xmm0 = VPMOVSXDQZ128rr $xmm0
990 ; CHECK: $xmm0 = VPMOVSXWDrm $rip, 1, $noreg, 0, $noreg
991 $xmm0 = VPMOVSXWDZ128rm $rip, 1, $noreg, 0, $noreg
992 ; CHECK: $xmm0 = VPMOVSXWDrr $xmm0
993 $xmm0 = VPMOVSXWDZ128rr $xmm0
994 ; CHECK: $xmm0 = VPMOVSXWQrm $rip, 1, $noreg, 0, $noreg
995 $xmm0 = VPMOVSXWQZ128rm $rip, 1, $noreg, 0, $noreg
996 ; CHECK: $xmm0 = VPMOVSXWQrr $xmm0
997 $xmm0 = VPMOVSXWQZ128rr $xmm0
998 ; CHECK: $xmm0 = VPMOVZXBDrm $rip, 1, $noreg, 0, $noreg
999 $xmm0 = VPMOVZXBDZ128rm $rip, 1, $noreg, 0, $noreg
1000 ; CHECK: $xmm0 = VPMOVZXBDrr $xmm0
1001 $xmm0 = VPMOVZXBDZ128rr $xmm0
1002 ; CHECK: $xmm0 = VPMOVZXBQrm $rip, 1, $noreg, 0, $noreg
1003 $xmm0 = VPMOVZXBQZ128rm $rip, 1, $noreg, 0, $noreg
1004 ; CHECK: $xmm0 = VPMOVZXBQrr $xmm0
1005 $xmm0 = VPMOVZXBQZ128rr $xmm0
1006 ; CHECK: $xmm0 = VPMOVZXBWrm $rip, 1, $noreg, 0, $noreg
1007 $xmm0 = VPMOVZXBWZ128rm $rip, 1, $noreg, 0, $noreg
1008 ; CHECK: $xmm0 = VPMOVZXBWrr $xmm0
1009 $xmm0 = VPMOVZXBWZ128rr $xmm0
1010 ; CHECK: $xmm0 = VPMOVZXDQrm $rip, 1, $noreg, 0, $noreg
1011 $xmm0 = VPMOVZXDQZ128rm $rip, 1, $noreg, 0, $noreg
1012 ; CHECK: $xmm0 = VPMOVZXDQrr $xmm0
1013 $xmm0 = VPMOVZXDQZ128rr $xmm0
1014 ; CHECK: $xmm0 = VPMOVZXWDrm $rip, 1, $noreg, 0, $noreg
1015 $xmm0 = VPMOVZXWDZ128rm $rip, 1, $noreg, 0, $noreg
1016 ; CHECK: $xmm0 = VPMOVZXWDrr $xmm0
1017 $xmm0 = VPMOVZXWDZ128rr $xmm0
1018 ; CHECK: $xmm0 = VPMOVZXWQrm $rip, 1, $noreg, 0, $noreg
1019 $xmm0 = VPMOVZXWQZ128rm $rip, 1, $noreg, 0, $noreg
1020 ; CHECK: $xmm0 = VPMOVZXWQrr $xmm0
1021 $xmm0 = VPMOVZXWQZ128rr $xmm0
1022 ; CHECK: VMOVHPDmr $rdi, 1, $noreg, 0, $noreg, $xmm0
1023 VMOVHPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
1024 ; CHECK: $xmm0 = VMOVHPDrm $xmm0, $rdi, 1, $noreg, 0, $noreg
1025 $xmm0 = VMOVHPDZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg
1026 ; CHECK: VMOVHPSmr $rdi, 1, $noreg, 0, $noreg, $xmm0
1027 VMOVHPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
1028 ; CHECK: $xmm0 = VMOVHPSrm $xmm0, $rdi, 1, $noreg, 0, $noreg
1029 $xmm0 = VMOVHPSZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg
1030 ; CHECK: VMOVLPDmr $rdi, 1, $noreg, 0, $noreg, $xmm0
1031 VMOVLPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
1032 ; CHECK: $xmm0 = VMOVLPDrm $xmm0, $rdi, 1, $noreg, 0, $noreg
1033 $xmm0 = VMOVLPDZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg
1034 ; CHECK: VMOVLPSmr $rdi, 1, $noreg, 0, $noreg, $xmm0
1035 VMOVLPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0
1036 ; CHECK: $xmm0 = VMOVLPSrm $xmm0, $rdi, 1, $noreg, 0, $noreg
1037 $xmm0 = VMOVLPSZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg
1038 ; CHECK: $xmm0 = VMAXCPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1039 $xmm0 = VMAXCPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1040 ; CHECK: $xmm0 = VMAXCPDrr $xmm0, $xmm1, implicit $mxcsr
1041 $xmm0 = VMAXCPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1042 ; CHECK: $xmm0 = VMAXCPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1043 $xmm0 = VMAXCPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1044 ; CHECK: $xmm0 = VMAXCPSrr $xmm0, $xmm1, implicit $mxcsr
1045 $xmm0 = VMAXCPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1046 ; CHECK: $xmm0 = VMAXPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1047 $xmm0 = VMAXPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1048 ; CHECK: $xmm0 = VMAXPDrr $xmm0, $xmm1, implicit $mxcsr
1049 $xmm0 = VMAXPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1050 ; CHECK: $xmm0 = VMAXPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1051 $xmm0 = VMAXPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1052 ; CHECK: $xmm0 = VMAXPSrr $xmm0, $xmm1, implicit $mxcsr
1053 $xmm0 = VMAXPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1054 ; CHECK: $xmm0 = VMINCPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1055 $xmm0 = VMINCPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1056 ; CHECK: $xmm0 = VMINCPDrr $xmm0, $xmm1, implicit $mxcsr
1057 $xmm0 = VMINCPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1058 ; CHECK: $xmm0 = VMINCPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1059 $xmm0 = VMINCPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1060 ; CHECK: $xmm0 = VMINCPSrr $xmm0, $xmm1, implicit $mxcsr
1061 $xmm0 = VMINCPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1062 ; CHECK: $xmm0 = VMINPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1063 $xmm0 = VMINPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1064 ; CHECK: $xmm0 = VMINPDrr $xmm0, $xmm1, implicit $mxcsr
1065 $xmm0 = VMINPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1066 ; CHECK: $xmm0 = VMINPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1067 $xmm0 = VMINPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1068 ; CHECK: $xmm0 = VMINPSrr $xmm0, $xmm1, implicit $mxcsr
1069 $xmm0 = VMINPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1070 ; CHECK: $xmm0 = VMULPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1071 $xmm0 = VMULPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1072 ; CHECK: $xmm0 = VMULPDrr $xmm0, $xmm1, implicit $mxcsr
1073 $xmm0 = VMULPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1074 ; CHECK: $xmm0 = VMULPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1075 $xmm0 = VMULPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1076 ; CHECK: $xmm0 = VMULPSrr $xmm0, $xmm1, implicit $mxcsr
1077 $xmm0 = VMULPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1078 ; CHECK: $xmm0 = VORPDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1079 $xmm0 = VORPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1080 ; CHECK: $xmm0 = VORPDrr $xmm0, $xmm1
1081 $xmm0 = VORPDZ128rr $xmm0, $xmm1
1082 ; CHECK: $xmm0 = VORPSrm $xmm0, $rip, 1, $noreg, 0, $noreg
1083 $xmm0 = VORPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1084 ; CHECK: $xmm0 = VORPSrr $xmm0, $xmm1
1085 $xmm0 = VORPSZ128rr $xmm0, $xmm1
1086 ; CHECK: $xmm0 = VPADDBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1087 $xmm0 = VPADDBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1088 ; CHECK: $xmm0 = VPADDBrr $xmm0, $xmm1
1089 $xmm0 = VPADDBZ128rr $xmm0, $xmm1
1090 ; CHECK: $xmm0 = VPADDDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1091 $xmm0 = VPADDDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1092 ; CHECK: $xmm0 = VPADDDrr $xmm0, $xmm1
1093 $xmm0 = VPADDDZ128rr $xmm0, $xmm1
1094 ; CHECK: $xmm0 = VPADDQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1095 $xmm0 = VPADDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1096 ; CHECK: $xmm0 = VPADDQrr $xmm0, $xmm1
1097 $xmm0 = VPADDQZ128rr $xmm0, $xmm1
1098 ; CHECK: $xmm0 = VPADDSBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1099 $xmm0 = VPADDSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1100 ; CHECK: $xmm0 = VPADDSBrr $xmm0, $xmm1
1101 $xmm0 = VPADDSBZ128rr $xmm0, $xmm1
1102 ; CHECK: $xmm0 = VPADDSWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1103 $xmm0 = VPADDSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1104 ; CHECK: $xmm0 = VPADDSWrr $xmm0, $xmm1
1105 $xmm0 = VPADDSWZ128rr $xmm0, $xmm1
1106 ; CHECK: $xmm0 = VPADDUSBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1107 $xmm0 = VPADDUSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1108 ; CHECK: $xmm0 = VPADDUSBrr $xmm0, $xmm1
1109 $xmm0 = VPADDUSBZ128rr $xmm0, $xmm1
1110 ; CHECK: $xmm0 = VPADDUSWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1111 $xmm0 = VPADDUSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1112 ; CHECK: $xmm0 = VPADDUSWrr $xmm0, $xmm1
1113 $xmm0 = VPADDUSWZ128rr $xmm0, $xmm1
1114 ; CHECK: $xmm0 = VPADDWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1115 $xmm0 = VPADDWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1116 ; CHECK: $xmm0 = VPADDWrr $xmm0, $xmm1
1117 $xmm0 = VPADDWZ128rr $xmm0, $xmm1
1118 ; CHECK: $xmm0 = VPANDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1119 $xmm0 = VPANDDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1120 ; CHECK: $xmm0 = VPANDrr $xmm0, $xmm1
1121 $xmm0 = VPANDDZ128rr $xmm0, $xmm1
1122 ; CHECK: $xmm0 = VPANDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1123 $xmm0 = VPANDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1124 ; CHECK: $xmm0 = VPANDrr $xmm0, $xmm1
1125 $xmm0 = VPANDQZ128rr $xmm0, $xmm1
1126 ; CHECK: $xmm0 = VPANDNrm $xmm0, $rip, 1, $noreg, 0, $noreg
1127 $xmm0 = VPANDNDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1128 ; CHECK: $xmm0 = VPANDNrr $xmm0, $xmm1
1129 $xmm0 = VPANDNDZ128rr $xmm0, $xmm1
1130 ; CHECK: $xmm0 = VPANDNrm $xmm0, $rip, 1, $noreg, 0, $noreg
1131 $xmm0 = VPANDNQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1132 ; CHECK: $xmm0 = VPANDNrr $xmm0, $xmm1
1133 $xmm0 = VPANDNQZ128rr $xmm0, $xmm1
1134 ; CHECK: $xmm0 = VPAVGBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1135 $xmm0 = VPAVGBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1136 ; CHECK: $xmm0 = VPAVGBrr $xmm0, $xmm1
1137 $xmm0 = VPAVGBZ128rr $xmm0, $xmm1
1138 ; CHECK: $xmm0 = VPAVGWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1139 $xmm0 = VPAVGWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1140 ; CHECK: $xmm0 = VPAVGWrr $xmm0, $xmm1
1141 $xmm0 = VPAVGWZ128rr $xmm0, $xmm1
1142 ; CHECK: $xmm0 = VPMAXSBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1143 $xmm0 = VPMAXSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1144 ; CHECK: $xmm0 = VPMAXSBrr $xmm0, $xmm1
1145 $xmm0 = VPMAXSBZ128rr $xmm0, $xmm1
1146 ; CHECK: $xmm0 = VPMAXSDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1147 $xmm0 = VPMAXSDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1148 ; CHECK: $xmm0 = VPMAXSDrr $xmm0, $xmm1
1149 $xmm0 = VPMAXSDZ128rr $xmm0, $xmm1
1150 ; CHECK: $xmm0 = VPMAXSWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1151 $xmm0 = VPMAXSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1152 ; CHECK: $xmm0 = VPMAXSWrr $xmm0, $xmm1
1153 $xmm0 = VPMAXSWZ128rr $xmm0, $xmm1
1154 ; CHECK: $xmm0 = VPMAXUBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1155 $xmm0 = VPMAXUBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1156 ; CHECK: $xmm0 = VPMAXUBrr $xmm0, $xmm1
1157 $xmm0 = VPMAXUBZ128rr $xmm0, $xmm1
1158 ; CHECK: $xmm0 = VPMAXUDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1159 $xmm0 = VPMAXUDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1160 ; CHECK: $xmm0 = VPMAXUDrr $xmm0, $xmm1
1161 $xmm0 = VPMAXUDZ128rr $xmm0, $xmm1
1162 ; CHECK: $xmm0 = VPMAXUWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1163 $xmm0 = VPMAXUWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1164 ; CHECK: $xmm0 = VPMAXUWrr $xmm0, $xmm1
1165 $xmm0 = VPMAXUWZ128rr $xmm0, $xmm1
1166 ; CHECK: $xmm0 = VPMINSBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1167 $xmm0 = VPMINSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1168 ; CHECK: $xmm0 = VPMINSBrr $xmm0, $xmm1
1169 $xmm0 = VPMINSBZ128rr $xmm0, $xmm1
1170 ; CHECK: $xmm0 = VPMINSDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1171 $xmm0 = VPMINSDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1172 ; CHECK: $xmm0 = VPMINSDrr $xmm0, $xmm1
1173 $xmm0 = VPMINSDZ128rr $xmm0, $xmm1
1174 ; CHECK: $xmm0 = VPMINSWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1175 $xmm0 = VPMINSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1176 ; CHECK: $xmm0 = VPMINSWrr $xmm0, $xmm1
1177 $xmm0 = VPMINSWZ128rr $xmm0, $xmm1
1178 ; CHECK: $xmm0 = VPMINUBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1179 $xmm0 = VPMINUBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1180 ; CHECK: $xmm0 = VPMINUBrr $xmm0, $xmm1
1181 $xmm0 = VPMINUBZ128rr $xmm0, $xmm1
1182 ; CHECK: $xmm0 = VPMINUDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1183 $xmm0 = VPMINUDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1184 ; CHECK: $xmm0 = VPMINUDrr $xmm0, $xmm1
1185 $xmm0 = VPMINUDZ128rr $xmm0, $xmm1
1186 ; CHECK: $xmm0 = VPMINUWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1187 $xmm0 = VPMINUWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1188 ; CHECK: $xmm0 = VPMINUWrr $xmm0, $xmm1
1189 $xmm0 = VPMINUWZ128rr $xmm0, $xmm1
1190 ; CHECK: $xmm0 = VPMULDQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1191 $xmm0 = VPMULDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1192 ; CHECK: $xmm0 = VPMULDQrr $xmm0, $xmm1
1193 $xmm0 = VPMULDQZ128rr $xmm0, $xmm1
1194 ; CHECK: $xmm0 = VPMULHRSWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1195 $xmm0 = VPMULHRSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1196 ; CHECK: $xmm0 = VPMULHRSWrr $xmm0, $xmm1
1197 $xmm0 = VPMULHRSWZ128rr $xmm0, $xmm1
1198 ; CHECK: $xmm0 = VPMULHUWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1199 $xmm0 = VPMULHUWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1200 ; CHECK: $xmm0 = VPMULHUWrr $xmm0, $xmm1
1201 $xmm0 = VPMULHUWZ128rr $xmm0, $xmm1
1202 ; CHECK: $xmm0 = VPMULHWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1203 $xmm0 = VPMULHWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1204 ; CHECK: $xmm0 = VPMULHWrr $xmm0, $xmm1
1205 $xmm0 = VPMULHWZ128rr $xmm0, $xmm1
1206 ; CHECK: $xmm0 = VPMULLDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1207 $xmm0 = VPMULLDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1208 ; CHECK: $xmm0 = VPMULLDrr $xmm0, $xmm1
1209 $xmm0 = VPMULLDZ128rr $xmm0, $xmm1
1210 ; CHECK: $xmm0 = VPMULLWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1211 $xmm0 = VPMULLWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1212 ; CHECK: $xmm0 = VPMULLWrr $xmm0, $xmm1
1213 $xmm0 = VPMULLWZ128rr $xmm0, $xmm1
1214 ; CHECK: $xmm0 = VPMULUDQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1215 $xmm0 = VPMULUDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1216 ; CHECK: $xmm0 = VPMULUDQrr $xmm0, $xmm1
1217 $xmm0 = VPMULUDQZ128rr $xmm0, $xmm1
1218 ; CHECK: $xmm0 = VPORrm $xmm0, $rip, 1, $noreg, 0, $noreg
1219 $xmm0 = VPORDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1220 ; CHECK: $xmm0 = VPORrr $xmm0, $xmm1
1221 $xmm0 = VPORDZ128rr $xmm0, $xmm1
1222 ; CHECK: $xmm0 = VPORrm $xmm0, $rip, 1, $noreg, 0, $noreg
1223 $xmm0 = VPORQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1224 ; CHECK: $xmm0 = VPORrr $xmm0, $xmm1
1225 $xmm0 = VPORQZ128rr $xmm0, $xmm1
1226 ; CHECK: $xmm0 = VPSUBBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1227 $xmm0 = VPSUBBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1228 ; CHECK: $xmm0 = VPSUBBrr $xmm0, $xmm1
1229 $xmm0 = VPSUBBZ128rr $xmm0, $xmm1
1230 ; CHECK: $xmm0 = VPSUBDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1231 $xmm0 = VPSUBDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1232 ; CHECK: $xmm0 = VPSUBDrr $xmm0, $xmm1
1233 $xmm0 = VPSUBDZ128rr $xmm0, $xmm1
1234 ; CHECK: $xmm0 = VPSUBQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1235 $xmm0 = VPSUBQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1236 ; CHECK: $xmm0 = VPSUBQrr $xmm0, $xmm1
1237 $xmm0 = VPSUBQZ128rr $xmm0, $xmm1
1238 ; CHECK: $xmm0 = VPSUBSBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1239 $xmm0 = VPSUBSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1240 ; CHECK: $xmm0 = VPSUBSBrr $xmm0, $xmm1
1241 $xmm0 = VPSUBSBZ128rr $xmm0, $xmm1
1242 ; CHECK: $xmm0 = VPSUBSWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1243 $xmm0 = VPSUBSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1244 ; CHECK: $xmm0 = VPSUBSWrr $xmm0, $xmm1
1245 $xmm0 = VPSUBSWZ128rr $xmm0, $xmm1
1246 ; CHECK: $xmm0 = VPSUBUSBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1247 $xmm0 = VPSUBUSBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1248 ; CHECK: $xmm0 = VPSUBUSBrr $xmm0, $xmm1
1249 $xmm0 = VPSUBUSBZ128rr $xmm0, $xmm1
1250 ; CHECK: $xmm0 = VPSUBUSWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1251 $xmm0 = VPSUBUSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1252 ; CHECK: $xmm0 = VPSUBUSWrr $xmm0, $xmm1
1253 $xmm0 = VPSUBUSWZ128rr $xmm0, $xmm1
1254 ; CHECK: $xmm0 = VPSUBWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1255 $xmm0 = VPSUBWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1256 ; CHECK: $xmm0 = VPSUBWrr $xmm0, $xmm1
1257 $xmm0 = VPSUBWZ128rr $xmm0, $xmm1
1258 ; CHECK: $xmm0 = VADDPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1259 $xmm0 = VADDPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1260 ; CHECK: $xmm0 = VADDPDrr $xmm0, $xmm1, implicit $mxcsr
1261 $xmm0 = VADDPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1262 ; CHECK: $xmm0 = VADDPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1263 $xmm0 = VADDPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1264 ; CHECK: $xmm0 = VADDPSrr $xmm0, $xmm1, implicit $mxcsr
1265 $xmm0 = VADDPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1266 ; CHECK: $xmm0 = VANDNPDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1267 $xmm0 = VANDNPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1268 ; CHECK: $xmm0 = VANDNPDrr $xmm0, $xmm1
1269 $xmm0 = VANDNPDZ128rr $xmm0, $xmm1
1270 ; CHECK: $xmm0 = VANDNPSrm $xmm0, $rip, 1, $noreg, 0, $noreg
1271 $xmm0 = VANDNPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1272 ; CHECK: $xmm0 = VANDNPSrr $xmm0, $xmm1
1273 $xmm0 = VANDNPSZ128rr $xmm0, $xmm1
1274 ; CHECK: $xmm0 = VANDPDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1275 $xmm0 = VANDPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1276 ; CHECK: $xmm0 = VANDPDrr $xmm0, $xmm1
1277 $xmm0 = VANDPDZ128rr $xmm0, $xmm1
1278 ; CHECK: $xmm0 = VANDPSrm $xmm0, $rip, 1, $noreg, 0, $noreg
1279 $xmm0 = VANDPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1280 ; CHECK: $xmm0 = VANDPSrr $xmm0, $xmm1
1281 $xmm0 = VANDPSZ128rr $xmm0, $xmm1
1282 ; CHECK: $xmm0 = VDIVPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1283 $xmm0 = VDIVPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1284 ; CHECK: $xmm0 = VDIVPDrr $xmm0, $xmm1, implicit $mxcsr
1285 $xmm0 = VDIVPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1286 ; CHECK: $xmm0 = VDIVPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1287 $xmm0 = VDIVPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1288 ; CHECK: $xmm0 = VDIVPSrr $xmm0, $xmm1, implicit $mxcsr
1289 $xmm0 = VDIVPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1290 ; CHECK: $xmm0 = VPXORrm $xmm0, $rip, 1, $noreg, 0, $noreg
1291 $xmm0 = VPXORDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1292 ; CHECK: $xmm0 = VPXORrr $xmm0, $xmm1
1293 $xmm0 = VPXORDZ128rr $xmm0, $xmm1
1294 ; CHECK: $xmm0 = VPXORrm $xmm0, $rip, 1, $noreg, 0, $noreg
1295 $xmm0 = VPXORQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1296 ; CHECK: $xmm0 = VPXORrr $xmm0, $xmm1
1297 $xmm0 = VPXORQZ128rr $xmm0, $xmm1
1298 ; CHECK: $xmm0 = VSUBPDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1299 $xmm0 = VSUBPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1300 ; CHECK: $xmm0 = VSUBPDrr $xmm0, $xmm1, implicit $mxcsr
1301 $xmm0 = VSUBPDZ128rr $xmm0, $xmm1, implicit $mxcsr
1302 ; CHECK: $xmm0 = VSUBPSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1303 $xmm0 = VSUBPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1304 ; CHECK: $xmm0 = VSUBPSrr $xmm0, $xmm1, implicit $mxcsr
1305 $xmm0 = VSUBPSZ128rr $xmm0, $xmm1, implicit $mxcsr
1306 ; CHECK: $xmm0 = VXORPDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1307 $xmm0 = VXORPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1308 ; CHECK: $xmm0 = VXORPDrr $xmm0, $xmm1
1309 $xmm0 = VXORPDZ128rr $xmm0, $xmm1
1310 ; CHECK: $xmm0 = VXORPSrm $xmm0, $rip, 1, $noreg, 0, $noreg
1311 $xmm0 = VXORPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1312 ; CHECK: $xmm0 = VXORPSrr $xmm0, $xmm1
1313 $xmm0 = VXORPSZ128rr $xmm0, $xmm1
1314 ; CHECK: $xmm0 = VPMADDUBSWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1315 $xmm0 = VPMADDUBSWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1316 ; CHECK: $xmm0 = VPMADDUBSWrr $xmm0, $xmm1
1317 $xmm0 = VPMADDUBSWZ128rr $xmm0, $xmm1
1318 ; CHECK: $xmm0 = VPMADDWDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1319 $xmm0 = VPMADDWDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1320 ; CHECK: $xmm0 = VPMADDWDrr $xmm0, $xmm1
1321 $xmm0 = VPMADDWDZ128rr $xmm0, $xmm1
1322 ; CHECK: $xmm0 = VPACKSSDWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1323 $xmm0 = VPACKSSDWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1324 ; CHECK: $xmm0 = VPACKSSDWrr $xmm0, $xmm1
1325 $xmm0 = VPACKSSDWZ128rr $xmm0, $xmm1
1326 ; CHECK: $xmm0 = VPACKSSWBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1327 $xmm0 = VPACKSSWBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1328 ; CHECK: $xmm0 = VPACKSSWBrr $xmm0, $xmm1
1329 $xmm0 = VPACKSSWBZ128rr $xmm0, $xmm1
1330 ; CHECK: $xmm0 = VPACKUSDWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1331 $xmm0 = VPACKUSDWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1332 ; CHECK: $xmm0 = VPACKUSDWrr $xmm0, $xmm1
1333 $xmm0 = VPACKUSDWZ128rr $xmm0, $xmm1
1334 ; CHECK: $xmm0 = VPACKUSWBrm $xmm0, $rip, 1, $noreg, 0, $noreg
1335 $xmm0 = VPACKUSWBZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1336 ; CHECK: $xmm0 = VPACKUSWBrr $xmm0, $xmm1
1337 $xmm0 = VPACKUSWBZ128rr $xmm0, $xmm1
1338 ; CHECK: $xmm0 = VPUNPCKHBWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1339 $xmm0 = VPUNPCKHBWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1340 ; CHECK: $xmm0 = VPUNPCKHBWrr $xmm0, $xmm1
1341 $xmm0 = VPUNPCKHBWZ128rr $xmm0, $xmm1
1342 ; CHECK: $xmm0 = VPUNPCKHDQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1343 $xmm0 = VPUNPCKHDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1344 ; CHECK: $xmm0 = VPUNPCKHDQrr $xmm0, $xmm1
1345 $xmm0 = VPUNPCKHDQZ128rr $xmm0, $xmm1
1346 ; CHECK: $xmm0 = VPUNPCKHQDQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1347 $xmm0 = VPUNPCKHQDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1348 ; CHECK: $xmm0 = VPUNPCKHQDQrr $xmm0, $xmm1
1349 $xmm0 = VPUNPCKHQDQZ128rr $xmm0, $xmm1
1350 ; CHECK: $xmm0 = VPUNPCKHWDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1351 $xmm0 = VPUNPCKHWDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1352 ; CHECK: $xmm0 = VPUNPCKHWDrr $xmm0, $xmm1
1353 $xmm0 = VPUNPCKHWDZ128rr $xmm0, $xmm1
1354 ; CHECK: $xmm0 = VPUNPCKLBWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1355 $xmm0 = VPUNPCKLBWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1356 ; CHECK: $xmm0 = VPUNPCKLBWrr $xmm0, $xmm1
1357 $xmm0 = VPUNPCKLBWZ128rr $xmm0, $xmm1
1358 ; CHECK: $xmm0 = VPUNPCKLDQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1359 $xmm0 = VPUNPCKLDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1360 ; CHECK: $xmm0 = VPUNPCKLDQrr $xmm0, $xmm1
1361 $xmm0 = VPUNPCKLDQZ128rr $xmm0, $xmm1
1362 ; CHECK: $xmm0 = VPUNPCKLQDQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1363 $xmm0 = VPUNPCKLQDQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1364 ; CHECK: $xmm0 = VPUNPCKLQDQrr $xmm0, $xmm1
1365 $xmm0 = VPUNPCKLQDQZ128rr $xmm0, $xmm1
1366 ; CHECK: $xmm0 = VPUNPCKLWDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1367 $xmm0 = VPUNPCKLWDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1368 ; CHECK: $xmm0 = VPUNPCKLWDrr $xmm0, $xmm1
1369 $xmm0 = VPUNPCKLWDZ128rr $xmm0, $xmm1
1370 ; CHECK: $xmm0 = VUNPCKHPDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1371 $xmm0 = VUNPCKHPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1372 ; CHECK: $xmm0 = VUNPCKHPDrr $xmm0, $xmm1
1373 $xmm0 = VUNPCKHPDZ128rr $xmm0, $xmm1
1374 ; CHECK: $xmm0 = VUNPCKHPSrm $xmm0, $rip, 1, $noreg, 0, $noreg
1375 $xmm0 = VUNPCKHPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1376 ; CHECK: $xmm0 = VUNPCKHPSrr $xmm0, $xmm1
1377 $xmm0 = VUNPCKHPSZ128rr $xmm0, $xmm1
1378 ; CHECK: $xmm0 = VUNPCKLPDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1379 $xmm0 = VUNPCKLPDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1380 ; CHECK: $xmm0 = VUNPCKLPDrr $xmm0, $xmm1
1381 $xmm0 = VUNPCKLPDZ128rr $xmm0, $xmm1
1382 ; CHECK: $xmm0 = VUNPCKLPSrm $xmm0, $rip, 1, $noreg, 0, $noreg
1383 $xmm0 = VUNPCKLPSZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1384 ; CHECK: $xmm0 = VUNPCKLPSrr $xmm0, $xmm1
1385 $xmm0 = VUNPCKLPSZ128rr $xmm0, $xmm1
1386 ; CHECK: $xmm0 = VFMADD132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1387 $xmm0 = VFMADD132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1388 ; CHECK: $xmm0 = VFMADD132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1389 $xmm0 = VFMADD132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1390 ; CHECK: $xmm0 = VFMADD132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1391 $xmm0 = VFMADD132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1392 ; CHECK: $xmm0 = VFMADD132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1393 $xmm0 = VFMADD132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1394 ; CHECK: $xmm0 = VFMADD213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1395 $xmm0 = VFMADD213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1396 ; CHECK: $xmm0 = VFMADD213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1397 $xmm0 = VFMADD213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1398 ; CHECK: $xmm0 = VFMADD213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1399 $xmm0 = VFMADD213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1400 ; CHECK: $xmm0 = VFMADD213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1401 $xmm0 = VFMADD213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1402 ; CHECK: $xmm0 = VFMADD231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1403 $xmm0 = VFMADD231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1404 ; CHECK: $xmm0 = VFMADD231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1405 $xmm0 = VFMADD231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1406 ; CHECK: $xmm0 = VFMADD231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1407 $xmm0 = VFMADD231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1408 ; CHECK: $xmm0 = VFMADD231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1409 $xmm0 = VFMADD231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1410 ; CHECK: $xmm0 = VFMADDSUB132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1411 $xmm0 = VFMADDSUB132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1412 ; CHECK: $xmm0 = VFMADDSUB132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1413 $xmm0 = VFMADDSUB132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1414 ; CHECK: $xmm0 = VFMADDSUB132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1415 $xmm0 = VFMADDSUB132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1416 ; CHECK: $xmm0 = VFMADDSUB132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1417 $xmm0 = VFMADDSUB132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1418 ; CHECK: $xmm0 = VFMADDSUB213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1419 $xmm0 = VFMADDSUB213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1420 ; CHECK: $xmm0 = VFMADDSUB213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1421 $xmm0 = VFMADDSUB213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1422 ; CHECK: $xmm0 = VFMADDSUB213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1423 $xmm0 = VFMADDSUB213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1424 ; CHECK: $xmm0 = VFMADDSUB213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1425 $xmm0 = VFMADDSUB213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1426 ; CHECK: $xmm0 = VFMADDSUB231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1427 $xmm0 = VFMADDSUB231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1428 ; CHECK: $xmm0 = VFMADDSUB231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1429 $xmm0 = VFMADDSUB231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1430 ; CHECK: $xmm0 = VFMADDSUB231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1431 $xmm0 = VFMADDSUB231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1432 ; CHECK: $xmm0 = VFMADDSUB231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1433 $xmm0 = VFMADDSUB231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1434 ; CHECK: $xmm0 = VFMSUB132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1435 $xmm0 = VFMSUB132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1436 ; CHECK: $xmm0 = VFMSUB132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1437 $xmm0 = VFMSUB132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1438 ; CHECK: $xmm0 = VFMSUB132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1439 $xmm0 = VFMSUB132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1440 ; CHECK: $xmm0 = VFMSUB132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1441 $xmm0 = VFMSUB132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1442 ; CHECK: $xmm0 = VFMSUB213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1443 $xmm0 = VFMSUB213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1444 ; CHECK: $xmm0 = VFMSUB213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1445 $xmm0 = VFMSUB213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1446 ; CHECK: $xmm0 = VFMSUB213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1447 $xmm0 = VFMSUB213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1448 ; CHECK: $xmm0 = VFMSUB213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1449 $xmm0 = VFMSUB213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1450 ; CHECK: $xmm0 = VFMSUB231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1451 $xmm0 = VFMSUB231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1452 ; CHECK: $xmm0 = VFMSUB231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1453 $xmm0 = VFMSUB231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1454 ; CHECK: $xmm0 = VFMSUB231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1455 $xmm0 = VFMSUB231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1456 ; CHECK: $xmm0 = VFMSUB231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1457 $xmm0 = VFMSUB231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1458 ; CHECK: $xmm0 = VFMSUBADD132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1459 $xmm0 = VFMSUBADD132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1460 ; CHECK: $xmm0 = VFMSUBADD132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1461 $xmm0 = VFMSUBADD132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1462 ; CHECK: $xmm0 = VFMSUBADD132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1463 $xmm0 = VFMSUBADD132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1464 ; CHECK: $xmm0 = VFMSUBADD132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1465 $xmm0 = VFMSUBADD132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1466 ; CHECK: $xmm0 = VFMSUBADD213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1467 $xmm0 = VFMSUBADD213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1468 ; CHECK: $xmm0 = VFMSUBADD213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1469 $xmm0 = VFMSUBADD213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1470 ; CHECK: $xmm0 = VFMSUBADD213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1471 $xmm0 = VFMSUBADD213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1472 ; CHECK: $xmm0 = VFMSUBADD213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1473 $xmm0 = VFMSUBADD213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1474 ; CHECK: $xmm0 = VFMSUBADD231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1475 $xmm0 = VFMSUBADD231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1476 ; CHECK: $xmm0 = VFMSUBADD231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1477 $xmm0 = VFMSUBADD231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1478 ; CHECK: $xmm0 = VFMSUBADD231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1479 $xmm0 = VFMSUBADD231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1480 ; CHECK: $xmm0 = VFMSUBADD231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1481 $xmm0 = VFMSUBADD231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1482 ; CHECK: $xmm0 = VFNMADD132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1483 $xmm0 = VFNMADD132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1484 ; CHECK: $xmm0 = VFNMADD132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1485 $xmm0 = VFNMADD132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1486 ; CHECK: $xmm0 = VFNMADD132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1487 $xmm0 = VFNMADD132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1488 ; CHECK: $xmm0 = VFNMADD132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1489 $xmm0 = VFNMADD132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1490 ; CHECK: $xmm0 = VFNMADD213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1491 $xmm0 = VFNMADD213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1492 ; CHECK: $xmm0 = VFNMADD213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1493 $xmm0 = VFNMADD213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1494 ; CHECK: $xmm0 = VFNMADD213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1495 $xmm0 = VFNMADD213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1496 ; CHECK: $xmm0 = VFNMADD213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1497 $xmm0 = VFNMADD213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1498 ; CHECK: $xmm0 = VFNMADD231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1499 $xmm0 = VFNMADD231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1500 ; CHECK: $xmm0 = VFNMADD231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1501 $xmm0 = VFNMADD231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1502 ; CHECK: $xmm0 = VFNMADD231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1503 $xmm0 = VFNMADD231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1504 ; CHECK: $xmm0 = VFNMADD231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1505 $xmm0 = VFNMADD231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1506 ; CHECK: $xmm0 = VFNMSUB132PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1507 $xmm0 = VFNMSUB132PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1508 ; CHECK: $xmm0 = VFNMSUB132PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1509 $xmm0 = VFNMSUB132PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1510 ; CHECK: $xmm0 = VFNMSUB132PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1511 $xmm0 = VFNMSUB132PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1512 ; CHECK: $xmm0 = VFNMSUB132PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1513 $xmm0 = VFNMSUB132PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1514 ; CHECK: $xmm0 = VFNMSUB213PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1515 $xmm0 = VFNMSUB213PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1516 ; CHECK: $xmm0 = VFNMSUB213PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1517 $xmm0 = VFNMSUB213PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1518 ; CHECK: $xmm0 = VFNMSUB213PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1519 $xmm0 = VFNMSUB213PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1520 ; CHECK: $xmm0 = VFNMSUB213PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1521 $xmm0 = VFNMSUB213PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1522 ; CHECK: $xmm0 = VFNMSUB231PDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1523 $xmm0 = VFNMSUB231PDZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1524 ; CHECK: $xmm0 = VFNMSUB231PDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1525 $xmm0 = VFNMSUB231PDZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1526 ; CHECK: $xmm0 = VFNMSUB231PSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1527 $xmm0 = VFNMSUB231PSZ128m $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1528 ; CHECK: $xmm0 = VFNMSUB231PSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1529 $xmm0 = VFNMSUB231PSZ128r $xmm0, $xmm1, $xmm2, implicit $mxcsr
1530 ; CHECK: $xmm0 = VPSLLDri $xmm0, 7
1531 $xmm0 = VPSLLDZ128ri $xmm0, 7
1532 ; CHECK: $xmm0 = VPSLLDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1533 $xmm0 = VPSLLDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1534 ; CHECK: $xmm0 = VPSLLDrr $xmm0, $xmm0
1535 $xmm0 = VPSLLDZ128rr $xmm0, $xmm0
1536 ; CHECK: $xmm0 = VPSLLQri $xmm0, 7
1537 $xmm0 = VPSLLQZ128ri $xmm0, 7
1538 ; CHECK: $xmm0 = VPSLLQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1539 $xmm0 = VPSLLQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1540 ; CHECK: $xmm0 = VPSLLQrr $xmm0, $xmm0
1541 $xmm0 = VPSLLQZ128rr $xmm0, $xmm0
1542 ; CHECK: $xmm0 = VPSLLVDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1543 $xmm0 = VPSLLVDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1544 ; CHECK: $xmm0 = VPSLLVDrr $xmm0, $xmm0
1545 $xmm0 = VPSLLVDZ128rr $xmm0, $xmm0
1546 ; CHECK: $xmm0 = VPSLLVQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1547 $xmm0 = VPSLLVQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1548 ; CHECK: $xmm0 = VPSLLVQrr $xmm0, $xmm0
1549 $xmm0 = VPSLLVQZ128rr $xmm0, $xmm0
1550 ; CHECK: $xmm0 = VPSLLWri $xmm0, 7
1551 $xmm0 = VPSLLWZ128ri $xmm0, 7
1552 ; CHECK: $xmm0 = VPSLLWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1553 $xmm0 = VPSLLWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1554 ; CHECK: $xmm0 = VPSLLWrr $xmm0, $xmm0
1555 $xmm0 = VPSLLWZ128rr $xmm0, $xmm0
1556 ; CHECK: $xmm0 = VPSRADri $xmm0, 7
1557 $xmm0 = VPSRADZ128ri $xmm0, 7
1558 ; CHECK: $xmm0 = VPSRADrm $xmm0, $rip, 1, $noreg, 0, $noreg
1559 $xmm0 = VPSRADZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1560 ; CHECK: $xmm0 = VPSRADrr $xmm0, $xmm0
1561 $xmm0 = VPSRADZ128rr $xmm0, $xmm0
1562 ; CHECK: $xmm0 = VPSRAVDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1563 $xmm0 = VPSRAVDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1564 ; CHECK: $xmm0 = VPSRAVDrr $xmm0, $xmm0
1565 $xmm0 = VPSRAVDZ128rr $xmm0, $xmm0
1566 ; CHECK: $xmm0 = VPSRAWri $xmm0, 7
1567 $xmm0 = VPSRAWZ128ri $xmm0, 7
1568 ; CHECK: $xmm0 = VPSRAWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1569 $xmm0 = VPSRAWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1570 ; CHECK: $xmm0 = VPSRAWrr $xmm0, $xmm0
1571 $xmm0 = VPSRAWZ128rr $xmm0, $xmm0
1572 ; CHECK: $xmm0 = VPSRLDQri $xmm0, 14
1573 $xmm0 = VPSRLDQZ128ri $xmm0, 14
1574 ; CHECK: $xmm0 = VPSRLDri $xmm0, 7
1575 $xmm0 = VPSRLDZ128ri $xmm0, 7
1576 ; CHECK: $xmm0 = VPSRLDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1577 $xmm0 = VPSRLDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1578 ; CHECK: $xmm0 = VPSRLDrr $xmm0, $xmm0
1579 $xmm0 = VPSRLDZ128rr $xmm0, $xmm0
1580 ; CHECK: $xmm0 = VPSRLQri $xmm0, 7
1581 $xmm0 = VPSRLQZ128ri $xmm0, 7
1582 ; CHECK: $xmm0 = VPSRLQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1583 $xmm0 = VPSRLQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1584 ; CHECK: $xmm0 = VPSRLQrr $xmm0, $xmm0
1585 $xmm0 = VPSRLQZ128rr $xmm0, $xmm0
1586 ; CHECK: $xmm0 = VPSRLVDrm $xmm0, $rip, 1, $noreg, 0, $noreg
1587 $xmm0 = VPSRLVDZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1588 ; CHECK: $xmm0 = VPSRLVDrr $xmm0, $xmm0
1589 $xmm0 = VPSRLVDZ128rr $xmm0, $xmm0
1590 ; CHECK: $xmm0 = VPSRLVQrm $xmm0, $rip, 1, $noreg, 0, $noreg
1591 $xmm0 = VPSRLVQZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1592 ; CHECK: $xmm0 = VPSRLVQrr $xmm0, $xmm0
1593 $xmm0 = VPSRLVQZ128rr $xmm0, $xmm0
1594 ; CHECK: $xmm0 = VPSRLWri $xmm0, 7
1595 $xmm0 = VPSRLWZ128ri $xmm0, 7
1596 ; CHECK: $xmm0 = VPSRLWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1597 $xmm0 = VPSRLWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1598 ; CHECK: $xmm0 = VPSRLWrr $xmm0, $xmm0
1599 $xmm0 = VPSRLWZ128rr $xmm0, $xmm0
1600 ; CHECK: $xmm0 = VPERMILPDmi $rdi, 1, $noreg, 0, $noreg, 9
1601 $xmm0 = VPERMILPDZ128mi $rdi, 1, $noreg, 0, $noreg, 9
1602 ; CHECK: $xmm0 = VPERMILPDri $xmm0, 9
1603 $xmm0 = VPERMILPDZ128ri $xmm0, 9
1604 ; CHECK: $xmm0 = VPERMILPDrm $xmm0, $rdi, 1, $noreg, 0, $noreg
1605 $xmm0 = VPERMILPDZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg
1606 ; CHECK: $xmm0 = VPERMILPDrr $xmm0, $xmm1
1607 $xmm0 = VPERMILPDZ128rr $xmm0, $xmm1
1608 ; CHECK: $xmm0 = VPERMILPSmi $rdi, 1, $noreg, 0, $noreg, 9
1609 $xmm0 = VPERMILPSZ128mi $rdi, 1, $noreg, 0, $noreg, 9
1610 ; CHECK: $xmm0 = VPERMILPSri $xmm0, 9
1611 $xmm0 = VPERMILPSZ128ri $xmm0, 9
1612 ; CHECK: $xmm0 = VPERMILPSrm $xmm0, $rdi, 1, $noreg, 0, $noreg
1613 $xmm0 = VPERMILPSZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg
1614 ; CHECK: $xmm0 = VPERMILPSrr $xmm0, $xmm1
1615 $xmm0 = VPERMILPSZ128rr $xmm0, $xmm1
1616 ; CHECK: $xmm0 = VCVTPH2PSrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1617 $xmm0 = VCVTPH2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1618 ; CHECK: $xmm0 = VCVTPH2PSrr $xmm0, implicit $mxcsr
1619 $xmm0 = VCVTPH2PSZ128rr $xmm0, implicit $mxcsr
1620 ; CHECK: $xmm0 = VCVTDQ2PDrm $rdi, 1, $noreg, 0, $noreg
1621 $xmm0 = VCVTDQ2PDZ128rm $rdi, 1, $noreg, 0, $noreg
1622 ; CHECK: $xmm0 = VCVTDQ2PDrr $xmm0
1623 $xmm0 = VCVTDQ2PDZ128rr $xmm0
1624 ; CHECK: $xmm0 = VCVTDQ2PSrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1625 $xmm0 = VCVTDQ2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1626 ; CHECK: $xmm0 = VCVTDQ2PSrr $xmm0, implicit $mxcsr
1627 $xmm0 = VCVTDQ2PSZ128rr $xmm0, implicit $mxcsr
1628 ; CHECK: $xmm0 = VCVTPD2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1629 $xmm0 = VCVTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1630 ; CHECK: $xmm0 = VCVTPD2DQrr $xmm0, implicit $mxcsr
1631 $xmm0 = VCVTPD2DQZ128rr $xmm0, implicit $mxcsr
1632 ; CHECK: $xmm0 = VCVTPD2PSrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1633 $xmm0 = VCVTPD2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1634 ; CHECK: $xmm0 = VCVTPD2PSrr $xmm0, implicit $mxcsr
1635 $xmm0 = VCVTPD2PSZ128rr $xmm0, implicit $mxcsr
1636 ; CHECK: $xmm0 = VCVTPS2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1637 $xmm0 = VCVTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1638 ; CHECK: $xmm0 = VCVTPS2DQrr $xmm0, implicit $mxcsr
1639 $xmm0 = VCVTPS2DQZ128rr $xmm0, implicit $mxcsr
1640 ; CHECK: $xmm0 = VCVTPS2PDrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1641 $xmm0 = VCVTPS2PDZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1642 ; CHECK: $xmm0 = VCVTPS2PDrr $xmm0, implicit $mxcsr
1643 $xmm0 = VCVTPS2PDZ128rr $xmm0, implicit $mxcsr
1644 ; CHECK: $xmm0 = VCVTTPD2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1645 $xmm0 = VCVTTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1646 ; CHECK: $xmm0 = VCVTTPD2DQrr $xmm0, implicit $mxcsr
1647 $xmm0 = VCVTTPD2DQZ128rr $xmm0, implicit $mxcsr
1648 ; CHECK: $xmm0 = VCVTTPS2DQrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1649 $xmm0 = VCVTTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1650 ; CHECK: $xmm0 = VCVTTPS2DQrr $xmm0, implicit $mxcsr
1651 $xmm0 = VCVTTPS2DQZ128rr $xmm0, implicit $mxcsr
1652 ; CHECK: $xmm0 = VSQRTPDm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1653 $xmm0 = VSQRTPDZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1654 ; CHECK: $xmm0 = VSQRTPDr $xmm0, implicit $mxcsr
1655 $xmm0 = VSQRTPDZ128r $xmm0, implicit $mxcsr
1656 ; CHECK: $xmm0 = VSQRTPSm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1657 $xmm0 = VSQRTPSZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
1658 ; CHECK: $xmm0 = VSQRTPSr $xmm0, implicit $mxcsr
1659 $xmm0 = VSQRTPSZ128r $xmm0, implicit $mxcsr
1660 ; CHECK: $xmm0 = VMOVDDUPrm $rdi, 1, $noreg, 0, $noreg
1661 $xmm0 = VMOVDDUPZ128rm $rdi, 1, $noreg, 0, $noreg
1662 ; CHECK: $xmm0 = VMOVDDUPrr $xmm0
1663 $xmm0 = VMOVDDUPZ128rr $xmm0
1664 ; CHECK: $xmm0 = VMOVSHDUPrm $rdi, 1, $noreg, 0, $noreg
1665 $xmm0 = VMOVSHDUPZ128rm $rdi, 1, $noreg, 0, $noreg
1666 ; CHECK: $xmm0 = VMOVSHDUPrr $xmm0
1667 $xmm0 = VMOVSHDUPZ128rr $xmm0
1668 ; CHECK: $xmm0 = VMOVSLDUPrm $rdi, 1, $noreg, 0, $noreg
1669 $xmm0 = VMOVSLDUPZ128rm $rdi, 1, $noreg, 0, $noreg
1670 ; CHECK: $xmm0 = VMOVSLDUPrr $xmm0
1671 $xmm0 = VMOVSLDUPZ128rr $xmm0
1672 ; CHECK: $xmm0 = VPSHUFBrm $xmm0, $rdi, 1, $noreg, 0, $noreg
1673 $xmm0 = VPSHUFBZ128rm $xmm0, $rdi, 1, $noreg, 0, $noreg
1674 ; CHECK: $xmm0 = VPSHUFBrr $xmm0, $xmm1
1675 $xmm0 = VPSHUFBZ128rr $xmm0, $xmm1
1676 ; CHECK: $xmm0 = VPSHUFDmi $rdi, 1, $noreg, 0, $noreg, -24
1677 $xmm0 = VPSHUFDZ128mi $rdi, 1, $noreg, 0, $noreg, -24
1678 ; CHECK: $xmm0 = VPSHUFDri $xmm0, -24
1679 $xmm0 = VPSHUFDZ128ri $xmm0, -24
1680 ; CHECK: $xmm0 = VPSHUFHWmi $rdi, 1, $noreg, 0, $noreg, -24
1681 $xmm0 = VPSHUFHWZ128mi $rdi, 1, $noreg, 0, $noreg, -24
1682 ; CHECK: $xmm0 = VPSHUFHWri $xmm0, -24
1683 $xmm0 = VPSHUFHWZ128ri $xmm0, -24
1684 ; CHECK: $xmm0 = VPSHUFLWmi $rdi, 1, $noreg, 0, $noreg, -24
1685 $xmm0 = VPSHUFLWZ128mi $rdi, 1, $noreg, 0, $noreg, -24
1686 ; CHECK: $xmm0 = VPSHUFLWri $xmm0, -24
1687 $xmm0 = VPSHUFLWZ128ri $xmm0, -24
1688 ; CHECK: $xmm0 = VPSLLDQri $xmm0, 7
1689 $xmm0 = VPSLLDQZ128ri $xmm0, 7
1690 ; CHECK: $xmm0 = VSHUFPDrmi $xmm0, $rip, 1, $noreg, 0, $noreg, -24
1691 $xmm0 = VSHUFPDZ128rmi $xmm0, $rip, 1, $noreg, 0, $noreg, -24
1692 ; CHECK: $xmm0 = VSHUFPDrri $xmm0, $xmm1, -24
1693 $xmm0 = VSHUFPDZ128rri $xmm0, $xmm1, -24
1694 ; CHECK: $xmm0 = VSHUFPSrmi $xmm0, $rip, 1, $noreg, 0, $noreg, -24
1695 $xmm0 = VSHUFPSZ128rmi $xmm0, $rip, 1, $noreg, 0, $noreg, -24
1696 ; CHECK: $xmm0 = VSHUFPSrri $xmm0, $xmm1, -24
1697 $xmm0 = VSHUFPSZ128rri $xmm0, $xmm1, -24
1698 ; CHECK: $xmm0 = VPSADBWrm $xmm0, $rip, 1, $noreg, 0, $noreg
1699 $xmm0 = VPSADBWZ128rm $xmm0, $rip, 1, $noreg, 0, $noreg
1700 ; CHECK: $xmm0 = VPSADBWrr $xmm0, $xmm1
1701 $xmm0 = VPSADBWZ128rr $xmm0, $xmm1
1702 ; CHECK: $xmm0 = VBROADCASTSSrm $rip, 1, $noreg, 0, $noreg
1703 $xmm0 = VBROADCASTSSZ128rm $rip, 1, $noreg, 0, $noreg
1704 ; CHECK: $xmm0 = VBROADCASTSSrr $xmm0
1705 $xmm0 = VBROADCASTSSZ128rr $xmm0
1706 ; CHECK: $xmm0 = VPBROADCASTBrm $rip, 1, $noreg, 0, $noreg
1707 $xmm0 = VPBROADCASTBZ128rm $rip, 1, $noreg, 0, $noreg
1708 ; CHECK: $xmm0 = VPBROADCASTBrr $xmm0
1709 $xmm0 = VPBROADCASTBZ128rr $xmm0
1710 ; CHECK: $xmm0 = VPBROADCASTDrm $rip, 1, $noreg, 0, $noreg
1711 $xmm0 = VPBROADCASTDZ128rm $rip, 1, $noreg, 0, $noreg
1712 ; CHECK: $xmm0 = VPBROADCASTDrr $xmm0
1713 $xmm0 = VPBROADCASTDZ128rr $xmm0
1714 ; CHECK: $xmm0 = VPBROADCASTQrm $rip, 1, $noreg, 0, $noreg
1715 $xmm0 = VPBROADCASTQZ128rm $rip, 1, $noreg, 0, $noreg
1716 ; CHECK: $xmm0 = VPBROADCASTQrr $xmm0
1717 $xmm0 = VPBROADCASTQZ128rr $xmm0
1718 ; CHECK: $xmm0 = VPBROADCASTWrm $rip, 1, $noreg, 0, $noreg
1719 $xmm0 = VPBROADCASTWZ128rm $rip, 1, $noreg, 0, $noreg
1720 ; CHECK: $xmm0 = VPBROADCASTWrr $xmm0
1721 $xmm0 = VPBROADCASTWZ128rr $xmm0
1722 ; CHECK: $xmm0 = VPBROADCASTQrm $rip, 1, $noreg, 0, $noreg
1723 $xmm0 = VBROADCASTI32X2Z128rm $rip, 1, $noreg, 0, $noreg
1724 ; CHECK: $xmm0 = VPBROADCASTQrr $xmm0
1725 $xmm0 = VBROADCASTI32X2Z128rr $xmm0
1726 ; CHECK: $xmm0 = VCVTPS2PHrr $xmm0, 2, implicit $mxcsr
1727 $xmm0 = VCVTPS2PHZ128rr $xmm0, 2, implicit $mxcsr
1728 ; CHECK: VCVTPS2PHmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 2, implicit $mxcsr
1729 VCVTPS2PHZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm0, 2, implicit $mxcsr
1730 ; CHECK: $xmm0 = VPABSBrm $rip, 1, $noreg, 0, $noreg
1731 $xmm0 = VPABSBZ128rm $rip, 1, $noreg, 0, $noreg
1732 ; CHECK: $xmm0 = VPABSBrr $xmm0
1733 $xmm0 = VPABSBZ128rr $xmm0
1734 ; CHECK: $xmm0 = VPABSDrm $rip, 1, $noreg, 0, $noreg
1735 $xmm0 = VPABSDZ128rm $rip, 1, $noreg, 0, $noreg
1736 ; CHECK: $xmm0 = VPABSDrr $xmm0
1737 $xmm0 = VPABSDZ128rr $xmm0
1738 ; CHECK: $xmm0 = VPABSWrm $rip, 1, $noreg, 0, $noreg
1739 $xmm0 = VPABSWZ128rm $rip, 1, $noreg, 0, $noreg
1740 ; CHECK: $xmm0 = VPABSWrr $xmm0
1741 $xmm0 = VPABSWZ128rr $xmm0
1742 ; CHECK: $xmm0 = VPALIGNRrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15
1743 $xmm0 = VPALIGNRZ128rmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15
1744 ; CHECK: $xmm0 = VPALIGNRrri $xmm0, $xmm1, 15
1745 $xmm0 = VPALIGNRZ128rri $xmm0, $xmm1, 15
1746 ; CHECK: $xmm0 = VPALIGNRrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 4
1747 $xmm0 = VALIGNDZ128rmi $xmm0, $rip, 1, $noreg, 0, $noreg, 1
1748 ; CHECK: $xmm0 = VPALIGNRrri $xmm0, $xmm1, 4
1749 $xmm0 = VALIGNDZ128rri $xmm0, $xmm1, 1
1750 ; CHECK: $xmm0 = VPALIGNRrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 8
1751 $xmm0 = VALIGNQZ128rmi $xmm0, $rip, 1, $noreg, 0, $noreg, 1
1752 ; CHECK: $xmm0 = VPALIGNRrri $xmm0, $xmm1, 8
1753 $xmm0 = VALIGNQZ128rri $xmm0, $xmm1, 1
1754 ; CHECK: $xmm0 = VROUNDPDm $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
1755 $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
1756 ; CHECK: $xmm0 = VROUNDPDr $xmm0, 15, implicit $mxcsr
1757 $xmm0 = VRNDSCALEPDZ128rri $xmm0, 15, implicit $mxcsr
1758 ; CHECK: $xmm0 = VROUNDPSm $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
1759 $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
1760 ; CHECK: $xmm0 = VROUNDPSr $xmm0, 15, implicit $mxcsr
1761 $xmm0 = VRNDSCALEPSZ128rri $xmm0, 15, implicit $mxcsr
1763 RET64
1764 ...
1765 ---
1766 # CHECK-LABEL: name: evex_scalar_to_vex_test
1767 # CHECK: bb.0:
1769 name: evex_scalar_to_vex_test
1770 body: |
1771 bb.0:
1773 ; CHECK: $xmm0 = VADDSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1774 $xmm0 = VADDSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1775 ; CHECK: $xmm0 = VADDSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1776 $xmm0 = VADDSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1777 ; CHECK: $xmm0 = VADDSDrr $xmm0, $xmm1, implicit $mxcsr
1778 $xmm0 = VADDSDZrr $xmm0, $xmm1, implicit $mxcsr
1779 ; CHECK: $xmm0 = VADDSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1780 $xmm0 = VADDSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1781 ; CHECK: $xmm0 = VADDSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1782 $xmm0 = VADDSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1783 ; CHECK: $xmm0 = VADDSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1784 $xmm0 = VADDSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1785 ; CHECK: $xmm0 = VADDSSrr $xmm0, $xmm1, implicit $mxcsr
1786 $xmm0 = VADDSSZrr $xmm0, $xmm1, implicit $mxcsr
1787 ; CHECK: $xmm0 = VADDSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1788 $xmm0 = VADDSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1789 ; CHECK: $xmm0 = VDIVSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1790 $xmm0 = VDIVSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1791 ; CHECK: $xmm0 = VDIVSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1792 $xmm0 = VDIVSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1793 ; CHECK: $xmm0 = VDIVSDrr $xmm0, $xmm1, implicit $mxcsr
1794 $xmm0 = VDIVSDZrr $xmm0, $xmm1, implicit $mxcsr
1795 ; CHECK: $xmm0 = VDIVSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1796 $xmm0 = VDIVSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1797 ; CHECK: $xmm0 = VDIVSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1798 $xmm0 = VDIVSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1799 ; CHECK: $xmm0 = VDIVSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1800 $xmm0 = VDIVSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1801 ; CHECK: $xmm0 = VDIVSSrr $xmm0, $xmm1, implicit $mxcsr
1802 $xmm0 = VDIVSSZrr $xmm0, $xmm1, implicit $mxcsr
1803 ; CHECK: $xmm0 = VDIVSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1804 $xmm0 = VDIVSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1805 ; CHECK: $xmm0 = VMAXCSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1806 $xmm0 = VMAXCSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1807 ; CHECK: $xmm0 = VMAXCSDrr $xmm0, $xmm1, implicit $mxcsr
1808 $xmm0 = VMAXCSDZrr $xmm0, $xmm1, implicit $mxcsr
1809 ; CHECK: $xmm0 = VMAXCSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1810 $xmm0 = VMAXCSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1811 ; CHECK: $xmm0 = VMAXCSSrr $xmm0, $xmm1, implicit $mxcsr
1812 $xmm0 = VMAXCSSZrr $xmm0, $xmm1, implicit $mxcsr
1813 ; CHECK: $xmm0 = VMAXSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1814 $xmm0 = VMAXSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1815 ; CHECK: $xmm0 = VMAXSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1816 $xmm0 = VMAXSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1817 ; CHECK: $xmm0 = VMAXSDrr $xmm0, $xmm1, implicit $mxcsr
1818 $xmm0 = VMAXSDZrr $xmm0, $xmm1, implicit $mxcsr
1819 ; CHECK: $xmm0 = VMAXSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1820 $xmm0 = VMAXSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1821 ; CHECK: $xmm0 = VMAXSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1822 $xmm0 = VMAXSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1823 ; CHECK: $xmm0 = VMAXSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1824 $xmm0 = VMAXSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1825 ; CHECK: $xmm0 = VMAXSSrr $xmm0, $xmm1, implicit $mxcsr
1826 $xmm0 = VMAXSSZrr $xmm0, $xmm1, implicit $mxcsr
1827 ; CHECK: $xmm0 = VMAXSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1828 $xmm0 = VMAXSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1829 ; CHECK: $xmm0 = VMINCSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1830 $xmm0 = VMINCSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1831 ; CHECK: $xmm0 = VMINCSDrr $xmm0, $xmm1, implicit $mxcsr
1832 $xmm0 = VMINCSDZrr $xmm0, $xmm1, implicit $mxcsr
1833 ; CHECK: $xmm0 = VMINCSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1834 $xmm0 = VMINCSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1835 ; CHECK: $xmm0 = VMINCSSrr $xmm0, $xmm1, implicit $mxcsr
1836 $xmm0 = VMINCSSZrr $xmm0, $xmm1, implicit $mxcsr
1837 ; CHECK: $xmm0 = VMINSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1838 $xmm0 = VMINSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1839 ; CHECK: $xmm0 = VMINSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1840 $xmm0 = VMINSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1841 ; CHECK: $xmm0 = VMINSDrr $xmm0, $xmm1, implicit $mxcsr
1842 $xmm0 = VMINSDZrr $xmm0, $xmm1, implicit $mxcsr
1843 ; CHECK: $xmm0 = VMINSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1844 $xmm0 = VMINSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1845 ; CHECK: $xmm0 = VMINSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1846 $xmm0 = VMINSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1847 ; CHECK: $xmm0 = VMINSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1848 $xmm0 = VMINSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1849 ; CHECK: $xmm0 = VMINSSrr $xmm0, $xmm1, implicit $mxcsr
1850 $xmm0 = VMINSSZrr $xmm0, $xmm1, implicit $mxcsr
1851 ; CHECK: $xmm0 = VMINSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1852 $xmm0 = VMINSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1853 ; CHECK: $xmm0 = VMULSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1854 $xmm0 = VMULSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1855 ; CHECK: $xmm0 = VMULSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1856 $xmm0 = VMULSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1857 ; CHECK: $xmm0 = VMULSDrr $xmm0, $xmm1, implicit $mxcsr
1858 $xmm0 = VMULSDZrr $xmm0, $xmm1, implicit $mxcsr
1859 ; CHECK: $xmm0 = VMULSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1860 $xmm0 = VMULSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1861 ; CHECK: $xmm0 = VMULSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1862 $xmm0 = VMULSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1863 ; CHECK: $xmm0 = VMULSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1864 $xmm0 = VMULSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1865 ; CHECK: $xmm0 = VMULSSrr $xmm0, $xmm1, implicit $mxcsr
1866 $xmm0 = VMULSSZrr $xmm0, $xmm1, implicit $mxcsr
1867 ; CHECK: $xmm0 = VMULSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1868 $xmm0 = VMULSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1869 ; CHECK: $xmm0 = VSUBSDrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1870 $xmm0 = VSUBSDZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1871 ; CHECK: $xmm0 = VSUBSDrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1872 $xmm0 = VSUBSDZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1873 ; CHECK: $xmm0 = VSUBSDrr $xmm0, $xmm1, implicit $mxcsr
1874 $xmm0 = VSUBSDZrr $xmm0, $xmm1, implicit $mxcsr
1875 ; CHECK: $xmm0 = VSUBSDrr_Int $xmm0, $xmm1, implicit $mxcsr
1876 $xmm0 = VSUBSDZrr_Int $xmm0, $xmm1, implicit $mxcsr
1877 ; CHECK: $xmm0 = VSUBSSrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1878 $xmm0 = VSUBSSZrm $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1879 ; CHECK: $xmm0 = VSUBSSrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1880 $xmm0 = VSUBSSZrm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
1881 ; CHECK: $xmm0 = VSUBSSrr $xmm0, $xmm1, implicit $mxcsr
1882 $xmm0 = VSUBSSZrr $xmm0, $xmm1, implicit $mxcsr
1883 ; CHECK: $xmm0 = VSUBSSrr_Int $xmm0, $xmm1, implicit $mxcsr
1884 $xmm0 = VSUBSSZrr_Int $xmm0, $xmm1, implicit $mxcsr
1885 ; CHECK: $xmm0 = VFMADD132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1886 $xmm0 = VFMADD132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1887 ; CHECK: $xmm0 = VFMADD132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1888 $xmm0 = VFMADD132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1889 ; CHECK: $xmm0 = VFMADD132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1890 $xmm0 = VFMADD132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1891 ; CHECK: $xmm0 = VFMADD132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1892 $xmm0 = VFMADD132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1893 ; CHECK: $xmm0 = VFMADD132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1894 $xmm0 = VFMADD132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1895 ; CHECK: $xmm0 = VFMADD132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1896 $xmm0 = VFMADD132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1897 ; CHECK: $xmm0 = VFMADD132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1898 $xmm0 = VFMADD132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1899 ; CHECK: $xmm0 = VFMADD132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1900 $xmm0 = VFMADD132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1901 ; CHECK: $xmm0 = VFMADD213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1902 $xmm0 = VFMADD213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1903 ; CHECK: $xmm0 = VFMADD213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1904 $xmm0 = VFMADD213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1905 ; CHECK: $xmm0 = VFMADD213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1906 $xmm0 = VFMADD213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1907 ; CHECK: $xmm0 = VFMADD213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1908 $xmm0 = VFMADD213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1909 ; CHECK: $xmm0 = VFMADD213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1910 $xmm0 = VFMADD213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1911 ; CHECK: $xmm0 = VFMADD213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1912 $xmm0 = VFMADD213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1913 ; CHECK: $xmm0 = VFMADD213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1914 $xmm0 = VFMADD213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1915 ; CHECK: $xmm0 = VFMADD213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1916 $xmm0 = VFMADD213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1917 ; CHECK: $xmm0 = VFMADD231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1918 $xmm0 = VFMADD231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1919 ; CHECK: $xmm0 = VFMADD231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1920 $xmm0 = VFMADD231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1921 ; CHECK: $xmm0 = VFMADD231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1922 $xmm0 = VFMADD231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1923 ; CHECK: $xmm0 = VFMADD231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1924 $xmm0 = VFMADD231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1925 ; CHECK: $xmm0 = VFMADD231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1926 $xmm0 = VFMADD231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1927 ; CHECK: $xmm0 = VFMADD231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1928 $xmm0 = VFMADD231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1929 ; CHECK: $xmm0 = VFMADD231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1930 $xmm0 = VFMADD231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1931 ; CHECK: $xmm0 = VFMADD231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1932 $xmm0 = VFMADD231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1933 ; CHECK: $xmm0 = VFMSUB132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1934 $xmm0 = VFMSUB132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1935 ; CHECK: $xmm0 = VFMSUB132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1936 $xmm0 = VFMSUB132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1937 ; CHECK: $xmm0 = VFMSUB132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1938 $xmm0 = VFMSUB132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1939 ; CHECK: $xmm0 = VFMSUB132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1940 $xmm0 = VFMSUB132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1941 ; CHECK: $xmm0 = VFMSUB132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1942 $xmm0 = VFMSUB132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1943 ; CHECK: $xmm0 = VFMSUB132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1944 $xmm0 = VFMSUB132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1945 ; CHECK: $xmm0 = VFMSUB132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1946 $xmm0 = VFMSUB132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1947 ; CHECK: $xmm0 = VFMSUB132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1948 $xmm0 = VFMSUB132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1949 ; CHECK: $xmm0 = VFMSUB213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1950 $xmm0 = VFMSUB213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1951 ; CHECK: $xmm0 = VFMSUB213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1952 $xmm0 = VFMSUB213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1953 ; CHECK: $xmm0 = VFMSUB213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1954 $xmm0 = VFMSUB213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1955 ; CHECK: $xmm0 = VFMSUB213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1956 $xmm0 = VFMSUB213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1957 ; CHECK: $xmm0 = VFMSUB213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1958 $xmm0 = VFMSUB213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1959 ; CHECK: $xmm0 = VFMSUB213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1960 $xmm0 = VFMSUB213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1961 ; CHECK: $xmm0 = VFMSUB213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1962 $xmm0 = VFMSUB213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1963 ; CHECK: $xmm0 = VFMSUB213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1964 $xmm0 = VFMSUB213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1965 ; CHECK: $xmm0 = VFMSUB231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1966 $xmm0 = VFMSUB231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1967 ; CHECK: $xmm0 = VFMSUB231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1968 $xmm0 = VFMSUB231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1969 ; CHECK: $xmm0 = VFMSUB231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1970 $xmm0 = VFMSUB231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1971 ; CHECK: $xmm0 = VFMSUB231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1972 $xmm0 = VFMSUB231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1973 ; CHECK: $xmm0 = VFMSUB231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1974 $xmm0 = VFMSUB231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1975 ; CHECK: $xmm0 = VFMSUB231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1976 $xmm0 = VFMSUB231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1977 ; CHECK: $xmm0 = VFMSUB231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1978 $xmm0 = VFMSUB231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1979 ; CHECK: $xmm0 = VFMSUB231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1980 $xmm0 = VFMSUB231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1981 ; CHECK: $xmm0 = VFNMADD132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1982 $xmm0 = VFNMADD132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1983 ; CHECK: $xmm0 = VFNMADD132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1984 $xmm0 = VFNMADD132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1985 ; CHECK: $xmm0 = VFNMADD132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1986 $xmm0 = VFNMADD132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1987 ; CHECK: $xmm0 = VFNMADD132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1988 $xmm0 = VFNMADD132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1989 ; CHECK: $xmm0 = VFNMADD132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1990 $xmm0 = VFNMADD132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1991 ; CHECK: $xmm0 = VFNMADD132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1992 $xmm0 = VFNMADD132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1993 ; CHECK: $xmm0 = VFNMADD132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1994 $xmm0 = VFNMADD132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
1995 ; CHECK: $xmm0 = VFNMADD132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1996 $xmm0 = VFNMADD132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
1997 ; CHECK: $xmm0 = VFNMADD213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1998 $xmm0 = VFNMADD213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
1999 ; CHECK: $xmm0 = VFNMADD213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2000 $xmm0 = VFNMADD213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2001 ; CHECK: $xmm0 = VFNMADD213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2002 $xmm0 = VFNMADD213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2003 ; CHECK: $xmm0 = VFNMADD213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2004 $xmm0 = VFNMADD213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2005 ; CHECK: $xmm0 = VFNMADD213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2006 $xmm0 = VFNMADD213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2007 ; CHECK: $xmm0 = VFNMADD213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2008 $xmm0 = VFNMADD213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2009 ; CHECK: $xmm0 = VFNMADD213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2010 $xmm0 = VFNMADD213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2011 ; CHECK: $xmm0 = VFNMADD213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2012 $xmm0 = VFNMADD213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2013 ; CHECK: $xmm0 = VFNMADD231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2014 $xmm0 = VFNMADD231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2015 ; CHECK: $xmm0 = VFNMADD231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2016 $xmm0 = VFNMADD231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2017 ; CHECK: $xmm0 = VFNMADD231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2018 $xmm0 = VFNMADD231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2019 ; CHECK: $xmm0 = VFNMADD231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2020 $xmm0 = VFNMADD231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2021 ; CHECK: $xmm0 = VFNMADD231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2022 $xmm0 = VFNMADD231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2023 ; CHECK: $xmm0 = VFNMADD231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2024 $xmm0 = VFNMADD231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2025 ; CHECK: $xmm0 = VFNMADD231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2026 $xmm0 = VFNMADD231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2027 ; CHECK: $xmm0 = VFNMADD231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2028 $xmm0 = VFNMADD231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2029 ; CHECK: $xmm0 = VFNMSUB132SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2030 $xmm0 = VFNMSUB132SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2031 ; CHECK: $xmm0 = VFNMSUB132SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2032 $xmm0 = VFNMSUB132SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2033 ; CHECK: $xmm0 = VFNMSUB132SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2034 $xmm0 = VFNMSUB132SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2035 ; CHECK: $xmm0 = VFNMSUB132SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2036 $xmm0 = VFNMSUB132SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2037 ; CHECK: $xmm0 = VFNMSUB132SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2038 $xmm0 = VFNMSUB132SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2039 ; CHECK: $xmm0 = VFNMSUB132SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2040 $xmm0 = VFNMSUB132SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2041 ; CHECK: $xmm0 = VFNMSUB132SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2042 $xmm0 = VFNMSUB132SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2043 ; CHECK: $xmm0 = VFNMSUB132SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2044 $xmm0 = VFNMSUB132SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2045 ; CHECK: $xmm0 = VFNMSUB213SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2046 $xmm0 = VFNMSUB213SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2047 ; CHECK: $xmm0 = VFNMSUB213SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2048 $xmm0 = VFNMSUB213SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2049 ; CHECK: $xmm0 = VFNMSUB213SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2050 $xmm0 = VFNMSUB213SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2051 ; CHECK: $xmm0 = VFNMSUB213SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2052 $xmm0 = VFNMSUB213SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2053 ; CHECK: $xmm0 = VFNMSUB213SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2054 $xmm0 = VFNMSUB213SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2055 ; CHECK: $xmm0 = VFNMSUB213SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2056 $xmm0 = VFNMSUB213SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2057 ; CHECK: $xmm0 = VFNMSUB213SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2058 $xmm0 = VFNMSUB213SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2059 ; CHECK: $xmm0 = VFNMSUB213SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2060 $xmm0 = VFNMSUB213SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2061 ; CHECK: $xmm0 = VFNMSUB231SDm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2062 $xmm0 = VFNMSUB231SDZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2063 ; CHECK: $xmm0 = VFNMSUB231SDm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2064 $xmm0 = VFNMSUB231SDZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2065 ; CHECK: $xmm0 = VFNMSUB231SDr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2066 $xmm0 = VFNMSUB231SDZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2067 ; CHECK: $xmm0 = VFNMSUB231SDr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2068 $xmm0 = VFNMSUB231SDZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2069 ; CHECK: $xmm0 = VFNMSUB231SSm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2070 $xmm0 = VFNMSUB231SSZm $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2071 ; CHECK: $xmm0 = VFNMSUB231SSm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2072 $xmm0 = VFNMSUB231SSZm_Int $xmm0, $xmm0, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2073 ; CHECK: $xmm0 = VFNMSUB231SSr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2074 $xmm0 = VFNMSUB231SSZr $xmm0, $xmm1, $xmm2, implicit $mxcsr
2075 ; CHECK: $xmm0 = VFNMSUB231SSr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2076 $xmm0 = VFNMSUB231SSZr_Int $xmm0, $xmm1, $xmm2, implicit $mxcsr
2077 ; CHECK: VPEXTRBmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
2078 VPEXTRBZmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
2079 ; CHECK: $eax = VPEXTRBrr $xmm0, 1
2080 $eax = VPEXTRBZrr $xmm0, 1
2081 ; CHECK: VPEXTRDmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
2082 VPEXTRDZmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
2083 ; CHECK: $eax = VPEXTRDrr $xmm0, 1
2084 $eax = VPEXTRDZrr $xmm0, 1
2085 ; CHECK: VPEXTRQmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
2086 VPEXTRQZmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
2087 ; CHECK: $rax = VPEXTRQrr $xmm0, 1
2088 $rax = VPEXTRQZrr $xmm0, 1
2089 ; CHECK: VPEXTRWmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
2090 VPEXTRWZmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 3
2091 ; CHECK: $eax = VPEXTRWrr $xmm0, 1
2092 $eax = VPEXTRWZrr $xmm0, 1
2093 ; CHECK: $xmm0 = VPINSRBrm $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
2094 $xmm0 = VPINSRBZrm $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
2095 ; CHECK: $xmm0 = VPINSRBrr $xmm0, $edi, 5
2096 $xmm0 = VPINSRBZrr $xmm0, $edi, 5
2097 ; CHECK: $xmm0 = VPINSRDrm $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
2098 $xmm0 = VPINSRDZrm $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
2099 ; CHECK: $xmm0 = VPINSRDrr $xmm0, $edi, 5
2100 $xmm0 = VPINSRDZrr $xmm0, $edi, 5
2101 ; CHECK: $xmm0 = VPINSRQrm $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
2102 $xmm0 = VPINSRQZrm $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
2103 ; CHECK: $xmm0 = VPINSRQrr $xmm0, $rdi, 5
2104 $xmm0 = VPINSRQZrr $xmm0, $rdi, 5
2105 ; CHECK: $xmm0 = VPINSRWrm $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
2106 $xmm0 = VPINSRWZrm $xmm0, $rsi, 1, $noreg, 0, $noreg, 3
2107 ; CHECK: $xmm0 = VPINSRWrr $xmm0, $edi, 5
2108 $xmm0 = VPINSRWZrr $xmm0, $edi, 5
2109 ; CHECK: $xmm0 = VSQRTSDm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2110 $xmm0 = VSQRTSDZm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2111 ; CHECK: $xmm0 = VSQRTSDm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2112 $xmm0 = VSQRTSDZm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2113 ; CHECK: $xmm0 = VSQRTSDr $xmm0, $xmm0, implicit $mxcsr
2114 $xmm0 = VSQRTSDZr $xmm0, $xmm0, implicit $mxcsr
2115 ; CHECK: $xmm0 = VSQRTSDr_Int $xmm0, $xmm0, implicit $mxcsr
2116 $xmm0 = VSQRTSDZr_Int $xmm0, $xmm0, implicit $mxcsr
2117 ; CHECK: $xmm0 = VSQRTSSm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2118 $xmm0 = VSQRTSSZm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2119 ; CHECK: $xmm0 = VSQRTSSm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2120 $xmm0 = VSQRTSSZm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2121 ; CHECK: $xmm0 = VSQRTSSr $xmm0, $xmm1, implicit $mxcsr
2122 $xmm0 = VSQRTSSZr $xmm0, $xmm1, implicit $mxcsr
2123 ; CHECK: $xmm0 = VSQRTSSr_Int $xmm0, $xmm1, implicit $mxcsr
2124 $xmm0 = VSQRTSSZr_Int $xmm0, $xmm1, implicit $mxcsr
2125 ; CHECK: $rdi = VCVTSD2SI64rr_Int $xmm0, implicit $mxcsr
2126 $rdi = VCVTSD2SI64Zrr_Int $xmm0, implicit $mxcsr
2127 ; CHECK: $edi = VCVTSD2SIrr_Int $xmm0, implicit $mxcsr
2128 $edi = VCVTSD2SIZrr_Int $xmm0, implicit $mxcsr
2129 ; CHECK: $xmm0 = VCVTSD2SSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2130 $xmm0 = VCVTSD2SSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2131 ; CHECK: $xmm0 = VCVTSD2SSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2132 $xmm0 = VCVTSD2SSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2133 ; CHECK: $xmm0 = VCVTSD2SSrr $xmm0, $xmm1, implicit $mxcsr
2134 $xmm0 = VCVTSD2SSZrr $xmm0, $xmm1, implicit $mxcsr
2135 ; CHECK: $xmm0 = VCVTSD2SSrr_Int $xmm0, $xmm1, implicit $mxcsr
2136 $xmm0 = VCVTSD2SSZrr_Int $xmm0, $xmm1, implicit $mxcsr
2137 ; CHECK: $xmm0 = VCVTSI2SDrm $xmm0, $rdi, 1, $noreg, 0, $noreg
2138 $xmm0 = VCVTSI2SDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg
2139 ; CHECK: $xmm0 = VCVTSI2SDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg
2140 $xmm0 = VCVTSI2SDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg
2141 ; CHECK: $xmm0 = VCVTSI2SDrr $xmm0, $edi
2142 $xmm0 = VCVTSI2SDZrr $xmm0, $edi
2143 ; CHECK: $xmm0 = VCVTSI2SDrr_Int $xmm0, $edi
2144 $xmm0 = VCVTSI2SDZrr_Int $xmm0, $edi
2145 ; CHECK: $xmm0 = VCVTSI2SSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2146 $xmm0 = VCVTSI2SSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2147 ; CHECK: $xmm0 = VCVTSI2SSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2148 $xmm0 = VCVTSI2SSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2149 ; CHECK: $xmm0 = VCVTSI2SSrr $xmm0, $edi, implicit $mxcsr
2150 $xmm0 = VCVTSI2SSZrr $xmm0, $edi, implicit $mxcsr
2151 ; CHECK: $xmm0 = VCVTSI2SSrr_Int $xmm0, $edi, implicit $mxcsr
2152 $xmm0 = VCVTSI2SSZrr_Int $xmm0, $edi, implicit $mxcsr
2153 ; CHECK: $xmm0 = VCVTSI642SDrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2154 $xmm0 = VCVTSI642SDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2155 ; CHECK: $xmm0 = VCVTSI642SDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2156 $xmm0 = VCVTSI642SDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2157 ; CHECK: $xmm0 = VCVTSI642SDrr $xmm0, $rdi, implicit $mxcsr
2158 $xmm0 = VCVTSI642SDZrr $xmm0, $rdi, implicit $mxcsr
2159 ; CHECK: $xmm0 = VCVTSI642SDrr_Int $xmm0, $rdi, implicit $mxcsr
2160 $xmm0 = VCVTSI642SDZrr_Int $xmm0, $rdi, implicit $mxcsr
2161 ; CHECK: $xmm0 = VCVTSI642SSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2162 $xmm0 = VCVTSI642SSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2163 ; CHECK: $xmm0 = VCVTSI642SSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2164 $xmm0 = VCVTSI642SSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2165 ; CHECK: $xmm0 = VCVTSI642SSrr $xmm0, $rdi, implicit $mxcsr
2166 $xmm0 = VCVTSI642SSZrr $xmm0, $rdi, implicit $mxcsr
2167 ; CHECK: $xmm0 = VCVTSI642SSrr_Int $xmm0, $rdi, implicit $mxcsr
2168 $xmm0 = VCVTSI642SSZrr_Int $xmm0, $rdi, implicit $mxcsr
2169 ; CHECK: $xmm0 = VCVTSS2SDrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2170 $xmm0 = VCVTSS2SDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2171 ; CHECK: $xmm0 = VCVTSS2SDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2172 $xmm0 = VCVTSS2SDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2173 ; CHECK: $xmm0 = VCVTSS2SDrr $xmm0, $xmm1, implicit $mxcsr
2174 $xmm0 = VCVTSS2SDZrr $xmm0, $xmm1, implicit $mxcsr
2175 ; CHECK: $xmm0 = VCVTSS2SDrr_Int $xmm0, $xmm1, implicit $mxcsr
2176 $xmm0 = VCVTSS2SDZrr_Int $xmm0, $xmm1, implicit $mxcsr
2177 ; CHECK: $rdi = VCVTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2178 $rdi = VCVTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2179 ; CHECK: $rdi = VCVTSS2SI64rr_Int $xmm0, implicit $mxcsr
2180 $rdi = VCVTSS2SI64Zrr_Int $xmm0, implicit $mxcsr
2181 ; CHECK: $edi = VCVTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2182 $edi = VCVTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2183 ; CHECK: $edi = VCVTSS2SIrr_Int $xmm0, implicit $mxcsr
2184 $edi = VCVTSS2SIZrr_Int $xmm0, implicit $mxcsr
2185 ; CHECK: $rdi = VCVTTSD2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2186 $rdi = VCVTTSD2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2187 ; CHECK: $rdi = VCVTTSD2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2188 $rdi = VCVTTSD2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2189 ; CHECK: $rdi = VCVTTSD2SI64rr $xmm0, implicit $mxcsr
2190 $rdi = VCVTTSD2SI64Zrr $xmm0, implicit $mxcsr
2191 ; CHECK: $rdi = VCVTTSD2SI64rr_Int $xmm0, implicit $mxcsr
2192 $rdi = VCVTTSD2SI64Zrr_Int $xmm0, implicit $mxcsr
2193 ; CHECK: $edi = VCVTTSD2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2194 $edi = VCVTTSD2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2195 ; CHECK: $edi = VCVTTSD2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2196 $edi = VCVTTSD2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2197 ; CHECK: $edi = VCVTTSD2SIrr $xmm0, implicit $mxcsr
2198 $edi = VCVTTSD2SIZrr $xmm0, implicit $mxcsr
2199 ; CHECK: $edi = VCVTTSD2SIrr_Int $xmm0, implicit $mxcsr
2200 $edi = VCVTTSD2SIZrr_Int $xmm0, implicit $mxcsr
2201 ; CHECK: $rdi = VCVTTSS2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2202 $rdi = VCVTTSS2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2203 ; CHECK: $rdi = VCVTTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2204 $rdi = VCVTTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2205 ; CHECK: $rdi = VCVTTSS2SI64rr $xmm0, implicit $mxcsr
2206 $rdi = VCVTTSS2SI64Zrr $xmm0, implicit $mxcsr
2207 ; CHECK: $rdi = VCVTTSS2SI64rr_Int $xmm0, implicit $mxcsr
2208 $rdi = VCVTTSS2SI64Zrr_Int $xmm0, implicit $mxcsr
2209 ; CHECK: $edi = VCVTTSS2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2210 $edi = VCVTTSS2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2211 ; CHECK: $edi = VCVTTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2212 $edi = VCVTTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
2213 ; CHECK: $edi = VCVTTSS2SIrr $xmm0, implicit $mxcsr
2214 $edi = VCVTTSS2SIZrr $xmm0, implicit $mxcsr
2215 ; CHECK: $edi = VCVTTSS2SIrr_Int $xmm0, implicit $mxcsr
2216 $edi = VCVTTSS2SIZrr_Int $xmm0, implicit $mxcsr
2217 ; CHECK: $xmm0 = VMOV64toSDrr $rdi
2218 $xmm0 = VMOV64toSDZrr $rdi
2219 ; CHECK: $xmm0 = VMOVDI2SSrr $eax
2220 $xmm0 = VMOVDI2SSZrr $eax
2221 ; CHECK: VMOVSDmr $rdi, 1, $noreg, 0, $noreg, $xmm0
2222 VMOVSDZmr $rdi, 1, $noreg, 0, $noreg, $xmm0
2223 ; CHECK: $xmm0 = VMOVSDrm $rip, 1, $noreg, 0, $noreg
2224 $xmm0 = VMOVSDZrm $rip, 1, $noreg, 0, $noreg
2225 ; CHECK: $xmm0 = VMOVSDrm_alt $rip, 1, $noreg, 0, $noreg
2226 $xmm0 = VMOVSDZrm_alt $rip, 1, $noreg, 0, $noreg
2227 ; CHECK: $xmm0 = VMOVSDrr $xmm0, $xmm1
2228 $xmm0 = VMOVSDZrr $xmm0, $xmm1
2229 ; CHECK: $rax = VMOVSDto64rr $xmm0
2230 $rax = VMOVSDto64Zrr $xmm0
2231 ; CHECK: VMOVSSmr $rdi, 1, $noreg, 0, $noreg, $xmm0
2232 VMOVSSZmr $rdi, 1, $noreg, 0, $noreg, $xmm0
2233 ; CHECK: $xmm0 = VMOVSSrm $rip, 1, $noreg, 0, $noreg
2234 $xmm0 = VMOVSSZrm $rip, 1, $noreg, 0, $noreg
2235 ; CHECK: $xmm0 = VMOVSSrm_alt $rip, 1, $noreg, 0, $noreg
2236 $xmm0 = VMOVSSZrm_alt $rip, 1, $noreg, 0, $noreg
2237 ; CHECK: $xmm0 = VMOVSSrr $xmm0, $xmm1
2238 $xmm0 = VMOVSSZrr $xmm0, $xmm1
2239 ; CHECK: $eax = VMOVSS2DIrr $xmm0
2240 $eax = VMOVSS2DIZrr $xmm0
2241 ; CHECK: $xmm0 = VMOV64toPQIrr $rdi
2242 $xmm0 = VMOV64toPQIZrr $rdi
2243 ; CHECK: $xmm0 = VMOV64toPQIrm $rdi, 1, $noreg, 0, $noreg
2244 $xmm0 = VMOV64toPQIZrm $rdi, 1, $noreg, 0, $noreg
2245 ; CHECK: $xmm0 = VMOV64toSDrr $rdi
2246 $xmm0 = VMOV64toSDZrr $rdi
2247 ; CHECK: $xmm0 = VMOVDI2PDIrm $rip, 1, $noreg, 0, $noreg
2248 $xmm0 = VMOVDI2PDIZrm $rip, 1, $noreg, 0, $noreg
2249 ; CHECK: $xmm0 = VMOVDI2PDIrr $edi
2250 $xmm0 = VMOVDI2PDIZrr $edi
2251 ; CHECK: $xmm0 = VMOVLHPSrr $xmm0, $xmm1
2252 $xmm0 = VMOVLHPSZrr $xmm0, $xmm1
2253 ; CHECK: $xmm0 = VMOVHLPSrr $xmm0, $xmm1
2254 $xmm0 = VMOVHLPSZrr $xmm0, $xmm1
2255 ; CHECK: VMOVPDI2DImr $rdi, 1, $noreg, 0, $noreg, $xmm0
2256 VMOVPDI2DIZmr $rdi, 1, $noreg, 0, $noreg, $xmm0
2257 ; CHECK: $edi = VMOVPDI2DIrr $xmm0
2258 $edi = VMOVPDI2DIZrr $xmm0
2259 ; CHECK: $xmm0 = VMOVPQI2QIrr $xmm0
2260 $xmm0 = VMOVPQI2QIZrr $xmm0
2261 ; CHECK: VMOVPQI2QImr $rdi, 1, $noreg, 0, $noreg, $xmm0
2262 VMOVPQI2QIZmr $rdi, 1, $noreg, 0, $noreg, $xmm0
2263 ; CHECK: $rdi = VMOVPQIto64rr $xmm0
2264 $rdi = VMOVPQIto64Zrr $xmm0
2265 ; CHECK: VMOVPQIto64mr $rdi, 1, $noreg, 0, $noreg, $xmm0
2266 VMOVPQIto64Zmr $rdi, 1, $noreg, 0, $noreg, $xmm0
2267 ; CHECK: $xmm0 = VMOVQI2PQIrm $rip, 1, $noreg, 0, $noreg
2268 $xmm0 = VMOVQI2PQIZrm $rip, 1, $noreg, 0, $noreg
2269 ; CHECK: $xmm0 = VMOVZPQILo2PQIrr $xmm0
2270 $xmm0 = VMOVZPQILo2PQIZrr $xmm0
2271 ; CHECK: VCOMISDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2272 VCOMISDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2273 ; CHECK: VCOMISDrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2274 VCOMISDZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2275 ; CHECK: VCOMISSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2276 VCOMISSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2277 ; CHECK: VCOMISSrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2278 VCOMISSZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2279 ; CHECK: VUCOMISDrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2280 VUCOMISDZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2281 ; CHECK: VUCOMISDrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2282 VUCOMISDZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2283 ; CHECK: VUCOMISSrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2284 VUCOMISSZrm_Int $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2285 ; CHECK: VUCOMISSrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2286 VUCOMISSZrr_Int $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2287 ; CHECK: VCOMISDrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2288 VCOMISDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2289 ; CHECK: VCOMISDrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2290 VCOMISDZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2291 ; CHECK: VCOMISSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2292 VCOMISSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2293 ; CHECK: VCOMISSrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2294 VCOMISSZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2295 ; CHECK: VUCOMISDrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2296 VUCOMISDZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2297 ; CHECK: VUCOMISDrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2298 VUCOMISDZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2299 ; CHECK: VUCOMISSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2300 VUCOMISSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
2301 ; CHECK: VUCOMISSrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2302 VUCOMISSZrr $xmm0, $xmm1, implicit-def $eflags, implicit $mxcsr
2303 ; CHECK: VEXTRACTPSmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 1
2304 VEXTRACTPSZmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 1
2305 ; CHECK: $eax = VEXTRACTPSrr $xmm0, 1
2306 $eax = VEXTRACTPSZrr $xmm0, 1
2307 ; CHECK: $xmm0 = VINSERTPSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
2308 $xmm0 = VINSERTPSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
2309 ; CHECK: $xmm0 = VINSERTPSrr $xmm0, $xmm0, 1
2310 $xmm0 = VINSERTPSZrr $xmm0, $xmm0, 1
2311 ; CHECK: $xmm0 = VROUNDSDm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2312 $xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2313 ; CHECK: $xmm0 = VROUNDSDr $xmm0, $xmm1, 15, implicit $mxcsr
2314 $xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 15, implicit $mxcsr
2315 ; CHECK: $xmm0 = VROUNDSSm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2316 $xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2317 ; CHECK: $xmm0 = VROUNDSSr $xmm0, $xmm1, 15, implicit $mxcsr
2318 $xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 15, implicit $mxcsr
2319 ; CHECK: $xmm0 = VROUNDSDm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2320 $xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2321 ; CHECK: $xmm0 = VROUNDSDr_Int $xmm0, $xmm1, 15, implicit $mxcsr
2322 $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 15, implicit $mxcsr
2323 ; CHECK: $xmm0 = VROUNDSSm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2324 $xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2325 ; CHECK: $xmm0 = VROUNDSSr_Int $xmm0, $xmm1, 15, implicit $mxcsr
2326 $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 15, implicit $mxcsr
2328 RET64
2329 ...
2330 ---
2331 # CHECK-LABEL: name: evex_z256_to_evex_test
2332 # CHECK: bb.0:
2334 name: evex_z256_to_evex_test
2335 body: |
2336 bb.0:
2337 ; CHECK: VMOVAPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2338 VMOVAPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2339 ; CHECK: $ymm16 = VMOVAPDZ256rm $rip, 1, $noreg, 0, $noreg
2340 $ymm16 = VMOVAPDZ256rm $rip, 1, $noreg, 0, $noreg
2341 ; CHECK: $ymm16 = VMOVAPDZ256rr $ymm16
2342 $ymm16 = VMOVAPDZ256rr $ymm16
2343 ; CHECK: VMOVAPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2344 VMOVAPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2345 ; CHECK: $ymm16 = VMOVAPSZ256rm $rip, 1, $noreg, 0, $noreg
2346 $ymm16 = VMOVAPSZ256rm $rip, 1, $noreg, 0, $noreg
2347 ; CHECK: $ymm16 = VMOVAPSZ256rr $ymm16
2348 $ymm16 = VMOVAPSZ256rr $ymm16
2349 ; CHECK: $ymm16 = VMOVDDUPZ256rm $rip, 1, $noreg, 0, $noreg
2350 $ymm16 = VMOVDDUPZ256rm $rip, 1, $noreg, 0, $noreg
2351 ; CHECK: $ymm16 = VMOVDDUPZ256rr $ymm16
2352 $ymm16 = VMOVDDUPZ256rr $ymm16
2353 ; CHECK: VMOVDQA32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2354 VMOVDQA32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2355 ; CHECK: $ymm16 = VMOVDQA32Z256rm $rip, 1, $noreg, 0, $noreg
2356 $ymm16 = VMOVDQA32Z256rm $rip, 1, $noreg, 0, $noreg
2357 ; CHECK: $ymm16 = VMOVDQA32Z256rr $ymm16
2358 $ymm16 = VMOVDQA32Z256rr $ymm16
2359 ; CHECK: VMOVDQA64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2360 VMOVDQA64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2361 ; CHECK: $ymm16 = VMOVDQA64Z256rm $rip, 1, $noreg, 0, $noreg
2362 $ymm16 = VMOVDQA64Z256rm $rip, 1, $noreg, 0, $noreg
2363 ; CHECK: $ymm16 = VMOVDQA64Z256rr $ymm16
2364 $ymm16 = VMOVDQA64Z256rr $ymm16
2365 ; CHECK: VMOVDQU16Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2366 VMOVDQU16Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2367 ; CHECK: $ymm16 = VMOVDQU16Z256rm $rip, 1, $noreg, 0, $noreg
2368 $ymm16 = VMOVDQU16Z256rm $rip, 1, $noreg, 0, $noreg
2369 ; CHECK: $ymm16 = VMOVDQU16Z256rr $ymm16
2370 $ymm16 = VMOVDQU16Z256rr $ymm16
2371 ; CHECK: VMOVDQU32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2372 VMOVDQU32Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2373 ; CHECK: $ymm16 = VMOVDQU32Z256rm $rip, 1, $noreg, 0, $noreg
2374 $ymm16 = VMOVDQU32Z256rm $rip, 1, $noreg, 0, $noreg
2375 ; CHECK: $ymm16 = VMOVDQU32Z256rr $ymm16
2376 $ymm16 = VMOVDQU32Z256rr $ymm16
2377 ; CHECK: VMOVDQU64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2378 VMOVDQU64Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2379 ; CHECK: $ymm16 = VMOVDQU64Z256rm $rip, 1, $noreg, 0, $noreg
2380 $ymm16 = VMOVDQU64Z256rm $rip, 1, $noreg, 0, $noreg
2381 ; CHECK: $ymm16 = VMOVDQU64Z256rr $ymm16
2382 $ymm16 = VMOVDQU64Z256rr $ymm16
2383 ; CHECK: VMOVDQU8Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2384 VMOVDQU8Z256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2385 ; CHECK: $ymm16 = VMOVDQU8Z256rm $rip, 1, $noreg, 0, $noreg
2386 $ymm16 = VMOVDQU8Z256rm $rip, 1, $noreg, 0, $noreg
2387 ; CHECK: $ymm16 = VMOVDQU8Z256rr $ymm16
2388 $ymm16 = VMOVDQU8Z256rr $ymm16
2389 ; CHECK: $ymm16 = VMOVNTDQAZ256rm $rip, 1, $noreg, 0, $noreg
2390 $ymm16 = VMOVNTDQAZ256rm $rip, 1, $noreg, 0, $noreg
2391 ; CHECK: VMOVNTDQZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2392 VMOVNTDQZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2393 ; CHECK: VMOVNTPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2394 VMOVNTPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2395 ; CHECK: VMOVNTPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2396 VMOVNTPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2397 ; CHECK: $ymm16 = VMOVSHDUPZ256rm $rip, 1, $noreg, 0, $noreg
2398 $ymm16 = VMOVSHDUPZ256rm $rip, 1, $noreg, 0, $noreg
2399 ; CHECK: $ymm16 = VMOVSHDUPZ256rr $ymm16
2400 $ymm16 = VMOVSHDUPZ256rr $ymm16
2401 ; CHECK: $ymm16 = VMOVSLDUPZ256rm $rip, 1, $noreg, 0, $noreg
2402 $ymm16 = VMOVSLDUPZ256rm $rip, 1, $noreg, 0, $noreg
2403 ; CHECK: $ymm16 = VMOVSLDUPZ256rr $ymm16
2404 $ymm16 = VMOVSLDUPZ256rr $ymm16
2405 ; CHECK: VMOVUPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2406 VMOVUPDZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2407 ; CHECK: $ymm16 = VMOVUPDZ256rm $rip, 1, $noreg, 0, $noreg
2408 $ymm16 = VMOVUPDZ256rm $rip, 1, $noreg, 0, $noreg
2409 ; CHECK: $ymm16 = VMOVUPDZ256rr $ymm16
2410 $ymm16 = VMOVUPDZ256rr $ymm16
2411 ; CHECK: VMOVUPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2412 VMOVUPSZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16
2413 ; CHECK: $ymm16 = VPANDDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2414 $ymm16 = VPANDDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2415 ; CHECK: $ymm16 = VPANDDZ256rr $ymm16, $ymm1
2416 $ymm16 = VPANDDZ256rr $ymm16, $ymm1
2417 ; CHECK: $ymm16 = VPANDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2418 $ymm16 = VPANDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2419 ; CHECK: $ymm16 = VPANDQZ256rr $ymm16, $ymm1
2420 $ymm16 = VPANDQZ256rr $ymm16, $ymm1
2421 ; CHECK: $ymm16 = VPANDNDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2422 $ymm16 = VPANDNDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2423 ; CHECK: $ymm16 = VPANDNDZ256rr $ymm16, $ymm1
2424 $ymm16 = VPANDNDZ256rr $ymm16, $ymm1
2425 ; CHECK: $ymm16 = VPANDNQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2426 $ymm16 = VPANDNQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2427 ; CHECK: $ymm16 = VPANDNQZ256rr $ymm16, $ymm1
2428 $ymm16 = VPANDNQZ256rr $ymm16, $ymm1
2429 ; CHECK: $ymm16 = VPAVGBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2430 $ymm16 = VPAVGBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2431 ; CHECK: $ymm16 = VPAVGBZ256rr $ymm16, $ymm1
2432 $ymm16 = VPAVGBZ256rr $ymm16, $ymm1
2433 ; CHECK: $ymm16 = VPAVGWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2434 $ymm16 = VPAVGWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2435 ; CHECK: $ymm16 = VPAVGWZ256rr $ymm16, $ymm1
2436 $ymm16 = VPAVGWZ256rr $ymm16, $ymm1
2437 ; CHECK: $ymm16 = VPADDBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2438 $ymm16 = VPADDBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2439 ; CHECK: $ymm16 = VPADDBZ256rr $ymm16, $ymm1
2440 $ymm16 = VPADDBZ256rr $ymm16, $ymm1
2441 ; CHECK: $ymm16 = VPADDDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2442 $ymm16 = VPADDDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2443 ; CHECK: $ymm16 = VPADDDZ256rr $ymm16, $ymm1
2444 $ymm16 = VPADDDZ256rr $ymm16, $ymm1
2445 ; CHECK: $ymm16 = VPADDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2446 $ymm16 = VPADDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2447 ; CHECK: $ymm16 = VPADDQZ256rr $ymm16, $ymm1
2448 $ymm16 = VPADDQZ256rr $ymm16, $ymm1
2449 ; CHECK: $ymm16 = VPADDSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2450 $ymm16 = VPADDSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2451 ; CHECK: $ymm16 = VPADDSBZ256rr $ymm16, $ymm1
2452 $ymm16 = VPADDSBZ256rr $ymm16, $ymm1
2453 ; CHECK: $ymm16 = VPADDSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2454 $ymm16 = VPADDSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2455 ; CHECK: $ymm16 = VPADDSWZ256rr $ymm16, $ymm1
2456 $ymm16 = VPADDSWZ256rr $ymm16, $ymm1
2457 ; CHECK: $ymm16 = VPADDUSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2458 $ymm16 = VPADDUSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2459 ; CHECK: $ymm16 = VPADDUSBZ256rr $ymm16, $ymm1
2460 $ymm16 = VPADDUSBZ256rr $ymm16, $ymm1
2461 ; CHECK: $ymm16 = VPADDUSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2462 $ymm16 = VPADDUSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2463 ; CHECK: $ymm16 = VPADDUSWZ256rr $ymm16, $ymm1
2464 $ymm16 = VPADDUSWZ256rr $ymm16, $ymm1
2465 ; CHECK: $ymm16 = VPADDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2466 $ymm16 = VPADDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2467 ; CHECK: $ymm16 = VPADDWZ256rr $ymm16, $ymm1
2468 $ymm16 = VPADDWZ256rr $ymm16, $ymm1
2469 ; CHECK: $ymm16 = VMULPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2470 $ymm16 = VMULPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2471 ; CHECK: $ymm16 = VMULPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2472 $ymm16 = VMULPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2473 ; CHECK: $ymm16 = VMULPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2474 $ymm16 = VMULPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2475 ; CHECK: $ymm16 = VMULPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2476 $ymm16 = VMULPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2477 ; CHECK: $ymm16 = VORPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2478 $ymm16 = VORPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2479 ; CHECK: $ymm16 = VORPDZ256rr $ymm16, $ymm1
2480 $ymm16 = VORPDZ256rr $ymm16, $ymm1
2481 ; CHECK: $ymm16 = VORPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2482 $ymm16 = VORPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2483 ; CHECK: $ymm16 = VORPSZ256rr $ymm16, $ymm1
2484 $ymm16 = VORPSZ256rr $ymm16, $ymm1
2485 ; CHECK: $ymm16 = VPMADDUBSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2486 $ymm16 = VPMADDUBSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2487 ; CHECK: $ymm16 = VPMADDUBSWZ256rr $ymm16, $ymm1
2488 $ymm16 = VPMADDUBSWZ256rr $ymm16, $ymm1
2489 ; CHECK: $ymm16 = VPMADDWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2490 $ymm16 = VPMADDWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2491 ; CHECK: $ymm16 = VPMADDWDZ256rr $ymm16, $ymm1
2492 $ymm16 = VPMADDWDZ256rr $ymm16, $ymm1
2493 ; CHECK: $ymm16 = VPMAXSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2494 $ymm16 = VPMAXSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2495 ; CHECK: $ymm16 = VPMAXSBZ256rr $ymm16, $ymm1
2496 $ymm16 = VPMAXSBZ256rr $ymm16, $ymm1
2497 ; CHECK: $ymm16 = VPMAXSDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2498 $ymm16 = VPMAXSDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2499 ; CHECK: $ymm16 = VPMAXSDZ256rr $ymm16, $ymm1
2500 $ymm16 = VPMAXSDZ256rr $ymm16, $ymm1
2501 ; CHECK: $ymm16 = VPMAXSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2502 $ymm16 = VPMAXSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2503 ; CHECK: $ymm16 = VPMAXSWZ256rr $ymm16, $ymm1
2504 $ymm16 = VPMAXSWZ256rr $ymm16, $ymm1
2505 ; CHECK: $ymm16 = VPMAXUBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2506 $ymm16 = VPMAXUBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2507 ; CHECK: $ymm16 = VPMAXUBZ256rr $ymm16, $ymm1
2508 $ymm16 = VPMAXUBZ256rr $ymm16, $ymm1
2509 ; CHECK: $ymm16 = VPMAXUDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2510 $ymm16 = VPMAXUDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2511 ; CHECK: $ymm16 = VPMAXUDZ256rr $ymm16, $ymm1
2512 $ymm16 = VPMAXUDZ256rr $ymm16, $ymm1
2513 ; CHECK: $ymm16 = VPMAXUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2514 $ymm16 = VPMAXUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2515 ; CHECK: $ymm16 = VPMAXUWZ256rr $ymm16, $ymm1
2516 $ymm16 = VPMAXUWZ256rr $ymm16, $ymm1
2517 ; CHECK: $ymm16 = VPMINSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2518 $ymm16 = VPMINSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2519 ; CHECK: $ymm16 = VPMINSBZ256rr $ymm16, $ymm1
2520 $ymm16 = VPMINSBZ256rr $ymm16, $ymm1
2521 ; CHECK: $ymm16 = VPMINSDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2522 $ymm16 = VPMINSDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2523 ; CHECK: $ymm16 = VPMINSDZ256rr $ymm16, $ymm1
2524 $ymm16 = VPMINSDZ256rr $ymm16, $ymm1
2525 ; CHECK: $ymm16 = VPMINSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2526 $ymm16 = VPMINSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2527 ; CHECK: $ymm16 = VPMINSWZ256rr $ymm16, $ymm1
2528 $ymm16 = VPMINSWZ256rr $ymm16, $ymm1
2529 ; CHECK: $ymm16 = VPMINUBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2530 $ymm16 = VPMINUBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2531 ; CHECK: $ymm16 = VPMINUBZ256rr $ymm16, $ymm1
2532 $ymm16 = VPMINUBZ256rr $ymm16, $ymm1
2533 ; CHECK: $ymm16 = VPMINUDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2534 $ymm16 = VPMINUDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2535 ; CHECK: $ymm16 = VPMINUDZ256rr $ymm16, $ymm1
2536 $ymm16 = VPMINUDZ256rr $ymm16, $ymm1
2537 ; CHECK: $ymm16 = VPMINUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2538 $ymm16 = VPMINUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2539 ; CHECK: $ymm16 = VPMINUWZ256rr $ymm16, $ymm1
2540 $ymm16 = VPMINUWZ256rr $ymm16, $ymm1
2541 ; CHECK: $ymm16 = VPMULDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2542 $ymm16 = VPMULDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2543 ; CHECK: $ymm16 = VPMULDQZ256rr $ymm16, $ymm1
2544 $ymm16 = VPMULDQZ256rr $ymm16, $ymm1
2545 ; CHECK: $ymm16 = VPMULHRSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2546 $ymm16 = VPMULHRSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2547 ; CHECK: $ymm16 = VPMULHRSWZ256rr $ymm16, $ymm1
2548 $ymm16 = VPMULHRSWZ256rr $ymm16, $ymm1
2549 ; CHECK: $ymm16 = VPMULHUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2550 $ymm16 = VPMULHUWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2551 ; CHECK: $ymm16 = VPMULHUWZ256rr $ymm16, $ymm1
2552 $ymm16 = VPMULHUWZ256rr $ymm16, $ymm1
2553 ; CHECK: $ymm16 = VPMULHWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2554 $ymm16 = VPMULHWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2555 ; CHECK: $ymm16 = VPMULHWZ256rr $ymm16, $ymm1
2556 $ymm16 = VPMULHWZ256rr $ymm16, $ymm1
2557 ; CHECK: $ymm16 = VPMULLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2558 $ymm16 = VPMULLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2559 ; CHECK: $ymm16 = VPMULLDZ256rr $ymm16, $ymm1
2560 $ymm16 = VPMULLDZ256rr $ymm16, $ymm1
2561 ; CHECK: $ymm16 = VPMULLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2562 $ymm16 = VPMULLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2563 ; CHECK: $ymm16 = VPMULLWZ256rr $ymm16, $ymm1
2564 $ymm16 = VPMULLWZ256rr $ymm16, $ymm1
2565 ; CHECK: $ymm16 = VPMULUDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2566 $ymm16 = VPMULUDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2567 ; CHECK: $ymm16 = VPMULUDQZ256rr $ymm16, $ymm1
2568 $ymm16 = VPMULUDQZ256rr $ymm16, $ymm1
2569 ; CHECK: $ymm16 = VPORDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2570 $ymm16 = VPORDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2571 ; CHECK: $ymm16 = VPORDZ256rr $ymm16, $ymm1
2572 $ymm16 = VPORDZ256rr $ymm16, $ymm1
2573 ; CHECK: $ymm16 = VPORQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2574 $ymm16 = VPORQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2575 ; CHECK: $ymm16 = VPORQZ256rr $ymm16, $ymm1
2576 $ymm16 = VPORQZ256rr $ymm16, $ymm1
2577 ; CHECK: $ymm16 = VPSUBBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2578 $ymm16 = VPSUBBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2579 ; CHECK: $ymm16 = VPSUBBZ256rr $ymm16, $ymm1
2580 $ymm16 = VPSUBBZ256rr $ymm16, $ymm1
2581 ; CHECK: $ymm16 = VPSUBDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2582 $ymm16 = VPSUBDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2583 ; CHECK: $ymm16 = VPSUBDZ256rr $ymm16, $ymm1
2584 $ymm16 = VPSUBDZ256rr $ymm16, $ymm1
2585 ; CHECK: $ymm16 = VPSUBQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2586 $ymm16 = VPSUBQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2587 ; CHECK: $ymm16 = VPSUBQZ256rr $ymm16, $ymm1
2588 $ymm16 = VPSUBQZ256rr $ymm16, $ymm1
2589 ; CHECK: $ymm16 = VPSUBSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2590 $ymm16 = VPSUBSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2591 ; CHECK: $ymm16 = VPSUBSBZ256rr $ymm16, $ymm1
2592 $ymm16 = VPSUBSBZ256rr $ymm16, $ymm1
2593 ; CHECK: $ymm16 = VPSUBSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2594 $ymm16 = VPSUBSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2595 ; CHECK: $ymm16 = VPSUBSWZ256rr $ymm16, $ymm1
2596 $ymm16 = VPSUBSWZ256rr $ymm16, $ymm1
2597 ; CHECK: $ymm16 = VPSUBUSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2598 $ymm16 = VPSUBUSBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2599 ; CHECK: $ymm16 = VPSUBUSBZ256rr $ymm16, $ymm1
2600 $ymm16 = VPSUBUSBZ256rr $ymm16, $ymm1
2601 ; CHECK: $ymm16 = VPSUBUSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2602 $ymm16 = VPSUBUSWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2603 ; CHECK: $ymm16 = VPSUBUSWZ256rr $ymm16, $ymm1
2604 $ymm16 = VPSUBUSWZ256rr $ymm16, $ymm1
2605 ; CHECK: $ymm16 = VPSUBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2606 $ymm16 = VPSUBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2607 ; CHECK: $ymm16 = VPSUBWZ256rr $ymm16, $ymm1
2608 $ymm16 = VPSUBWZ256rr $ymm16, $ymm1
2609 ; CHECK: $ymm16 = VPXORDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2610 $ymm16 = VPXORDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2611 ; CHECK: $ymm16 = VPXORDZ256rr $ymm16, $ymm1
2612 $ymm16 = VPXORDZ256rr $ymm16, $ymm1
2613 ; CHECK: $ymm16 = VPXORQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2614 $ymm16 = VPXORQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2615 ; CHECK: $ymm16 = VPXORQZ256rr $ymm16, $ymm1
2616 $ymm16 = VPXORQZ256rr $ymm16, $ymm1
2617 ; CHECK: $ymm16 = VADDPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2618 $ymm16 = VADDPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2619 ; CHECK: $ymm16 = VADDPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2620 $ymm16 = VADDPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2621 ; CHECK: $ymm16 = VADDPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2622 $ymm16 = VADDPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2623 ; CHECK: $ymm16 = VADDPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2624 $ymm16 = VADDPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2625 ; CHECK: $ymm16 = VANDNPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2626 $ymm16 = VANDNPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2627 ; CHECK: $ymm16 = VANDNPDZ256rr $ymm16, $ymm1
2628 $ymm16 = VANDNPDZ256rr $ymm16, $ymm1
2629 ; CHECK: $ymm16 = VANDNPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2630 $ymm16 = VANDNPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2631 ; CHECK: $ymm16 = VANDNPSZ256rr $ymm16, $ymm1
2632 $ymm16 = VANDNPSZ256rr $ymm16, $ymm1
2633 ; CHECK: $ymm16 = VANDPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2634 $ymm16 = VANDPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2635 ; CHECK: $ymm16 = VANDPDZ256rr $ymm16, $ymm1
2636 $ymm16 = VANDPDZ256rr $ymm16, $ymm1
2637 ; CHECK: $ymm16 = VANDPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2638 $ymm16 = VANDPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2639 ; CHECK: $ymm16 = VANDPSZ256rr $ymm16, $ymm1
2640 $ymm16 = VANDPSZ256rr $ymm16, $ymm1
2641 ; CHECK: $ymm16 = VDIVPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2642 $ymm16 = VDIVPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2643 ; CHECK: $ymm16 = VDIVPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2644 $ymm16 = VDIVPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2645 ; CHECK: $ymm16 = VDIVPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2646 $ymm16 = VDIVPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2647 ; CHECK: $ymm16 = VDIVPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2648 $ymm16 = VDIVPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2649 ; CHECK: $ymm16 = VMAXCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2650 $ymm16 = VMAXCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2651 ; CHECK: $ymm16 = VMAXCPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2652 $ymm16 = VMAXCPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2653 ; CHECK: $ymm16 = VMAXCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2654 $ymm16 = VMAXCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2655 ; CHECK: $ymm16 = VMAXCPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2656 $ymm16 = VMAXCPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2657 ; CHECK: $ymm16 = VMAXPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2658 $ymm16 = VMAXPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2659 ; CHECK: $ymm16 = VMAXPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2660 $ymm16 = VMAXPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2661 ; CHECK: $ymm16 = VMAXPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2662 $ymm16 = VMAXPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2663 ; CHECK: $ymm16 = VMAXPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2664 $ymm16 = VMAXPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2665 ; CHECK: $ymm16 = VMINCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2666 $ymm16 = VMINCPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2667 ; CHECK: $ymm16 = VMINCPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2668 $ymm16 = VMINCPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2669 ; CHECK: $ymm16 = VMINCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2670 $ymm16 = VMINCPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2671 ; CHECK: $ymm16 = VMINCPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2672 $ymm16 = VMINCPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2673 ; CHECK: $ymm16 = VMINPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2674 $ymm16 = VMINPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2675 ; CHECK: $ymm16 = VMINPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2676 $ymm16 = VMINPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2677 ; CHECK: $ymm16 = VMINPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2678 $ymm16 = VMINPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2679 ; CHECK: $ymm16 = VMINPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2680 $ymm16 = VMINPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2681 ; CHECK: $ymm16 = VXORPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2682 $ymm16 = VXORPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2683 ; CHECK: $ymm16 = VXORPDZ256rr $ymm16, $ymm1
2684 $ymm16 = VXORPDZ256rr $ymm16, $ymm1
2685 ; CHECK: $ymm16 = VXORPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2686 $ymm16 = VXORPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2687 ; CHECK: $ymm16 = VXORPSZ256rr $ymm16, $ymm1
2688 $ymm16 = VXORPSZ256rr $ymm16, $ymm1
2689 ; CHECK: $ymm16 = VPACKSSDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2690 $ymm16 = VPACKSSDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2691 ; CHECK: $ymm16 = VPACKSSDWZ256rr $ymm16, $ymm1
2692 $ymm16 = VPACKSSDWZ256rr $ymm16, $ymm1
2693 ; CHECK: $ymm16 = VPACKSSWBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2694 $ymm16 = VPACKSSWBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2695 ; CHECK: $ymm16 = VPACKSSWBZ256rr $ymm16, $ymm1
2696 $ymm16 = VPACKSSWBZ256rr $ymm16, $ymm1
2697 ; CHECK: $ymm16 = VPACKUSDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2698 $ymm16 = VPACKUSDWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2699 ; CHECK: $ymm16 = VPACKUSDWZ256rr $ymm16, $ymm1
2700 $ymm16 = VPACKUSDWZ256rr $ymm16, $ymm1
2701 ; CHECK: $ymm16 = VPACKUSWBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2702 $ymm16 = VPACKUSWBZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2703 ; CHECK: $ymm16 = VPACKUSWBZ256rr $ymm16, $ymm1
2704 $ymm16 = VPACKUSWBZ256rr $ymm16, $ymm1
2705 ; CHECK: $ymm16 = VUNPCKHPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2706 $ymm16 = VUNPCKHPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2707 ; CHECK: $ymm16 = VUNPCKHPDZ256rr $ymm16, $ymm1
2708 $ymm16 = VUNPCKHPDZ256rr $ymm16, $ymm1
2709 ; CHECK: $ymm16 = VUNPCKHPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2710 $ymm16 = VUNPCKHPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2711 ; CHECK: $ymm16 = VUNPCKHPSZ256rr $ymm16, $ymm1
2712 $ymm16 = VUNPCKHPSZ256rr $ymm16, $ymm1
2713 ; CHECK: $ymm16 = VUNPCKLPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2714 $ymm16 = VUNPCKLPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2715 ; CHECK: $ymm16 = VUNPCKLPDZ256rr $ymm16, $ymm1
2716 $ymm16 = VUNPCKLPDZ256rr $ymm16, $ymm1
2717 ; CHECK: $ymm16 = VUNPCKLPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2718 $ymm16 = VUNPCKLPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2719 ; CHECK: $ymm16 = VUNPCKLPSZ256rr $ymm16, $ymm1
2720 $ymm16 = VUNPCKLPSZ256rr $ymm16, $ymm1
2721 ; CHECK: $ymm16 = VSUBPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2722 $ymm16 = VSUBPDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2723 ; CHECK: $ymm16 = VSUBPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2724 $ymm16 = VSUBPDZ256rr $ymm16, $ymm1, implicit $mxcsr
2725 ; CHECK: $ymm16 = VSUBPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2726 $ymm16 = VSUBPSZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
2727 ; CHECK: $ymm16 = VSUBPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2728 $ymm16 = VSUBPSZ256rr $ymm16, $ymm1, implicit $mxcsr
2729 ; CHECK: $ymm16 = VPUNPCKHBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2730 $ymm16 = VPUNPCKHBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2731 ; CHECK: $ymm16 = VPUNPCKHBWZ256rr $ymm16, $ymm1
2732 $ymm16 = VPUNPCKHBWZ256rr $ymm16, $ymm1
2733 ; CHECK: $ymm16 = VPUNPCKHDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2734 $ymm16 = VPUNPCKHDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2735 ; CHECK: $ymm16 = VPUNPCKHDQZ256rr $ymm16, $ymm1
2736 $ymm16 = VPUNPCKHDQZ256rr $ymm16, $ymm1
2737 ; CHECK: $ymm16 = VPUNPCKHQDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2738 $ymm16 = VPUNPCKHQDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2739 ; CHECK: $ymm16 = VPUNPCKHQDQZ256rr $ymm16, $ymm1
2740 $ymm16 = VPUNPCKHQDQZ256rr $ymm16, $ymm1
2741 ; CHECK: $ymm16 = VPUNPCKHWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2742 $ymm16 = VPUNPCKHWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2743 ; CHECK: $ymm16 = VPUNPCKHWDZ256rr $ymm16, $ymm1
2744 $ymm16 = VPUNPCKHWDZ256rr $ymm16, $ymm1
2745 ; CHECK: $ymm16 = VPUNPCKLBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2746 $ymm16 = VPUNPCKLBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2747 ; CHECK: $ymm16 = VPUNPCKLBWZ256rr $ymm16, $ymm1
2748 $ymm16 = VPUNPCKLBWZ256rr $ymm16, $ymm1
2749 ; CHECK: $ymm16 = VPUNPCKLDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2750 $ymm16 = VPUNPCKLDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2751 ; CHECK: $ymm16 = VPUNPCKLDQZ256rr $ymm16, $ymm1
2752 $ymm16 = VPUNPCKLDQZ256rr $ymm16, $ymm1
2753 ; CHECK: $ymm16 = VPUNPCKLQDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2754 $ymm16 = VPUNPCKLQDQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2755 ; CHECK: $ymm16 = VPUNPCKLQDQZ256rr $ymm16, $ymm1
2756 $ymm16 = VPUNPCKLQDQZ256rr $ymm16, $ymm1
2757 ; CHECK: $ymm16 = VPUNPCKLWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2758 $ymm16 = VPUNPCKLWDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2759 ; CHECK: $ymm16 = VPUNPCKLWDZ256rr $ymm16, $ymm1
2760 $ymm16 = VPUNPCKLWDZ256rr $ymm16, $ymm1
2761 ; CHECK: $ymm16 = VFMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2762 $ymm16 = VFMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2763 ; CHECK: $ymm16 = VFMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2764 $ymm16 = VFMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2765 ; CHECK: $ymm16 = VFMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2766 $ymm16 = VFMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2767 ; CHECK: $ymm16 = VFMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2768 $ymm16 = VFMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2769 ; CHECK: $ymm16 = VFMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2770 $ymm16 = VFMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2771 ; CHECK: $ymm16 = VFMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2772 $ymm16 = VFMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2773 ; CHECK: $ymm16 = VFMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2774 $ymm16 = VFMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2775 ; CHECK: $ymm16 = VFMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2776 $ymm16 = VFMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2777 ; CHECK: $ymm16 = VFMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2778 $ymm16 = VFMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2779 ; CHECK: $ymm16 = VFMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2780 $ymm16 = VFMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2781 ; CHECK: $ymm16 = VFMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2782 $ymm16 = VFMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2783 ; CHECK: $ymm16 = VFMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2784 $ymm16 = VFMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2785 ; CHECK: $ymm16 = VFMADDSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2786 $ymm16 = VFMADDSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2787 ; CHECK: $ymm16 = VFMADDSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2788 $ymm16 = VFMADDSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2789 ; CHECK: $ymm16 = VFMADDSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2790 $ymm16 = VFMADDSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2791 ; CHECK: $ymm16 = VFMADDSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2792 $ymm16 = VFMADDSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2793 ; CHECK: $ymm16 = VFMADDSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2794 $ymm16 = VFMADDSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2795 ; CHECK: $ymm16 = VFMADDSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2796 $ymm16 = VFMADDSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2797 ; CHECK: $ymm16 = VFMADDSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2798 $ymm16 = VFMADDSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2799 ; CHECK: $ymm16 = VFMADDSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2800 $ymm16 = VFMADDSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2801 ; CHECK: $ymm16 = VFMADDSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2802 $ymm16 = VFMADDSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2803 ; CHECK: $ymm16 = VFMADDSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2804 $ymm16 = VFMADDSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2805 ; CHECK: $ymm16 = VFMADDSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2806 $ymm16 = VFMADDSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2807 ; CHECK: $ymm16 = VFMADDSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2808 $ymm16 = VFMADDSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2809 ; CHECK: $ymm16 = VFMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2810 $ymm16 = VFMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2811 ; CHECK: $ymm16 = VFMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2812 $ymm16 = VFMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2813 ; CHECK: $ymm16 = VFMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2814 $ymm16 = VFMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2815 ; CHECK: $ymm16 = VFMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2816 $ymm16 = VFMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2817 ; CHECK: $ymm16 = VFMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2818 $ymm16 = VFMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2819 ; CHECK: $ymm16 = VFMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2820 $ymm16 = VFMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2821 ; CHECK: $ymm16 = VFMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2822 $ymm16 = VFMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2823 ; CHECK: $ymm16 = VFMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2824 $ymm16 = VFMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2825 ; CHECK: $ymm16 = VFMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2826 $ymm16 = VFMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2827 ; CHECK: $ymm16 = VFMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2828 $ymm16 = VFMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2829 ; CHECK: $ymm16 = VFMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2830 $ymm16 = VFMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2831 ; CHECK: $ymm16 = VFMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2832 $ymm16 = VFMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2833 ; CHECK: $ymm16 = VFMSUBADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2834 $ymm16 = VFMSUBADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2835 ; CHECK: $ymm16 = VFMSUBADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2836 $ymm16 = VFMSUBADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2837 ; CHECK: $ymm16 = VFMSUBADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2838 $ymm16 = VFMSUBADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2839 ; CHECK: $ymm16 = VFMSUBADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2840 $ymm16 = VFMSUBADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2841 ; CHECK: $ymm16 = VFMSUBADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2842 $ymm16 = VFMSUBADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2843 ; CHECK: $ymm16 = VFMSUBADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2844 $ymm16 = VFMSUBADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2845 ; CHECK: $ymm16 = VFMSUBADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2846 $ymm16 = VFMSUBADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2847 ; CHECK: $ymm16 = VFMSUBADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2848 $ymm16 = VFMSUBADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2849 ; CHECK: $ymm16 = VFMSUBADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2850 $ymm16 = VFMSUBADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2851 ; CHECK: $ymm16 = VFMSUBADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2852 $ymm16 = VFMSUBADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2853 ; CHECK: $ymm16 = VFMSUBADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2854 $ymm16 = VFMSUBADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2855 ; CHECK: $ymm16 = VFMSUBADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2856 $ymm16 = VFMSUBADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2857 ; CHECK: $ymm16 = VFNMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2858 $ymm16 = VFNMADD132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2859 ; CHECK: $ymm16 = VFNMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2860 $ymm16 = VFNMADD132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2861 ; CHECK: $ymm16 = VFNMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2862 $ymm16 = VFNMADD132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2863 ; CHECK: $ymm16 = VFNMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2864 $ymm16 = VFNMADD132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2865 ; CHECK: $ymm16 = VFNMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2866 $ymm16 = VFNMADD213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2867 ; CHECK: $ymm16 = VFNMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2868 $ymm16 = VFNMADD213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2869 ; CHECK: $ymm16 = VFNMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2870 $ymm16 = VFNMADD213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2871 ; CHECK: $ymm16 = VFNMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2872 $ymm16 = VFNMADD213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2873 ; CHECK: $ymm16 = VFNMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2874 $ymm16 = VFNMADD231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2875 ; CHECK: $ymm16 = VFNMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2876 $ymm16 = VFNMADD231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2877 ; CHECK: $ymm16 = VFNMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2878 $ymm16 = VFNMADD231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2879 ; CHECK: $ymm16 = VFNMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2880 $ymm16 = VFNMADD231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2881 ; CHECK: $ymm16 = VFNMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2882 $ymm16 = VFNMSUB132PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2883 ; CHECK: $ymm16 = VFNMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2884 $ymm16 = VFNMSUB132PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2885 ; CHECK: $ymm16 = VFNMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2886 $ymm16 = VFNMSUB132PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2887 ; CHECK: $ymm16 = VFNMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2888 $ymm16 = VFNMSUB132PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2889 ; CHECK: $ymm16 = VFNMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2890 $ymm16 = VFNMSUB213PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2891 ; CHECK: $ymm16 = VFNMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2892 $ymm16 = VFNMSUB213PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2893 ; CHECK: $ymm16 = VFNMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2894 $ymm16 = VFNMSUB213PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2895 ; CHECK: $ymm16 = VFNMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2896 $ymm16 = VFNMSUB213PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2897 ; CHECK: $ymm16 = VFNMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2898 $ymm16 = VFNMSUB231PDZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2899 ; CHECK: $ymm16 = VFNMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2900 $ymm16 = VFNMSUB231PDZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2901 ; CHECK: $ymm16 = VFNMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2902 $ymm16 = VFNMSUB231PSZ256m $ymm16, $ymm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
2903 ; CHECK: $ymm16 = VFNMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2904 $ymm16 = VFNMSUB231PSZ256r $ymm16, $ymm1, $ymm2, implicit $mxcsr
2905 ; CHECK: $ymm16 = VPSRADZ256ri $ymm16, 7
2906 $ymm16 = VPSRADZ256ri $ymm16, 7
2907 ; CHECK: $ymm16 = VPSRADZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2908 $ymm16 = VPSRADZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2909 ; CHECK: $ymm16 = VPSRADZ256rr $ymm16, $xmm1
2910 $ymm16 = VPSRADZ256rr $ymm16, $xmm1
2911 ; CHECK: $ymm16 = VPSRAVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2912 $ymm16 = VPSRAVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2913 ; CHECK: $ymm16 = VPSRAVDZ256rr $ymm16, $ymm1
2914 $ymm16 = VPSRAVDZ256rr $ymm16, $ymm1
2915 ; CHECK: $ymm16 = VPSRAWZ256ri $ymm16, 7
2916 $ymm16 = VPSRAWZ256ri $ymm16, 7
2917 ; CHECK: $ymm16 = VPSRAWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2918 $ymm16 = VPSRAWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2919 ; CHECK: $ymm16 = VPSRAWZ256rr $ymm16, $xmm1
2920 $ymm16 = VPSRAWZ256rr $ymm16, $xmm1
2921 ; CHECK: $ymm16 = VPSRLDQZ256ri $ymm16, 7
2922 $ymm16 = VPSRLDQZ256ri $ymm16, 7
2923 ; CHECK: $ymm16 = VPSRLDZ256ri $ymm16, 7
2924 $ymm16 = VPSRLDZ256ri $ymm16, 7
2925 ; CHECK: $ymm16 = VPSRLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2926 $ymm16 = VPSRLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2927 ; CHECK: $ymm16 = VPSRLDZ256rr $ymm16, $xmm1
2928 $ymm16 = VPSRLDZ256rr $ymm16, $xmm1
2929 ; CHECK: $ymm16 = VPSRLQZ256ri $ymm16, 7
2930 $ymm16 = VPSRLQZ256ri $ymm16, 7
2931 ; CHECK: $ymm16 = VPSRLQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2932 $ymm16 = VPSRLQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2933 ; CHECK: $ymm16 = VPSRLQZ256rr $ymm16, $xmm1
2934 $ymm16 = VPSRLQZ256rr $ymm16, $xmm1
2935 ; CHECK: $ymm16 = VPSRLVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2936 $ymm16 = VPSRLVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2937 ; CHECK: $ymm16 = VPSRLVDZ256rr $ymm16, $ymm1
2938 $ymm16 = VPSRLVDZ256rr $ymm16, $ymm1
2939 ; CHECK: $ymm16 = VPSRLVQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2940 $ymm16 = VPSRLVQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2941 ; CHECK: $ymm16 = VPSRLVQZ256rr $ymm16, $ymm1
2942 $ymm16 = VPSRLVQZ256rr $ymm16, $ymm1
2943 ; CHECK: $ymm16 = VPSRLWZ256ri $ymm16, 7
2944 $ymm16 = VPSRLWZ256ri $ymm16, 7
2945 ; CHECK: $ymm16 = VPSRLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2946 $ymm16 = VPSRLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
2947 ; CHECK: $ymm16 = VPSRLWZ256rr $ymm16, $xmm1
2948 $ymm16 = VPSRLWZ256rr $ymm16, $xmm1
2949 ; CHECK: $ymm16 = VPMOVSXBDZ256rm $rip, 1, $noreg, 0, $noreg
2950 $ymm16 = VPMOVSXBDZ256rm $rip, 1, $noreg, 0, $noreg
2951 ; CHECK: $ymm16 = VPMOVSXBDZ256rr $xmm0
2952 $ymm16 = VPMOVSXBDZ256rr $xmm0
2953 ; CHECK: $ymm16 = VPMOVSXBQZ256rm $rip, 1, $noreg, 0, $noreg
2954 $ymm16 = VPMOVSXBQZ256rm $rip, 1, $noreg, 0, $noreg
2955 ; CHECK: $ymm16 = VPMOVSXBQZ256rr $xmm0
2956 $ymm16 = VPMOVSXBQZ256rr $xmm0
2957 ; CHECK: $ymm16 = VPMOVSXBWZ256rm $rip, 1, $noreg, 0, $noreg
2958 $ymm16 = VPMOVSXBWZ256rm $rip, 1, $noreg, 0, $noreg
2959 ; CHECK: $ymm16 = VPMOVSXBWZ256rr $xmm0
2960 $ymm16 = VPMOVSXBWZ256rr $xmm0
2961 ; CHECK: $ymm16 = VPMOVSXDQZ256rm $rip, 1, $noreg, 0, $noreg
2962 $ymm16 = VPMOVSXDQZ256rm $rip, 1, $noreg, 0, $noreg
2963 ; CHECK: $ymm16 = VPMOVSXDQZ256rr $xmm0
2964 $ymm16 = VPMOVSXDQZ256rr $xmm0
2965 ; CHECK: $ymm16 = VPMOVSXWDZ256rm $rip, 1, $noreg, 0, $noreg
2966 $ymm16 = VPMOVSXWDZ256rm $rip, 1, $noreg, 0, $noreg
2967 ; CHECK: $ymm16 = VPMOVSXWDZ256rr $xmm0
2968 $ymm16 = VPMOVSXWDZ256rr $xmm0
2969 ; CHECK: $ymm16 = VPMOVSXWQZ256rm $rip, 1, $noreg, 0, $noreg
2970 $ymm16 = VPMOVSXWQZ256rm $rip, 1, $noreg, 0, $noreg
2971 ; CHECK: $ymm16 = VPMOVSXWQZ256rr $xmm0
2972 $ymm16 = VPMOVSXWQZ256rr $xmm0
2973 ; CHECK: $ymm16 = VPMOVZXBDZ256rm $rip, 1, $noreg, 0, $noreg
2974 $ymm16 = VPMOVZXBDZ256rm $rip, 1, $noreg, 0, $noreg
2975 ; CHECK: $ymm16 = VPMOVZXBDZ256rr $xmm0
2976 $ymm16 = VPMOVZXBDZ256rr $xmm0
2977 ; CHECK: $ymm16 = VPMOVZXBQZ256rm $rip, 1, $noreg, 0, $noreg
2978 $ymm16 = VPMOVZXBQZ256rm $rip, 1, $noreg, 0, $noreg
2979 ; CHECK: $ymm16 = VPMOVZXBQZ256rr $xmm0
2980 $ymm16 = VPMOVZXBQZ256rr $xmm0
2981 ; CHECK: $ymm16 = VPMOVZXBWZ256rm $rip, 1, $noreg, 0, $noreg
2982 $ymm16 = VPMOVZXBWZ256rm $rip, 1, $noreg, 0, $noreg
2983 ; CHECK: $ymm16 = VPMOVZXBWZ256rr $xmm0
2984 $ymm16 = VPMOVZXBWZ256rr $xmm0
2985 ; CHECK: $ymm16 = VPMOVZXDQZ256rm $rip, 1, $noreg, 0, $noreg
2986 $ymm16 = VPMOVZXDQZ256rm $rip, 1, $noreg, 0, $noreg
2987 ; CHECK: $ymm16 = VPMOVZXDQZ256rr $xmm0
2988 $ymm16 = VPMOVZXDQZ256rr $xmm0
2989 ; CHECK: $ymm16 = VPMOVZXWDZ256rm $rip, 1, $noreg, 0, $noreg
2990 $ymm16 = VPMOVZXWDZ256rm $rip, 1, $noreg, 0, $noreg
2991 ; CHECK: $ymm16 = VPMOVZXWDZ256rr $xmm0
2992 $ymm16 = VPMOVZXWDZ256rr $xmm0
2993 ; CHECK: $ymm16 = VPMOVZXWQZ256rm $rip, 1, $noreg, 0, $noreg
2994 $ymm16 = VPMOVZXWQZ256rm $rip, 1, $noreg, 0, $noreg
2995 ; CHECK: $ymm16 = VPMOVZXWQZ256rr $xmm0
2996 $ymm16 = VPMOVZXWQZ256rr $xmm0
2997 ; CHECK: $ymm16 = VBROADCASTF32X2Z256rm $rip, 1, $noreg, 0, $noreg
2998 $ymm16 = VBROADCASTF32X2Z256rm $rip, 1, $noreg, 0, $noreg
2999 ; CHECK: $ymm16 = VBROADCASTF32X2Z256rr $xmm16
3000 $ymm16 = VBROADCASTF32X2Z256rr $xmm16
3001 ; CHECK: $ymm16 = VBROADCASTF32X4Z256rm $rip, 1, $noreg, 0, $noreg
3002 $ymm16 = VBROADCASTF32X4Z256rm $rip, 1, $noreg, 0, $noreg
3003 ; CHECK: $ymm16 = VBROADCASTSDZ256rm $rip, 1, $noreg, 0, $noreg
3004 $ymm16 = VBROADCASTSDZ256rm $rip, 1, $noreg, 0, $noreg
3005 ; CHECK: $ymm16 = VBROADCASTSDZ256rr $xmm0
3006 $ymm16 = VBROADCASTSDZ256rr $xmm0
3007 ; CHECK: $ymm16 = VBROADCASTSSZ256rm $rip, 1, $noreg, 0, $noreg
3008 $ymm16 = VBROADCASTSSZ256rm $rip, 1, $noreg, 0, $noreg
3009 ; CHECK: $ymm16 = VBROADCASTSSZ256rr $xmm0
3010 $ymm16 = VBROADCASTSSZ256rr $xmm0
3011 ; CHECK: $ymm16 = VPBROADCASTBZ256rm $rip, 1, $noreg, 0, $noreg
3012 $ymm16 = VPBROADCASTBZ256rm $rip, 1, $noreg, 0, $noreg
3013 ; CHECK: $ymm16 = VPBROADCASTBZ256rr $xmm0
3014 $ymm16 = VPBROADCASTBZ256rr $xmm0
3015 ; CHECK: $ymm16 = VPBROADCASTDZ256rm $rip, 1, $noreg, 0, $noreg
3016 $ymm16 = VPBROADCASTDZ256rm $rip, 1, $noreg, 0, $noreg
3017 ; CHECK: $ymm16 = VPBROADCASTDZ256rr $xmm0
3018 $ymm16 = VPBROADCASTDZ256rr $xmm0
3019 ; CHECK: $ymm16 = VPBROADCASTWZ256rm $rip, 1, $noreg, 0, $noreg
3020 $ymm16 = VPBROADCASTWZ256rm $rip, 1, $noreg, 0, $noreg
3021 ; CHECK: $ymm16 = VPBROADCASTWZ256rr $xmm0
3022 $ymm16 = VPBROADCASTWZ256rr $xmm0
3023 ; CHECK: $ymm16 = VBROADCASTI32X4Z256rm $rip, 1, $noreg, 0, $noreg
3024 $ymm16 = VBROADCASTI32X4Z256rm $rip, 1, $noreg, 0, $noreg
3025 ; CHECK: $ymm16 = VBROADCASTI32X2Z256rm $rip, 1, $noreg, 0, $noreg
3026 $ymm16 = VBROADCASTI32X2Z256rm $rip, 1, $noreg, 0, $noreg
3027 ; CHECK: $ymm16 = VBROADCASTI32X2Z256rr $xmm16
3028 $ymm16 = VBROADCASTI32X2Z256rr $xmm16
3029 ; CHECK: $ymm16 = VPBROADCASTQZ256rm $rip, 1, $noreg, 0, $noreg
3030 $ymm16 = VPBROADCASTQZ256rm $rip, 1, $noreg, 0, $noreg
3031 ; CHECK: $ymm16 = VPBROADCASTQZ256rr $xmm0
3032 $ymm16 = VPBROADCASTQZ256rr $xmm0
3033 ; CHECK: $ymm16 = VPABSBZ256rm $rip, 1, $noreg, 0, $noreg
3034 $ymm16 = VPABSBZ256rm $rip, 1, $noreg, 0, $noreg
3035 ; CHECK: $ymm16 = VPABSBZ256rr $ymm16
3036 $ymm16 = VPABSBZ256rr $ymm16
3037 ; CHECK: $ymm16 = VPABSDZ256rm $rip, 1, $noreg, 0, $noreg
3038 $ymm16 = VPABSDZ256rm $rip, 1, $noreg, 0, $noreg
3039 ; CHECK: $ymm16 = VPABSDZ256rr $ymm16
3040 $ymm16 = VPABSDZ256rr $ymm16
3041 ; CHECK: $ymm16 = VPABSWZ256rm $rip, 1, $noreg, 0, $noreg
3042 $ymm16 = VPABSWZ256rm $rip, 1, $noreg, 0, $noreg
3043 ; CHECK: $ymm16 = VPABSWZ256rr $ymm16
3044 $ymm16 = VPABSWZ256rr $ymm16
3045 ; CHECK: $ymm16 = VPSADBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3046 $ymm16 = VPSADBWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3047 ; CHECK: $ymm16 = VPSADBWZ256rr $ymm16, $ymm1
3048 $ymm16 = VPSADBWZ256rr $ymm16, $ymm1
3049 ; CHECK: $ymm16 = VPERMDZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg
3050 $ymm16 = VPERMDZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg
3051 ; CHECK: $ymm16 = VPERMDZ256rr $ymm1, $ymm16
3052 $ymm16 = VPERMDZ256rr $ymm1, $ymm16
3053 ; CHECK: $ymm16 = VPERMILPDZ256mi $rdi, 1, $noreg, 0, $noreg, 7
3054 $ymm16 = VPERMILPDZ256mi $rdi, 1, $noreg, 0, $noreg, 7
3055 ; CHECK: $ymm16 = VPERMILPDZ256ri $ymm16, 7
3056 $ymm16 = VPERMILPDZ256ri $ymm16, 7
3057 ; CHECK: $ymm16 = VPERMILPDZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg
3058 $ymm16 = VPERMILPDZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg
3059 ; CHECK: $ymm16 = VPERMILPDZ256rr $ymm1, $ymm16
3060 $ymm16 = VPERMILPDZ256rr $ymm1, $ymm16
3061 ; CHECK: $ymm16 = VPERMILPSZ256mi $rdi, 1, $noreg, 0, $noreg, 7
3062 $ymm16 = VPERMILPSZ256mi $rdi, 1, $noreg, 0, $noreg, 7
3063 ; CHECK: $ymm16 = VPERMILPSZ256ri $ymm16, 7
3064 $ymm16 = VPERMILPSZ256ri $ymm16, 7
3065 ; CHECK: $ymm16 = VPERMILPSZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg
3066 $ymm16 = VPERMILPSZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg
3067 ; CHECK: $ymm16 = VPERMILPSZ256rr $ymm1, $ymm16
3068 $ymm16 = VPERMILPSZ256rr $ymm1, $ymm16
3069 ; CHECK: $ymm16 = VPERMPDZ256mi $rdi, 1, $noreg, 0, $noreg, 7
3070 $ymm16 = VPERMPDZ256mi $rdi, 1, $noreg, 0, $noreg, 7
3071 ; CHECK: $ymm16 = VPERMPDZ256ri $ymm16, 7
3072 $ymm16 = VPERMPDZ256ri $ymm16, 7
3073 ; CHECK: $ymm16 = VPERMPSZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg
3074 $ymm16 = VPERMPSZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg
3075 ; CHECK: $ymm16 = VPERMPSZ256rr $ymm1, $ymm16
3076 $ymm16 = VPERMPSZ256rr $ymm1, $ymm16
3077 ; CHECK: $ymm16 = VPERMQZ256mi $rdi, 1, $noreg, 0, $noreg, 7
3078 $ymm16 = VPERMQZ256mi $rdi, 1, $noreg, 0, $noreg, 7
3079 ; CHECK: $ymm16 = VPERMQZ256ri $ymm16, 7
3080 $ymm16 = VPERMQZ256ri $ymm16, 7
3081 ; CHECK: $ymm16 = VPSLLDQZ256ri $ymm16, 14
3082 $ymm16 = VPSLLDQZ256ri $ymm16, 14
3083 ; CHECK: $ymm16 = VPSLLDZ256ri $ymm16, 7
3084 $ymm16 = VPSLLDZ256ri $ymm16, 7
3085 ; CHECK: $ymm16 = VPSLLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3086 $ymm16 = VPSLLDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3087 ; CHECK: $ymm16 = VPSLLDZ256rr $ymm16, $xmm16
3088 $ymm16 = VPSLLDZ256rr $ymm16, $xmm16
3089 ; CHECK: $ymm16 = VPSLLQZ256ri $ymm16, 7
3090 $ymm16 = VPSLLQZ256ri $ymm16, 7
3091 ; CHECK: $ymm16 = VPSLLQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3092 $ymm16 = VPSLLQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3093 ; CHECK: $ymm16 = VPSLLQZ256rr $ymm16, $xmm16
3094 $ymm16 = VPSLLQZ256rr $ymm16, $xmm16
3095 ; CHECK: $ymm16 = VPSLLVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3096 $ymm16 = VPSLLVDZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3097 ; CHECK: $ymm16 = VPSLLVDZ256rr $ymm16, $ymm16
3098 $ymm16 = VPSLLVDZ256rr $ymm16, $ymm16
3099 ; CHECK: $ymm16 = VPSLLVQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3100 $ymm16 = VPSLLVQZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3101 ; CHECK: $ymm16 = VPSLLVQZ256rr $ymm16, $ymm16
3102 $ymm16 = VPSLLVQZ256rr $ymm16, $ymm16
3103 ; CHECK: $ymm16 = VPSLLWZ256ri $ymm16, 7
3104 $ymm16 = VPSLLWZ256ri $ymm16, 7
3105 ; CHECK: $ymm16 = VPSLLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3106 $ymm16 = VPSLLWZ256rm $ymm16, $rip, 1, $noreg, 0, $noreg
3107 ; CHECK: $ymm16 = VPSLLWZ256rr $ymm16, $xmm16
3108 $ymm16 = VPSLLWZ256rr $ymm16, $xmm16
3109 ; CHECK: $ymm16 = VCVTDQ2PDZ256rm $rdi, 1, $noreg, 0, $noreg
3110 $ymm16 = VCVTDQ2PDZ256rm $rdi, 1, $noreg, 0, $noreg
3111 ; CHECK: $ymm16 = VCVTDQ2PDZ256rr $xmm0
3112 $ymm16 = VCVTDQ2PDZ256rr $xmm0, implicit $mxcsr
3113 ; CHECK: $ymm16 = VCVTDQ2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3114 $ymm16 = VCVTDQ2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3115 ; CHECK: $ymm16 = VCVTDQ2PSZ256rr $ymm16, implicit $mxcsr
3116 $ymm16 = VCVTDQ2PSZ256rr $ymm16, implicit $mxcsr
3117 ; CHECK: $xmm16 = VCVTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3118 $xmm16 = VCVTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3119 ; CHECK: $xmm16 = VCVTPD2DQZ256rr $ymm16, implicit $mxcsr
3120 $xmm16 = VCVTPD2DQZ256rr $ymm16, implicit $mxcsr
3121 ; CHECK: $xmm16 = VCVTPD2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3122 $xmm16 = VCVTPD2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3123 ; CHECK: $xmm16 = VCVTPD2PSZ256rr $ymm16, implicit $mxcsr
3124 $xmm16 = VCVTPD2PSZ256rr $ymm16, implicit $mxcsr
3125 ; CHECK: $ymm16 = VCVTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3126 $ymm16 = VCVTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3127 ; CHECK: $ymm16 = VCVTPS2DQZ256rr $ymm16, implicit $mxcsr
3128 $ymm16 = VCVTPS2DQZ256rr $ymm16, implicit $mxcsr
3129 ; CHECK: $ymm16 = VCVTPS2PDZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3130 $ymm16 = VCVTPS2PDZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3131 ; CHECK: $ymm16 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
3132 $ymm16 = VCVTPS2PDZ256rr $xmm0, implicit $mxcsr
3133 ; CHECK: VCVTPS2PHZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16, 0, implicit $mxcsr
3134 VCVTPS2PHZ256mr $rdi, 1, $noreg, 0, $noreg, $ymm16, 0, implicit $mxcsr
3135 ; CHECK: $xmm0 = VCVTPS2PHZ256rr $ymm16, 0, implicit $mxcsr
3136 $xmm0 = VCVTPS2PHZ256rr $ymm16, 0, implicit $mxcsr
3137 ; CHECK: $ymm16 = VCVTPH2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3138 $ymm16 = VCVTPH2PSZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3139 ; CHECK: $ymm16 = VCVTPH2PSZ256rr $xmm16, implicit $mxcsr
3140 $ymm16 = VCVTPH2PSZ256rr $xmm16, implicit $mxcsr
3141 ; CHECK: $xmm16 = VCVTTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3142 $xmm16 = VCVTTPD2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3143 ; CHECK: $xmm16 = VCVTTPD2DQZ256rr $ymm16, implicit $mxcsr
3144 $xmm16 = VCVTTPD2DQZ256rr $ymm16, implicit $mxcsr
3145 ; CHECK: $ymm16 = VCVTTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3146 $ymm16 = VCVTTPS2DQZ256rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3147 ; CHECK: $ymm16 = VCVTTPS2DQZ256rr $ymm16, implicit $mxcsr
3148 $ymm16 = VCVTTPS2DQZ256rr $ymm16, implicit $mxcsr
3149 ; CHECK: $ymm16 = VSQRTPDZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3150 $ymm16 = VSQRTPDZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3151 ; CHECK: $ymm16 = VSQRTPDZ256r $ymm16, implicit $mxcsr
3152 $ymm16 = VSQRTPDZ256r $ymm16, implicit $mxcsr
3153 ; CHECK: $ymm16 = VSQRTPSZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3154 $ymm16 = VSQRTPSZ256m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3155 ; CHECK: $ymm16 = VSQRTPSZ256r $ymm16, implicit $mxcsr
3156 $ymm16 = VSQRTPSZ256r $ymm16, implicit $mxcsr
3157 ; CHECK: $ymm16 = VPALIGNRZ256rmi $ymm16, $rdi, 1, $noreg, 0, $noreg, 1
3158 $ymm16 = VPALIGNRZ256rmi $ymm16, $rdi, 1, $noreg, 0, $noreg, 1
3159 ; CHECK: $ymm16 = VPALIGNRZ256rri $ymm16, $ymm1, 1
3160 $ymm16 = VPALIGNRZ256rri $ymm16, $ymm1, 1
3161 ; CHECK: $ymm16 = VMOVUPSZ256rm $rdi, 1, $noreg, 0, $noreg
3162 $ymm16 = VMOVUPSZ256rm $rdi, 1, $noreg, 0, $noreg
3163 ; CHECK: $ymm16 = VMOVUPSZ256rr $ymm16
3164 $ymm16 = VMOVUPSZ256rr $ymm16
3165 ; CHECK: $ymm16 = VPSHUFBZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg
3166 $ymm16 = VPSHUFBZ256rm $ymm16, $rdi, 1, $noreg, 0, $noreg
3167 ; CHECK: $ymm16 = VPSHUFBZ256rr $ymm16, $ymm1
3168 $ymm16 = VPSHUFBZ256rr $ymm16, $ymm1
3169 ; CHECK: $ymm16 = VPSHUFDZ256mi $rdi, 1, $noreg, 0, $noreg, -24
3170 $ymm16 = VPSHUFDZ256mi $rdi, 1, $noreg, 0, $noreg, -24
3171 ; CHECK: $ymm16 = VPSHUFDZ256ri $ymm16, -24
3172 $ymm16 = VPSHUFDZ256ri $ymm16, -24
3173 ; CHECK: $ymm16 = VPSHUFHWZ256mi $rdi, 1, $noreg, 0, $noreg, -24
3174 $ymm16 = VPSHUFHWZ256mi $rdi, 1, $noreg, 0, $noreg, -24
3175 ; CHECK: $ymm16 = VPSHUFHWZ256ri $ymm16, -24
3176 $ymm16 = VPSHUFHWZ256ri $ymm16, -24
3177 ; CHECK: $ymm16 = VPSHUFLWZ256mi $rdi, 1, $noreg, 0, $noreg, -24
3178 $ymm16 = VPSHUFLWZ256mi $rdi, 1, $noreg, 0, $noreg, -24
3179 ; CHECK: $ymm16 = VPSHUFLWZ256ri $ymm16, -24
3180 $ymm16 = VPSHUFLWZ256ri $ymm16, -24
3181 ; CHECK: $ymm16 = VSHUFPDZ256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, -24
3182 $ymm16 = VSHUFPDZ256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, -24
3183 ; CHECK: $ymm16 = VSHUFPDZ256rri $ymm16, $ymm1, -24
3184 $ymm16 = VSHUFPDZ256rri $ymm16, $ymm1, -24
3185 ; CHECK: $ymm16 = VSHUFPSZ256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, -24
3186 $ymm16 = VSHUFPSZ256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, -24
3187 ; CHECK: $ymm16 = VSHUFPSZ256rri $ymm16, $ymm1, -24
3188 $ymm16 = VSHUFPSZ256rri $ymm16, $ymm1, -24
3189 ; CHECK: $ymm16 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
3190 $ymm16 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
3191 ; CHECK: $ymm16 = VRNDSCALEPDZ256rri $ymm16, 15, implicit $mxcsr
3192 $ymm16 = VRNDSCALEPDZ256rri $ymm16, 15, implicit $mxcsr
3193 ; CHECK: $ymm16 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
3194 $ymm16 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
3195 ; CHECK: $ymm16 = VRNDSCALEPSZ256rri $ymm16, 15, implicit $mxcsr
3196 $ymm16 = VRNDSCALEPSZ256rri $ymm16, 15, implicit $mxcsr
3197 ; CHECK: $ymm0 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
3198 $ymm0 = VRNDSCALEPDZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
3199 ; CHECK: $ymm0 = VRNDSCALEPDZ256rri $ymm0, 31, implicit $mxcsr
3200 $ymm0 = VRNDSCALEPDZ256rri $ymm0, 31, implicit $mxcsr
3201 ; CHECK: $ymm0 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
3202 $ymm0 = VRNDSCALEPSZ256rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
3203 ; CHECK: $ymm0 = VRNDSCALEPSZ256rri $ymm0, 31, implicit $mxcsr
3204 $ymm0 = VRNDSCALEPSZ256rri $ymm0, 31, implicit $mxcsr
3205 ; CHECK: $ymm16 = VSHUFF32X4Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
3206 $ymm16 = VSHUFF32X4Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
3207 ; CHECK: $ymm16 = VSHUFF32X4Z256rri $ymm16, $ymm1, 228
3208 $ymm16 = VSHUFF32X4Z256rri $ymm16, $ymm1, 228
3209 ; CHECK: $ymm16 = VSHUFF64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
3210 $ymm16 = VSHUFF64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
3211 ; CHECK: $ymm16 = VSHUFF64X2Z256rri $ymm16, $ymm1, 228
3212 $ymm16 = VSHUFF64X2Z256rri $ymm16, $ymm1, 228
3213 ; CHECK: $ymm16 = VSHUFI32X4Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
3214 $ymm16 = VSHUFI32X4Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
3215 ; CHECK: $ymm16 = VSHUFI32X4Z256rri $ymm16, $ymm1, 228
3216 $ymm16 = VSHUFI32X4Z256rri $ymm16, $ymm1, 228
3217 ; CHECK: $ymm16 = VSHUFI64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
3218 $ymm16 = VSHUFI64X2Z256rmi $ymm16, $rip, 1, $noreg, 0, $noreg, 228
3219 ; CHECK: $ymm16 = VSHUFI64X2Z256rri $ymm16, $ymm1, 228
3220 $ymm16 = VSHUFI64X2Z256rri $ymm16, $ymm1, 228
3222 RET64
3223 ...
3224 ---
3225 # CHECK-LABEL: name: evex_z128_to_evex_test
3226 # CHECK: bb.0:
3228 name: evex_z128_to_evex_test
3229 body: |
3230 bb.0:
3231 ; CHECK: VMOVAPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3232 VMOVAPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3233 ; CHECK: $xmm16 = VMOVAPDZ128rm $rip, 1, $noreg, 0, $noreg
3234 $xmm16 = VMOVAPDZ128rm $rip, 1, $noreg, 0, $noreg
3235 ; CHECK: $xmm16 = VMOVAPDZ128rr $xmm16
3236 $xmm16 = VMOVAPDZ128rr $xmm16
3237 ; CHECK: VMOVAPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3238 VMOVAPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3239 ; CHECK: $xmm16 = VMOVAPSZ128rm $rip, 1, $noreg, 0, $noreg
3240 $xmm16 = VMOVAPSZ128rm $rip, 1, $noreg, 0, $noreg
3241 ; CHECK: $xmm16 = VMOVAPSZ128rr $xmm16
3242 $xmm16 = VMOVAPSZ128rr $xmm16
3243 ; CHECK: VMOVDQA32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3244 VMOVDQA32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3245 ; CHECK: $xmm16 = VMOVDQA32Z128rm $rip, 1, $noreg, 0, $noreg
3246 $xmm16 = VMOVDQA32Z128rm $rip, 1, $noreg, 0, $noreg
3247 ; CHECK: $xmm16 = VMOVDQA32Z128rr $xmm16
3248 $xmm16 = VMOVDQA32Z128rr $xmm16
3249 ; CHECK: VMOVDQA64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3250 VMOVDQA64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3251 ; CHECK: $xmm16 = VMOVDQA64Z128rm $rip, 1, $noreg, 0, $noreg
3252 $xmm16 = VMOVDQA64Z128rm $rip, 1, $noreg, 0, $noreg
3253 ; CHECK: $xmm16 = VMOVDQA64Z128rr $xmm16
3254 $xmm16 = VMOVDQA64Z128rr $xmm16
3255 ; CHECK: VMOVDQU16Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3256 VMOVDQU16Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3257 ; CHECK: $xmm16 = VMOVDQU16Z128rm $rip, 1, $noreg, 0, $noreg
3258 $xmm16 = VMOVDQU16Z128rm $rip, 1, $noreg, 0, $noreg
3259 ; CHECK: $xmm16 = VMOVDQU16Z128rr $xmm16
3260 $xmm16 = VMOVDQU16Z128rr $xmm16
3261 ; CHECK: VMOVDQU32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3262 VMOVDQU32Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3263 ; CHECK: $xmm16 = VMOVDQU32Z128rm $rip, 1, $noreg, 0, $noreg
3264 $xmm16 = VMOVDQU32Z128rm $rip, 1, $noreg, 0, $noreg
3265 ; CHECK: $xmm16 = VMOVDQU32Z128rr $xmm16
3266 $xmm16 = VMOVDQU32Z128rr $xmm16
3267 ; CHECK: VMOVDQU64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3268 VMOVDQU64Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3269 ; CHECK: $xmm16 = VMOVDQU64Z128rm $rip, 1, $noreg, 0, $noreg
3270 $xmm16 = VMOVDQU64Z128rm $rip, 1, $noreg, 0, $noreg
3271 ; CHECK: $xmm16 = VMOVDQU64Z128rr $xmm16
3272 $xmm16 = VMOVDQU64Z128rr $xmm16
3273 ; CHECK: VMOVDQU8Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3274 VMOVDQU8Z128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3275 ; CHECK: $xmm16 = VMOVDQU8Z128rm $rip, 1, $noreg, 0, $noreg
3276 $xmm16 = VMOVDQU8Z128rm $rip, 1, $noreg, 0, $noreg
3277 ; CHECK: $xmm16 = VMOVDQU8Z128rr $xmm16
3278 $xmm16 = VMOVDQU8Z128rr $xmm16
3279 ; CHECK: $xmm16 = VMOVNTDQAZ128rm $rip, 1, $noreg, 0, $noreg
3280 $xmm16 = VMOVNTDQAZ128rm $rip, 1, $noreg, 0, $noreg
3281 ; CHECK: VMOVUPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3282 VMOVUPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3283 ; CHECK: $xmm16 = VMOVUPDZ128rm $rip, 1, $noreg, 0, $noreg
3284 $xmm16 = VMOVUPDZ128rm $rip, 1, $noreg, 0, $noreg
3285 ; CHECK: $xmm16 = VMOVUPDZ128rr $xmm16
3286 $xmm16 = VMOVUPDZ128rr $xmm16
3287 ; CHECK: VMOVUPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3288 VMOVUPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3289 ; CHECK: $xmm16 = VMOVUPSZ128rm $rip, 1, $noreg, 0, $noreg
3290 $xmm16 = VMOVUPSZ128rm $rip, 1, $noreg, 0, $noreg
3291 ; CHECK: $xmm16 = VMOVUPSZ128rr $xmm16
3292 $xmm16 = VMOVUPSZ128rr $xmm16
3293 ; CHECK: VMOVNTDQZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3294 VMOVNTDQZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3295 ; CHECK: VMOVNTPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3296 VMOVNTPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3297 ; CHECK: VMOVNTPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3298 VMOVNTPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3299 ; CHECK: $xmm16 = VPMOVSXBDZ128rm $rip, 1, $noreg, 0, $noreg
3300 $xmm16 = VPMOVSXBDZ128rm $rip, 1, $noreg, 0, $noreg
3301 ; CHECK: $xmm16 = VPMOVSXBDZ128rr $xmm16
3302 $xmm16 = VPMOVSXBDZ128rr $xmm16
3303 ; CHECK: $xmm16 = VPMOVSXBQZ128rm $rip, 1, $noreg, 0, $noreg
3304 $xmm16 = VPMOVSXBQZ128rm $rip, 1, $noreg, 0, $noreg
3305 ; CHECK: $xmm16 = VPMOVSXBQZ128rr $xmm16
3306 $xmm16 = VPMOVSXBQZ128rr $xmm16
3307 ; CHECK: $xmm16 = VPMOVSXBWZ128rm $rip, 1, $noreg, 0, $noreg
3308 $xmm16 = VPMOVSXBWZ128rm $rip, 1, $noreg, 0, $noreg
3309 ; CHECK: $xmm16 = VPMOVSXBWZ128rr $xmm16
3310 $xmm16 = VPMOVSXBWZ128rr $xmm16
3311 ; CHECK: $xmm16 = VPMOVSXDQZ128rm $rip, 1, $noreg, 0, $noreg
3312 $xmm16 = VPMOVSXDQZ128rm $rip, 1, $noreg, 0, $noreg
3313 ; CHECK: $xmm16 = VPMOVSXDQZ128rr $xmm16
3314 $xmm16 = VPMOVSXDQZ128rr $xmm16
3315 ; CHECK: $xmm16 = VPMOVSXWDZ128rm $rip, 1, $noreg, 0, $noreg
3316 $xmm16 = VPMOVSXWDZ128rm $rip, 1, $noreg, 0, $noreg
3317 ; CHECK: $xmm16 = VPMOVSXWDZ128rr $xmm16
3318 $xmm16 = VPMOVSXWDZ128rr $xmm16
3319 ; CHECK: $xmm16 = VPMOVSXWQZ128rm $rip, 1, $noreg, 0, $noreg
3320 $xmm16 = VPMOVSXWQZ128rm $rip, 1, $noreg, 0, $noreg
3321 ; CHECK: $xmm16 = VPMOVSXWQZ128rr $xmm16
3322 $xmm16 = VPMOVSXWQZ128rr $xmm16
3323 ; CHECK: $xmm16 = VPMOVZXBDZ128rm $rip, 1, $noreg, 0, $noreg
3324 $xmm16 = VPMOVZXBDZ128rm $rip, 1, $noreg, 0, $noreg
3325 ; CHECK: $xmm16 = VPMOVZXBDZ128rr $xmm16
3326 $xmm16 = VPMOVZXBDZ128rr $xmm16
3327 ; CHECK: $xmm16 = VPMOVZXBQZ128rm $rip, 1, $noreg, 0, $noreg
3328 $xmm16 = VPMOVZXBQZ128rm $rip, 1, $noreg, 0, $noreg
3329 ; CHECK: $xmm16 = VPMOVZXBQZ128rr $xmm16
3330 $xmm16 = VPMOVZXBQZ128rr $xmm16
3331 ; CHECK: $xmm16 = VPMOVZXBWZ128rm $rip, 1, $noreg, 0, $noreg
3332 $xmm16 = VPMOVZXBWZ128rm $rip, 1, $noreg, 0, $noreg
3333 ; CHECK: $xmm16 = VPMOVZXBWZ128rr $xmm16
3334 $xmm16 = VPMOVZXBWZ128rr $xmm16
3335 ; CHECK: $xmm16 = VPMOVZXDQZ128rm $rip, 1, $noreg, 0, $noreg
3336 $xmm16 = VPMOVZXDQZ128rm $rip, 1, $noreg, 0, $noreg
3337 ; CHECK: $xmm16 = VPMOVZXDQZ128rr $xmm16
3338 $xmm16 = VPMOVZXDQZ128rr $xmm16
3339 ; CHECK: $xmm16 = VPMOVZXWDZ128rm $rip, 1, $noreg, 0, $noreg
3340 $xmm16 = VPMOVZXWDZ128rm $rip, 1, $noreg, 0, $noreg
3341 ; CHECK: $xmm16 = VPMOVZXWDZ128rr $xmm16
3342 $xmm16 = VPMOVZXWDZ128rr $xmm16
3343 ; CHECK: $xmm16 = VPMOVZXWQZ128rm $rip, 1, $noreg, 0, $noreg
3344 $xmm16 = VPMOVZXWQZ128rm $rip, 1, $noreg, 0, $noreg
3345 ; CHECK: $xmm16 = VPMOVZXWQZ128rr $xmm16
3346 $xmm16 = VPMOVZXWQZ128rr $xmm16
3347 ; CHECK: VMOVHPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3348 VMOVHPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3349 ; CHECK: $xmm16 = VMOVHPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3350 $xmm16 = VMOVHPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3351 ; CHECK: VMOVHPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3352 VMOVHPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3353 ; CHECK: $xmm16 = VMOVHPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3354 $xmm16 = VMOVHPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3355 ; CHECK: VMOVLPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3356 VMOVLPDZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3357 ; CHECK: $xmm16 = VMOVLPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3358 $xmm16 = VMOVLPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3359 ; CHECK: VMOVLPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3360 VMOVLPSZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16
3361 ; CHECK: $xmm16 = VMOVLPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3362 $xmm16 = VMOVLPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3363 ; CHECK: $xmm16 = VMAXCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3364 $xmm16 = VMAXCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3365 ; CHECK: $xmm16 = VMAXCPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3366 $xmm16 = VMAXCPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3367 ; CHECK: $xmm16 = VMAXCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3368 $xmm16 = VMAXCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3369 ; CHECK: $xmm16 = VMAXCPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3370 $xmm16 = VMAXCPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3371 ; CHECK: $xmm16 = VMAXPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3372 $xmm16 = VMAXPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3373 ; CHECK: $xmm16 = VMAXPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3374 $xmm16 = VMAXPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3375 ; CHECK: $xmm16 = VMAXPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3376 $xmm16 = VMAXPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3377 ; CHECK: $xmm16 = VMAXPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3378 $xmm16 = VMAXPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3379 ; CHECK: $xmm16 = VMINCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3380 $xmm16 = VMINCPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3381 ; CHECK: $xmm16 = VMINCPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3382 $xmm16 = VMINCPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3383 ; CHECK: $xmm16 = VMINCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3384 $xmm16 = VMINCPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3385 ; CHECK: $xmm16 = VMINCPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3386 $xmm16 = VMINCPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3387 ; CHECK: $xmm16 = VMINPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3388 $xmm16 = VMINPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3389 ; CHECK: $xmm16 = VMINPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3390 $xmm16 = VMINPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3391 ; CHECK: $xmm16 = VMINPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3392 $xmm16 = VMINPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3393 ; CHECK: $xmm16 = VMINPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3394 $xmm16 = VMINPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3395 ; CHECK: $xmm16 = VMULPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3396 $xmm16 = VMULPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3397 ; CHECK: $xmm16 = VMULPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3398 $xmm16 = VMULPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3399 ; CHECK: $xmm16 = VMULPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3400 $xmm16 = VMULPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3401 ; CHECK: $xmm16 = VMULPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3402 $xmm16 = VMULPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3403 ; CHECK: $xmm16 = VORPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3404 $xmm16 = VORPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3405 ; CHECK: $xmm16 = VORPDZ128rr $xmm16, $xmm1
3406 $xmm16 = VORPDZ128rr $xmm16, $xmm1
3407 ; CHECK: $xmm16 = VORPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3408 $xmm16 = VORPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3409 ; CHECK: $xmm16 = VORPSZ128rr $xmm16, $xmm1
3410 $xmm16 = VORPSZ128rr $xmm16, $xmm1
3411 ; CHECK: $xmm16 = VPADDBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3412 $xmm16 = VPADDBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3413 ; CHECK: $xmm16 = VPADDBZ128rr $xmm16, $xmm1
3414 $xmm16 = VPADDBZ128rr $xmm16, $xmm1
3415 ; CHECK: $xmm16 = VPADDDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3416 $xmm16 = VPADDDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3417 ; CHECK: $xmm16 = VPADDDZ128rr $xmm16, $xmm1
3418 $xmm16 = VPADDDZ128rr $xmm16, $xmm1
3419 ; CHECK: $xmm16 = VPADDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3420 $xmm16 = VPADDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3421 ; CHECK: $xmm16 = VPADDQZ128rr $xmm16, $xmm1
3422 $xmm16 = VPADDQZ128rr $xmm16, $xmm1
3423 ; CHECK: $xmm16 = VPADDSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3424 $xmm16 = VPADDSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3425 ; CHECK: $xmm16 = VPADDSBZ128rr $xmm16, $xmm1
3426 $xmm16 = VPADDSBZ128rr $xmm16, $xmm1
3427 ; CHECK: $xmm16 = VPADDSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3428 $xmm16 = VPADDSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3429 ; CHECK: $xmm16 = VPADDSWZ128rr $xmm16, $xmm1
3430 $xmm16 = VPADDSWZ128rr $xmm16, $xmm1
3431 ; CHECK: $xmm16 = VPADDUSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3432 $xmm16 = VPADDUSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3433 ; CHECK: $xmm16 = VPADDUSBZ128rr $xmm16, $xmm1
3434 $xmm16 = VPADDUSBZ128rr $xmm16, $xmm1
3435 ; CHECK: $xmm16 = VPADDUSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3436 $xmm16 = VPADDUSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3437 ; CHECK: $xmm16 = VPADDUSWZ128rr $xmm16, $xmm1
3438 $xmm16 = VPADDUSWZ128rr $xmm16, $xmm1
3439 ; CHECK: $xmm16 = VPADDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3440 $xmm16 = VPADDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3441 ; CHECK: $xmm16 = VPADDWZ128rr $xmm16, $xmm1
3442 $xmm16 = VPADDWZ128rr $xmm16, $xmm1
3443 ; CHECK: $xmm16 = VPANDDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3444 $xmm16 = VPANDDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3445 ; CHECK: $xmm16 = VPANDDZ128rr $xmm16, $xmm1
3446 $xmm16 = VPANDDZ128rr $xmm16, $xmm1
3447 ; CHECK: $xmm16 = VPANDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3448 $xmm16 = VPANDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3449 ; CHECK: $xmm16 = VPANDQZ128rr $xmm16, $xmm1
3450 $xmm16 = VPANDQZ128rr $xmm16, $xmm1
3451 ; CHECK: $xmm16 = VPANDNDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3452 $xmm16 = VPANDNDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3453 ; CHECK: $xmm16 = VPANDNDZ128rr $xmm16, $xmm1
3454 $xmm16 = VPANDNDZ128rr $xmm16, $xmm1
3455 ; CHECK: $xmm16 = VPANDNQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3456 $xmm16 = VPANDNQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3457 ; CHECK: $xmm16 = VPANDNQZ128rr $xmm16, $xmm1
3458 $xmm16 = VPANDNQZ128rr $xmm16, $xmm1
3459 ; CHECK: $xmm16 = VPAVGBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3460 $xmm16 = VPAVGBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3461 ; CHECK: $xmm16 = VPAVGBZ128rr $xmm16, $xmm1
3462 $xmm16 = VPAVGBZ128rr $xmm16, $xmm1
3463 ; CHECK: $xmm16 = VPAVGWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3464 $xmm16 = VPAVGWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3465 ; CHECK: $xmm16 = VPAVGWZ128rr $xmm16, $xmm1
3466 $xmm16 = VPAVGWZ128rr $xmm16, $xmm1
3467 ; CHECK: $xmm16 = VPMAXSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3468 $xmm16 = VPMAXSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3469 ; CHECK: $xmm16 = VPMAXSBZ128rr $xmm16, $xmm1
3470 $xmm16 = VPMAXSBZ128rr $xmm16, $xmm1
3471 ; CHECK: $xmm16 = VPMAXSDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3472 $xmm16 = VPMAXSDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3473 ; CHECK: $xmm16 = VPMAXSDZ128rr $xmm16, $xmm1
3474 $xmm16 = VPMAXSDZ128rr $xmm16, $xmm1
3475 ; CHECK: $xmm16 = VPMAXSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3476 $xmm16 = VPMAXSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3477 ; CHECK: $xmm16 = VPMAXSWZ128rr $xmm16, $xmm1
3478 $xmm16 = VPMAXSWZ128rr $xmm16, $xmm1
3479 ; CHECK: $xmm16 = VPMAXUBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3480 $xmm16 = VPMAXUBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3481 ; CHECK: $xmm16 = VPMAXUBZ128rr $xmm16, $xmm1
3482 $xmm16 = VPMAXUBZ128rr $xmm16, $xmm1
3483 ; CHECK: $xmm16 = VPMAXUDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3484 $xmm16 = VPMAXUDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3485 ; CHECK: $xmm16 = VPMAXUDZ128rr $xmm16, $xmm1
3486 $xmm16 = VPMAXUDZ128rr $xmm16, $xmm1
3487 ; CHECK: $xmm16 = VPMAXUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3488 $xmm16 = VPMAXUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3489 ; CHECK: $xmm16 = VPMAXUWZ128rr $xmm16, $xmm1
3490 $xmm16 = VPMAXUWZ128rr $xmm16, $xmm1
3491 ; CHECK: $xmm16 = VPMINSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3492 $xmm16 = VPMINSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3493 ; CHECK: $xmm16 = VPMINSBZ128rr $xmm16, $xmm1
3494 $xmm16 = VPMINSBZ128rr $xmm16, $xmm1
3495 ; CHECK: $xmm16 = VPMINSDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3496 $xmm16 = VPMINSDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3497 ; CHECK: $xmm16 = VPMINSDZ128rr $xmm16, $xmm1
3498 $xmm16 = VPMINSDZ128rr $xmm16, $xmm1
3499 ; CHECK: $xmm16 = VPMINSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3500 $xmm16 = VPMINSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3501 ; CHECK: $xmm16 = VPMINSWZ128rr $xmm16, $xmm1
3502 $xmm16 = VPMINSWZ128rr $xmm16, $xmm1
3503 ; CHECK: $xmm16 = VPMINUBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3504 $xmm16 = VPMINUBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3505 ; CHECK: $xmm16 = VPMINUBZ128rr $xmm16, $xmm1
3506 $xmm16 = VPMINUBZ128rr $xmm16, $xmm1
3507 ; CHECK: $xmm16 = VPMINUDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3508 $xmm16 = VPMINUDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3509 ; CHECK: $xmm16 = VPMINUDZ128rr $xmm16, $xmm1
3510 $xmm16 = VPMINUDZ128rr $xmm16, $xmm1
3511 ; CHECK: $xmm16 = VPMINUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3512 $xmm16 = VPMINUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3513 ; CHECK: $xmm16 = VPMINUWZ128rr $xmm16, $xmm1
3514 $xmm16 = VPMINUWZ128rr $xmm16, $xmm1
3515 ; CHECK: $xmm16 = VPMULDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3516 $xmm16 = VPMULDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3517 ; CHECK: $xmm16 = VPMULDQZ128rr $xmm16, $xmm1
3518 $xmm16 = VPMULDQZ128rr $xmm16, $xmm1
3519 ; CHECK: $xmm16 = VPMULHRSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3520 $xmm16 = VPMULHRSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3521 ; CHECK: $xmm16 = VPMULHRSWZ128rr $xmm16, $xmm1
3522 $xmm16 = VPMULHRSWZ128rr $xmm16, $xmm1
3523 ; CHECK: $xmm16 = VPMULHUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3524 $xmm16 = VPMULHUWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3525 ; CHECK: $xmm16 = VPMULHUWZ128rr $xmm16, $xmm1
3526 $xmm16 = VPMULHUWZ128rr $xmm16, $xmm1
3527 ; CHECK: $xmm16 = VPMULHWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3528 $xmm16 = VPMULHWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3529 ; CHECK: $xmm16 = VPMULHWZ128rr $xmm16, $xmm1
3530 $xmm16 = VPMULHWZ128rr $xmm16, $xmm1
3531 ; CHECK: $xmm16 = VPMULLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3532 $xmm16 = VPMULLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3533 ; CHECK: $xmm16 = VPMULLDZ128rr $xmm16, $xmm1
3534 $xmm16 = VPMULLDZ128rr $xmm16, $xmm1
3535 ; CHECK: $xmm16 = VPMULLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3536 $xmm16 = VPMULLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3537 ; CHECK: $xmm16 = VPMULLWZ128rr $xmm16, $xmm1
3538 $xmm16 = VPMULLWZ128rr $xmm16, $xmm1
3539 ; CHECK: $xmm16 = VPMULUDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3540 $xmm16 = VPMULUDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3541 ; CHECK: $xmm16 = VPMULUDQZ128rr $xmm16, $xmm1
3542 $xmm16 = VPMULUDQZ128rr $xmm16, $xmm1
3543 ; CHECK: $xmm16 = VPORDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3544 $xmm16 = VPORDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3545 ; CHECK: $xmm16 = VPORDZ128rr $xmm16, $xmm1
3546 $xmm16 = VPORDZ128rr $xmm16, $xmm1
3547 ; CHECK: $xmm16 = VPORQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3548 $xmm16 = VPORQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3549 ; CHECK: $xmm16 = VPORQZ128rr $xmm16, $xmm1
3550 $xmm16 = VPORQZ128rr $xmm16, $xmm1
3551 ; CHECK: $xmm16 = VPSUBBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3552 $xmm16 = VPSUBBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3553 ; CHECK: $xmm16 = VPSUBBZ128rr $xmm16, $xmm1
3554 $xmm16 = VPSUBBZ128rr $xmm16, $xmm1
3555 ; CHECK: $xmm16 = VPSUBDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3556 $xmm16 = VPSUBDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3557 ; CHECK: $xmm16 = VPSUBDZ128rr $xmm16, $xmm1
3558 $xmm16 = VPSUBDZ128rr $xmm16, $xmm1
3559 ; CHECK: $xmm16 = VPSUBQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3560 $xmm16 = VPSUBQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3561 ; CHECK: $xmm16 = VPSUBQZ128rr $xmm16, $xmm1
3562 $xmm16 = VPSUBQZ128rr $xmm16, $xmm1
3563 ; CHECK: $xmm16 = VPSUBSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3564 $xmm16 = VPSUBSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3565 ; CHECK: $xmm16 = VPSUBSBZ128rr $xmm16, $xmm1
3566 $xmm16 = VPSUBSBZ128rr $xmm16, $xmm1
3567 ; CHECK: $xmm16 = VPSUBSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3568 $xmm16 = VPSUBSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3569 ; CHECK: $xmm16 = VPSUBSWZ128rr $xmm16, $xmm1
3570 $xmm16 = VPSUBSWZ128rr $xmm16, $xmm1
3571 ; CHECK: $xmm16 = VPSUBUSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3572 $xmm16 = VPSUBUSBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3573 ; CHECK: $xmm16 = VPSUBUSBZ128rr $xmm16, $xmm1
3574 $xmm16 = VPSUBUSBZ128rr $xmm16, $xmm1
3575 ; CHECK: $xmm16 = VPSUBUSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3576 $xmm16 = VPSUBUSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3577 ; CHECK: $xmm16 = VPSUBUSWZ128rr $xmm16, $xmm1
3578 $xmm16 = VPSUBUSWZ128rr $xmm16, $xmm1
3579 ; CHECK: $xmm16 = VPSUBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3580 $xmm16 = VPSUBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3581 ; CHECK: $xmm16 = VPSUBWZ128rr $xmm16, $xmm1
3582 $xmm16 = VPSUBWZ128rr $xmm16, $xmm1
3583 ; CHECK: $xmm16 = VADDPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3584 $xmm16 = VADDPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3585 ; CHECK: $xmm16 = VADDPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3586 $xmm16 = VADDPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3587 ; CHECK: $xmm16 = VADDPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3588 $xmm16 = VADDPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3589 ; CHECK: $xmm16 = VADDPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3590 $xmm16 = VADDPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3591 ; CHECK: $xmm16 = VANDNPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3592 $xmm16 = VANDNPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3593 ; CHECK: $xmm16 = VANDNPDZ128rr $xmm16, $xmm1
3594 $xmm16 = VANDNPDZ128rr $xmm16, $xmm1
3595 ; CHECK: $xmm16 = VANDNPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3596 $xmm16 = VANDNPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3597 ; CHECK: $xmm16 = VANDNPSZ128rr $xmm16, $xmm1
3598 $xmm16 = VANDNPSZ128rr $xmm16, $xmm1
3599 ; CHECK: $xmm16 = VANDPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3600 $xmm16 = VANDPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3601 ; CHECK: $xmm16 = VANDPDZ128rr $xmm16, $xmm1
3602 $xmm16 = VANDPDZ128rr $xmm16, $xmm1
3603 ; CHECK: $xmm16 = VANDPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3604 $xmm16 = VANDPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3605 ; CHECK: $xmm16 = VANDPSZ128rr $xmm16, $xmm1
3606 $xmm16 = VANDPSZ128rr $xmm16, $xmm1
3607 ; CHECK: $xmm16 = VDIVPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3608 $xmm16 = VDIVPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3609 ; CHECK: $xmm16 = VDIVPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3610 $xmm16 = VDIVPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3611 ; CHECK: $xmm16 = VDIVPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3612 $xmm16 = VDIVPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3613 ; CHECK: $xmm16 = VDIVPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3614 $xmm16 = VDIVPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3615 ; CHECK: $xmm16 = VPXORDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3616 $xmm16 = VPXORDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3617 ; CHECK: $xmm16 = VPXORDZ128rr $xmm16, $xmm1
3618 $xmm16 = VPXORDZ128rr $xmm16, $xmm1
3619 ; CHECK: $xmm16 = VPXORQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3620 $xmm16 = VPXORQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3621 ; CHECK: $xmm16 = VPXORQZ128rr $xmm16, $xmm1
3622 $xmm16 = VPXORQZ128rr $xmm16, $xmm1
3623 ; CHECK: $xmm16 = VSUBPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3624 $xmm16 = VSUBPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3625 ; CHECK: $xmm16 = VSUBPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3626 $xmm16 = VSUBPDZ128rr $xmm16, $xmm1, implicit $mxcsr
3627 ; CHECK: $xmm16 = VSUBPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3628 $xmm16 = VSUBPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
3629 ; CHECK: $xmm16 = VSUBPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3630 $xmm16 = VSUBPSZ128rr $xmm16, $xmm1, implicit $mxcsr
3631 ; CHECK: $xmm16 = VXORPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3632 $xmm16 = VXORPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3633 ; CHECK: $xmm16 = VXORPDZ128rr $xmm16, $xmm1
3634 $xmm16 = VXORPDZ128rr $xmm16, $xmm1
3635 ; CHECK: $xmm16 = VXORPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3636 $xmm16 = VXORPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3637 ; CHECK: $xmm16 = VXORPSZ128rr $xmm16, $xmm1
3638 $xmm16 = VXORPSZ128rr $xmm16, $xmm1
3639 ; CHECK: $xmm16 = VPMADDUBSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3640 $xmm16 = VPMADDUBSWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3641 ; CHECK: $xmm16 = VPMADDUBSWZ128rr $xmm16, $xmm1
3642 $xmm16 = VPMADDUBSWZ128rr $xmm16, $xmm1
3643 ; CHECK: $xmm16 = VPMADDWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3644 $xmm16 = VPMADDWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3645 ; CHECK: $xmm16 = VPMADDWDZ128rr $xmm16, $xmm1
3646 $xmm16 = VPMADDWDZ128rr $xmm16, $xmm1
3647 ; CHECK: $xmm16 = VPACKSSDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3648 $xmm16 = VPACKSSDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3649 ; CHECK: $xmm16 = VPACKSSDWZ128rr $xmm16, $xmm1
3650 $xmm16 = VPACKSSDWZ128rr $xmm16, $xmm1
3651 ; CHECK: $xmm16 = VPACKSSWBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3652 $xmm16 = VPACKSSWBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3653 ; CHECK: $xmm16 = VPACKSSWBZ128rr $xmm16, $xmm1
3654 $xmm16 = VPACKSSWBZ128rr $xmm16, $xmm1
3655 ; CHECK: $xmm16 = VPACKUSDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3656 $xmm16 = VPACKUSDWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3657 ; CHECK: $xmm16 = VPACKUSDWZ128rr $xmm16, $xmm1
3658 $xmm16 = VPACKUSDWZ128rr $xmm16, $xmm1
3659 ; CHECK: $xmm16 = VPACKUSWBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3660 $xmm16 = VPACKUSWBZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3661 ; CHECK: $xmm16 = VPACKUSWBZ128rr $xmm16, $xmm1
3662 $xmm16 = VPACKUSWBZ128rr $xmm16, $xmm1
3663 ; CHECK: $xmm16 = VPUNPCKHBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3664 $xmm16 = VPUNPCKHBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3665 ; CHECK: $xmm16 = VPUNPCKHBWZ128rr $xmm16, $xmm1
3666 $xmm16 = VPUNPCKHBWZ128rr $xmm16, $xmm1
3667 ; CHECK: $xmm16 = VPUNPCKHDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3668 $xmm16 = VPUNPCKHDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3669 ; CHECK: $xmm16 = VPUNPCKHDQZ128rr $xmm16, $xmm1
3670 $xmm16 = VPUNPCKHDQZ128rr $xmm16, $xmm1
3671 ; CHECK: $xmm16 = VPUNPCKHQDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3672 $xmm16 = VPUNPCKHQDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3673 ; CHECK: $xmm16 = VPUNPCKHQDQZ128rr $xmm16, $xmm1
3674 $xmm16 = VPUNPCKHQDQZ128rr $xmm16, $xmm1
3675 ; CHECK: $xmm16 = VPUNPCKHWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3676 $xmm16 = VPUNPCKHWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3677 ; CHECK: $xmm16 = VPUNPCKHWDZ128rr $xmm16, $xmm1
3678 $xmm16 = VPUNPCKHWDZ128rr $xmm16, $xmm1
3679 ; CHECK: $xmm16 = VPUNPCKLBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3680 $xmm16 = VPUNPCKLBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3681 ; CHECK: $xmm16 = VPUNPCKLBWZ128rr $xmm16, $xmm1
3682 $xmm16 = VPUNPCKLBWZ128rr $xmm16, $xmm1
3683 ; CHECK: $xmm16 = VPUNPCKLDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3684 $xmm16 = VPUNPCKLDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3685 ; CHECK: $xmm16 = VPUNPCKLDQZ128rr $xmm16, $xmm1
3686 $xmm16 = VPUNPCKLDQZ128rr $xmm16, $xmm1
3687 ; CHECK: $xmm16 = VPUNPCKLQDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3688 $xmm16 = VPUNPCKLQDQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3689 ; CHECK: $xmm16 = VPUNPCKLQDQZ128rr $xmm16, $xmm1
3690 $xmm16 = VPUNPCKLQDQZ128rr $xmm16, $xmm1
3691 ; CHECK: $xmm16 = VPUNPCKLWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3692 $xmm16 = VPUNPCKLWDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3693 ; CHECK: $xmm16 = VPUNPCKLWDZ128rr $xmm16, $xmm1
3694 $xmm16 = VPUNPCKLWDZ128rr $xmm16, $xmm1
3695 ; CHECK: $xmm16 = VUNPCKHPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3696 $xmm16 = VUNPCKHPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3697 ; CHECK: $xmm16 = VUNPCKHPDZ128rr $xmm16, $xmm1
3698 $xmm16 = VUNPCKHPDZ128rr $xmm16, $xmm1
3699 ; CHECK: $xmm16 = VUNPCKHPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3700 $xmm16 = VUNPCKHPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3701 ; CHECK: $xmm16 = VUNPCKHPSZ128rr $xmm16, $xmm1
3702 $xmm16 = VUNPCKHPSZ128rr $xmm16, $xmm1
3703 ; CHECK: $xmm16 = VUNPCKLPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3704 $xmm16 = VUNPCKLPDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3705 ; CHECK: $xmm16 = VUNPCKLPDZ128rr $xmm16, $xmm1
3706 $xmm16 = VUNPCKLPDZ128rr $xmm16, $xmm1
3707 ; CHECK: $xmm16 = VUNPCKLPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3708 $xmm16 = VUNPCKLPSZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3709 ; CHECK: $xmm16 = VUNPCKLPSZ128rr $xmm16, $xmm1
3710 $xmm16 = VUNPCKLPSZ128rr $xmm16, $xmm1
3711 ; CHECK: $xmm16 = VFMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3712 $xmm16 = VFMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3713 ; CHECK: $xmm16 = VFMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3714 $xmm16 = VFMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3715 ; CHECK: $xmm16 = VFMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3716 $xmm16 = VFMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3717 ; CHECK: $xmm16 = VFMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3718 $xmm16 = VFMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3719 ; CHECK: $xmm16 = VFMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3720 $xmm16 = VFMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3721 ; CHECK: $xmm16 = VFMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3722 $xmm16 = VFMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3723 ; CHECK: $xmm16 = VFMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3724 $xmm16 = VFMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3725 ; CHECK: $xmm16 = VFMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3726 $xmm16 = VFMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3727 ; CHECK: $xmm16 = VFMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3728 $xmm16 = VFMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3729 ; CHECK: $xmm16 = VFMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3730 $xmm16 = VFMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3731 ; CHECK: $xmm16 = VFMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3732 $xmm16 = VFMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3733 ; CHECK: $xmm16 = VFMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3734 $xmm16 = VFMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3735 ; CHECK: $xmm16 = VFMADDSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3736 $xmm16 = VFMADDSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3737 ; CHECK: $xmm16 = VFMADDSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3738 $xmm16 = VFMADDSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3739 ; CHECK: $xmm16 = VFMADDSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3740 $xmm16 = VFMADDSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3741 ; CHECK: $xmm16 = VFMADDSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3742 $xmm16 = VFMADDSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3743 ; CHECK: $xmm16 = VFMADDSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3744 $xmm16 = VFMADDSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3745 ; CHECK: $xmm16 = VFMADDSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3746 $xmm16 = VFMADDSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3747 ; CHECK: $xmm16 = VFMADDSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3748 $xmm16 = VFMADDSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3749 ; CHECK: $xmm16 = VFMADDSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3750 $xmm16 = VFMADDSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3751 ; CHECK: $xmm16 = VFMADDSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3752 $xmm16 = VFMADDSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3753 ; CHECK: $xmm16 = VFMADDSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3754 $xmm16 = VFMADDSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3755 ; CHECK: $xmm16 = VFMADDSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3756 $xmm16 = VFMADDSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3757 ; CHECK: $xmm16 = VFMADDSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3758 $xmm16 = VFMADDSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3759 ; CHECK: $xmm16 = VFMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3760 $xmm16 = VFMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3761 ; CHECK: $xmm16 = VFMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3762 $xmm16 = VFMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3763 ; CHECK: $xmm16 = VFMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3764 $xmm16 = VFMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3765 ; CHECK: $xmm16 = VFMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3766 $xmm16 = VFMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3767 ; CHECK: $xmm16 = VFMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3768 $xmm16 = VFMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3769 ; CHECK: $xmm16 = VFMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3770 $xmm16 = VFMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3771 ; CHECK: $xmm16 = VFMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3772 $xmm16 = VFMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3773 ; CHECK: $xmm16 = VFMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3774 $xmm16 = VFMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3775 ; CHECK: $xmm16 = VFMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3776 $xmm16 = VFMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3777 ; CHECK: $xmm16 = VFMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3778 $xmm16 = VFMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3779 ; CHECK: $xmm16 = VFMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3780 $xmm16 = VFMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3781 ; CHECK: $xmm16 = VFMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3782 $xmm16 = VFMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3783 ; CHECK: $xmm16 = VFMSUBADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3784 $xmm16 = VFMSUBADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3785 ; CHECK: $xmm16 = VFMSUBADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3786 $xmm16 = VFMSUBADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3787 ; CHECK: $xmm16 = VFMSUBADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3788 $xmm16 = VFMSUBADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3789 ; CHECK: $xmm16 = VFMSUBADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3790 $xmm16 = VFMSUBADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3791 ; CHECK: $xmm16 = VFMSUBADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3792 $xmm16 = VFMSUBADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3793 ; CHECK: $xmm16 = VFMSUBADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3794 $xmm16 = VFMSUBADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3795 ; CHECK: $xmm16 = VFMSUBADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3796 $xmm16 = VFMSUBADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3797 ; CHECK: $xmm16 = VFMSUBADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3798 $xmm16 = VFMSUBADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3799 ; CHECK: $xmm16 = VFMSUBADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3800 $xmm16 = VFMSUBADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3801 ; CHECK: $xmm16 = VFMSUBADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3802 $xmm16 = VFMSUBADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3803 ; CHECK: $xmm16 = VFMSUBADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3804 $xmm16 = VFMSUBADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3805 ; CHECK: $xmm16 = VFMSUBADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3806 $xmm16 = VFMSUBADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3807 ; CHECK: $xmm16 = VFNMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3808 $xmm16 = VFNMADD132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3809 ; CHECK: $xmm16 = VFNMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3810 $xmm16 = VFNMADD132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3811 ; CHECK: $xmm16 = VFNMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3812 $xmm16 = VFNMADD132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3813 ; CHECK: $xmm16 = VFNMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3814 $xmm16 = VFNMADD132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3815 ; CHECK: $xmm16 = VFNMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3816 $xmm16 = VFNMADD213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3817 ; CHECK: $xmm16 = VFNMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3818 $xmm16 = VFNMADD213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3819 ; CHECK: $xmm16 = VFNMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3820 $xmm16 = VFNMADD213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3821 ; CHECK: $xmm16 = VFNMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3822 $xmm16 = VFNMADD213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3823 ; CHECK: $xmm16 = VFNMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3824 $xmm16 = VFNMADD231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3825 ; CHECK: $xmm16 = VFNMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3826 $xmm16 = VFNMADD231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3827 ; CHECK: $xmm16 = VFNMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3828 $xmm16 = VFNMADD231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3829 ; CHECK: $xmm16 = VFNMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3830 $xmm16 = VFNMADD231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3831 ; CHECK: $xmm16 = VFNMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3832 $xmm16 = VFNMSUB132PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3833 ; CHECK: $xmm16 = VFNMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3834 $xmm16 = VFNMSUB132PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3835 ; CHECK: $xmm16 = VFNMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3836 $xmm16 = VFNMSUB132PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3837 ; CHECK: $xmm16 = VFNMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3838 $xmm16 = VFNMSUB132PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3839 ; CHECK: $xmm16 = VFNMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3840 $xmm16 = VFNMSUB213PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3841 ; CHECK: $xmm16 = VFNMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3842 $xmm16 = VFNMSUB213PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3843 ; CHECK: $xmm16 = VFNMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3844 $xmm16 = VFNMSUB213PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3845 ; CHECK: $xmm16 = VFNMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3846 $xmm16 = VFNMSUB213PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3847 ; CHECK: $xmm16 = VFNMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3848 $xmm16 = VFNMSUB231PDZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3849 ; CHECK: $xmm16 = VFNMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3850 $xmm16 = VFNMSUB231PDZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3851 ; CHECK: $xmm16 = VFNMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3852 $xmm16 = VFNMSUB231PSZ128m $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
3853 ; CHECK: $xmm16 = VFNMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3854 $xmm16 = VFNMSUB231PSZ128r $xmm16, $xmm1, $xmm2, implicit $mxcsr
3855 ; CHECK: $xmm16 = VPSLLDZ128ri $xmm16, 7
3856 $xmm16 = VPSLLDZ128ri $xmm16, 7
3857 ; CHECK: $xmm16 = VPSLLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3858 $xmm16 = VPSLLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3859 ; CHECK: $xmm16 = VPSLLDZ128rr $xmm16, $xmm16
3860 $xmm16 = VPSLLDZ128rr $xmm16, $xmm16
3861 ; CHECK: $xmm16 = VPSLLQZ128ri $xmm16, 7
3862 $xmm16 = VPSLLQZ128ri $xmm16, 7
3863 ; CHECK: $xmm16 = VPSLLQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3864 $xmm16 = VPSLLQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3865 ; CHECK: $xmm16 = VPSLLQZ128rr $xmm16, $xmm16
3866 $xmm16 = VPSLLQZ128rr $xmm16, $xmm16
3867 ; CHECK: $xmm16 = VPSLLVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3868 $xmm16 = VPSLLVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3869 ; CHECK: $xmm16 = VPSLLVDZ128rr $xmm16, $xmm16
3870 $xmm16 = VPSLLVDZ128rr $xmm16, $xmm16
3871 ; CHECK: $xmm16 = VPSLLVQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3872 $xmm16 = VPSLLVQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3873 ; CHECK: $xmm16 = VPSLLVQZ128rr $xmm16, $xmm16
3874 $xmm16 = VPSLLVQZ128rr $xmm16, $xmm16
3875 ; CHECK: $xmm16 = VPSLLWZ128ri $xmm16, 7
3876 $xmm16 = VPSLLWZ128ri $xmm16, 7
3877 ; CHECK: $xmm16 = VPSLLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3878 $xmm16 = VPSLLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3879 ; CHECK: $xmm16 = VPSLLWZ128rr $xmm16, $xmm16
3880 $xmm16 = VPSLLWZ128rr $xmm16, $xmm16
3881 ; CHECK: $xmm16 = VPSRADZ128ri $xmm16, 7
3882 $xmm16 = VPSRADZ128ri $xmm16, 7
3883 ; CHECK: $xmm16 = VPSRADZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3884 $xmm16 = VPSRADZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3885 ; CHECK: $xmm16 = VPSRADZ128rr $xmm16, $xmm16
3886 $xmm16 = VPSRADZ128rr $xmm16, $xmm16
3887 ; CHECK: $xmm16 = VPSRAVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3888 $xmm16 = VPSRAVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3889 ; CHECK: $xmm16 = VPSRAVDZ128rr $xmm16, $xmm16
3890 $xmm16 = VPSRAVDZ128rr $xmm16, $xmm16
3891 ; CHECK: $xmm16 = VPSRAWZ128ri $xmm16, 7
3892 $xmm16 = VPSRAWZ128ri $xmm16, 7
3893 ; CHECK: $xmm16 = VPSRAWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3894 $xmm16 = VPSRAWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3895 ; CHECK: $xmm16 = VPSRAWZ128rr $xmm16, $xmm16
3896 $xmm16 = VPSRAWZ128rr $xmm16, $xmm16
3897 ; CHECK: $xmm16 = VPSRLDQZ128ri $xmm16, 14
3898 $xmm16 = VPSRLDQZ128ri $xmm16, 14
3899 ; CHECK: $xmm16 = VPSRLDZ128ri $xmm16, 7
3900 $xmm16 = VPSRLDZ128ri $xmm16, 7
3901 ; CHECK: $xmm16 = VPSRLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3902 $xmm16 = VPSRLDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3903 ; CHECK: $xmm16 = VPSRLDZ128rr $xmm16, $xmm16
3904 $xmm16 = VPSRLDZ128rr $xmm16, $xmm16
3905 ; CHECK: $xmm16 = VPSRLQZ128ri $xmm16, 7
3906 $xmm16 = VPSRLQZ128ri $xmm16, 7
3907 ; CHECK: $xmm16 = VPSRLQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3908 $xmm16 = VPSRLQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3909 ; CHECK: $xmm16 = VPSRLQZ128rr $xmm16, $xmm16
3910 $xmm16 = VPSRLQZ128rr $xmm16, $xmm16
3911 ; CHECK: $xmm16 = VPSRLVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3912 $xmm16 = VPSRLVDZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3913 ; CHECK: $xmm16 = VPSRLVDZ128rr $xmm16, $xmm16
3914 $xmm16 = VPSRLVDZ128rr $xmm16, $xmm16
3915 ; CHECK: $xmm16 = VPSRLVQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3916 $xmm16 = VPSRLVQZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3917 ; CHECK: $xmm16 = VPSRLVQZ128rr $xmm16, $xmm16
3918 $xmm16 = VPSRLVQZ128rr $xmm16, $xmm16
3919 ; CHECK: $xmm16 = VPSRLWZ128ri $xmm16, 7
3920 $xmm16 = VPSRLWZ128ri $xmm16, 7
3921 ; CHECK: $xmm16 = VPSRLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3922 $xmm16 = VPSRLWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
3923 ; CHECK: $xmm16 = VPSRLWZ128rr $xmm16, $xmm16
3924 $xmm16 = VPSRLWZ128rr $xmm16, $xmm16
3925 ; CHECK: $xmm16 = VPERMILPDZ128mi $rdi, 1, $noreg, 0, $noreg, 9
3926 $xmm16 = VPERMILPDZ128mi $rdi, 1, $noreg, 0, $noreg, 9
3927 ; CHECK: $xmm16 = VPERMILPDZ128ri $xmm16, 9
3928 $xmm16 = VPERMILPDZ128ri $xmm16, 9
3929 ; CHECK: $xmm16 = VPERMILPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3930 $xmm16 = VPERMILPDZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3931 ; CHECK: $xmm16 = VPERMILPDZ128rr $xmm16, $xmm1
3932 $xmm16 = VPERMILPDZ128rr $xmm16, $xmm1
3933 ; CHECK: $xmm16 = VPERMILPSZ128mi $rdi, 1, $noreg, 0, $noreg, 9
3934 $xmm16 = VPERMILPSZ128mi $rdi, 1, $noreg, 0, $noreg, 9
3935 ; CHECK: $xmm16 = VPERMILPSZ128ri $xmm16, 9
3936 $xmm16 = VPERMILPSZ128ri $xmm16, 9
3937 ; CHECK: $xmm16 = VPERMILPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3938 $xmm16 = VPERMILPSZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3939 ; CHECK: $xmm16 = VPERMILPSZ128rr $xmm16, $xmm1
3940 $xmm16 = VPERMILPSZ128rr $xmm16, $xmm1
3941 ; CHECK: $xmm16 = VCVTPH2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3942 $xmm16 = VCVTPH2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3943 ; CHECK: $xmm16 = VCVTPH2PSZ128rr $xmm16, implicit $mxcsr
3944 $xmm16 = VCVTPH2PSZ128rr $xmm16, implicit $mxcsr
3945 ; CHECK: $xmm16 = VCVTDQ2PDZ128rm $rdi, 1, $noreg, 0, $noreg
3946 $xmm16 = VCVTDQ2PDZ128rm $rdi, 1, $noreg, 0, $noreg
3947 ; CHECK: $xmm16 = VCVTDQ2PDZ128rr $xmm16
3948 $xmm16 = VCVTDQ2PDZ128rr $xmm16
3949 ; CHECK: $xmm16 = VCVTDQ2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3950 $xmm16 = VCVTDQ2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3951 ; CHECK: $xmm16 = VCVTDQ2PSZ128rr $xmm16, implicit $mxcsr
3952 $xmm16 = VCVTDQ2PSZ128rr $xmm16, implicit $mxcsr
3953 ; CHECK: $xmm16 = VCVTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3954 $xmm16 = VCVTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3955 ; CHECK: $xmm16 = VCVTPD2DQZ128rr $xmm16, implicit $mxcsr
3956 $xmm16 = VCVTPD2DQZ128rr $xmm16, implicit $mxcsr
3957 ; CHECK: $xmm16 = VCVTPD2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3958 $xmm16 = VCVTPD2PSZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3959 ; CHECK: $xmm16 = VCVTPD2PSZ128rr $xmm16, implicit $mxcsr
3960 $xmm16 = VCVTPD2PSZ128rr $xmm16, implicit $mxcsr
3961 ; CHECK: $xmm16 = VCVTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3962 $xmm16 = VCVTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3963 ; CHECK: $xmm16 = VCVTPS2DQZ128rr $xmm16, implicit $mxcsr
3964 $xmm16 = VCVTPS2DQZ128rr $xmm16, implicit $mxcsr
3965 ; CHECK: $xmm16 = VCVTPS2PDZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3966 $xmm16 = VCVTPS2PDZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3967 ; CHECK: $xmm16 = VCVTPS2PDZ128rr $xmm16, implicit $mxcsr
3968 $xmm16 = VCVTPS2PDZ128rr $xmm16, implicit $mxcsr
3969 ; CHECK: $xmm16 = VCVTTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3970 $xmm16 = VCVTTPD2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3971 ; CHECK: $xmm16 = VCVTTPD2DQZ128rr $xmm16, implicit $mxcsr
3972 $xmm16 = VCVTTPD2DQZ128rr $xmm16, implicit $mxcsr
3973 ; CHECK: $xmm16 = VCVTTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3974 $xmm16 = VCVTTPS2DQZ128rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3975 ; CHECK: $xmm16 = VCVTTPS2DQZ128rr $xmm16, implicit $mxcsr
3976 $xmm16 = VCVTTPS2DQZ128rr $xmm16, implicit $mxcsr
3977 ; CHECK: $xmm16 = VSQRTPDZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3978 $xmm16 = VSQRTPDZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3979 ; CHECK: $xmm16 = VSQRTPDZ128r $xmm16, implicit $mxcsr
3980 $xmm16 = VSQRTPDZ128r $xmm16, implicit $mxcsr
3981 ; CHECK: $xmm16 = VSQRTPSZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3982 $xmm16 = VSQRTPSZ128m $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
3983 ; CHECK: $xmm16 = VSQRTPSZ128r $xmm16, implicit $mxcsr
3984 $xmm16 = VSQRTPSZ128r $xmm16, implicit $mxcsr
3985 ; CHECK: $xmm16 = VMOVDDUPZ128rm $rdi, 1, $noreg, 0, $noreg
3986 $xmm16 = VMOVDDUPZ128rm $rdi, 1, $noreg, 0, $noreg
3987 ; CHECK: $xmm16 = VMOVDDUPZ128rr $xmm16
3988 $xmm16 = VMOVDDUPZ128rr $xmm16
3989 ; CHECK: $xmm16 = VMOVSHDUPZ128rm $rdi, 1, $noreg, 0, $noreg
3990 $xmm16 = VMOVSHDUPZ128rm $rdi, 1, $noreg, 0, $noreg
3991 ; CHECK: $xmm16 = VMOVSHDUPZ128rr $xmm16
3992 $xmm16 = VMOVSHDUPZ128rr $xmm16
3993 ; CHECK: $xmm16 = VMOVSLDUPZ128rm $rdi, 1, $noreg, 0, $noreg
3994 $xmm16 = VMOVSLDUPZ128rm $rdi, 1, $noreg, 0, $noreg
3995 ; CHECK: $xmm16 = VMOVSLDUPZ128rr $xmm16
3996 $xmm16 = VMOVSLDUPZ128rr $xmm16
3997 ; CHECK: $xmm16 = VPSHUFBZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3998 $xmm16 = VPSHUFBZ128rm $xmm16, $rdi, 1, $noreg, 0, $noreg
3999 ; CHECK: $xmm16 = VPSHUFBZ128rr $xmm16, $xmm1
4000 $xmm16 = VPSHUFBZ128rr $xmm16, $xmm1
4001 ; CHECK: $xmm16 = VPSHUFDZ128mi $rdi, 1, $noreg, 0, $noreg, -24
4002 $xmm16 = VPSHUFDZ128mi $rdi, 1, $noreg, 0, $noreg, -24
4003 ; CHECK: $xmm16 = VPSHUFDZ128ri $xmm16, -24
4004 $xmm16 = VPSHUFDZ128ri $xmm16, -24
4005 ; CHECK: $xmm16 = VPSHUFHWZ128mi $rdi, 1, $noreg, 0, $noreg, -24
4006 $xmm16 = VPSHUFHWZ128mi $rdi, 1, $noreg, 0, $noreg, -24
4007 ; CHECK: $xmm16 = VPSHUFHWZ128ri $xmm16, -24
4008 $xmm16 = VPSHUFHWZ128ri $xmm16, -24
4009 ; CHECK: $xmm16 = VPSHUFLWZ128mi $rdi, 1, $noreg, 0, $noreg, -24
4010 $xmm16 = VPSHUFLWZ128mi $rdi, 1, $noreg, 0, $noreg, -24
4011 ; CHECK: $xmm16 = VPSHUFLWZ128ri $xmm16, -24
4012 $xmm16 = VPSHUFLWZ128ri $xmm16, -24
4013 ; CHECK: $xmm16 = VPSLLDQZ128ri $xmm16, 1
4014 $xmm16 = VPSLLDQZ128ri $xmm16, 1
4015 ; CHECK: $xmm16 = VSHUFPDZ128rmi $xmm16, $rip, 1, $noreg, 0, $noreg, -24
4016 $xmm16 = VSHUFPDZ128rmi $xmm16, $rip, 1, $noreg, 0, $noreg, -24
4017 ; CHECK: $xmm16 = VSHUFPDZ128rri $xmm16, $xmm1, -24
4018 $xmm16 = VSHUFPDZ128rri $xmm16, $xmm1, -24
4019 ; CHECK: $xmm16 = VSHUFPSZ128rmi $xmm16, $rip, 1, $noreg, 0, $noreg, -24
4020 $xmm16 = VSHUFPSZ128rmi $xmm16, $rip, 1, $noreg, 0, $noreg, -24
4021 ; CHECK: $xmm16 = VSHUFPSZ128rri $xmm16, $xmm1, -24
4022 $xmm16 = VSHUFPSZ128rri $xmm16, $xmm1, -24
4023 ; CHECK: $xmm16 = VPSADBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
4024 $xmm16 = VPSADBWZ128rm $xmm16, $rip, 1, $noreg, 0, $noreg
4025 ; CHECK: $xmm16 = VPSADBWZ128rr $xmm16, $xmm1
4026 $xmm16 = VPSADBWZ128rr $xmm16, $xmm1
4027 ; CHECK: $xmm16 = VBROADCASTSSZ128rm $rip, 1, $noreg, 0, $noreg
4028 $xmm16 = VBROADCASTSSZ128rm $rip, 1, $noreg, 0, $noreg
4029 ; CHECK: $xmm16 = VBROADCASTSSZ128rr $xmm16
4030 $xmm16 = VBROADCASTSSZ128rr $xmm16
4031 ; CHECK: $xmm16 = VPBROADCASTBZ128rm $rip, 1, $noreg, 0, $noreg
4032 $xmm16 = VPBROADCASTBZ128rm $rip, 1, $noreg, 0, $noreg
4033 ; CHECK: $xmm16 = VPBROADCASTBZ128rr $xmm16
4034 $xmm16 = VPBROADCASTBZ128rr $xmm16
4035 ; CHECK: $xmm16 = VPBROADCASTDZ128rm $rip, 1, $noreg, 0, $noreg
4036 $xmm16 = VPBROADCASTDZ128rm $rip, 1, $noreg, 0, $noreg
4037 ; CHECK: $xmm16 = VPBROADCASTDZ128rr $xmm16
4038 $xmm16 = VPBROADCASTDZ128rr $xmm16
4039 ; CHECK: $xmm16 = VPBROADCASTQZ128rm $rip, 1, $noreg, 0, $noreg
4040 $xmm16 = VPBROADCASTQZ128rm $rip, 1, $noreg, 0, $noreg
4041 ; CHECK: $xmm16 = VPBROADCASTQZ128rr $xmm16
4042 $xmm16 = VPBROADCASTQZ128rr $xmm16
4043 ; CHECK: $xmm16 = VPBROADCASTWZ128rm $rip, 1, $noreg, 0, $noreg
4044 $xmm16 = VPBROADCASTWZ128rm $rip, 1, $noreg, 0, $noreg
4045 ; CHECK: $xmm16 = VPBROADCASTWZ128rr $xmm16
4046 $xmm16 = VPBROADCASTWZ128rr $xmm16
4047 ; CHECK: $xmm16 = VBROADCASTI32X2Z128rm $rip, 1, $noreg, 0, $noreg
4048 $xmm16 = VBROADCASTI32X2Z128rm $rip, 1, $noreg, 0, $noreg
4049 ; CHECK: $xmm16 = VBROADCASTI32X2Z128rr $xmm0
4050 $xmm16 = VBROADCASTI32X2Z128rr $xmm0
4051 ; CHECK: $xmm16 = VCVTPS2PHZ128rr $xmm16, 2, implicit $mxcsr
4052 $xmm16 = VCVTPS2PHZ128rr $xmm16, 2, implicit $mxcsr
4053 ; CHECK: VCVTPS2PHZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16, 2, implicit $mxcsr
4054 VCVTPS2PHZ128mr $rdi, 1, $noreg, 0, $noreg, $xmm16, 2, implicit $mxcsr
4055 ; CHECK: $xmm16 = VPABSBZ128rm $rip, 1, $noreg, 0, $noreg
4056 $xmm16 = VPABSBZ128rm $rip, 1, $noreg, 0, $noreg
4057 ; CHECK: $xmm16 = VPABSBZ128rr $xmm16
4058 $xmm16 = VPABSBZ128rr $xmm16
4059 ; CHECK: $xmm16 = VPABSDZ128rm $rip, 1, $noreg, 0, $noreg
4060 $xmm16 = VPABSDZ128rm $rip, 1, $noreg, 0, $noreg
4061 ; CHECK: $xmm16 = VPABSDZ128rr $xmm16
4062 $xmm16 = VPABSDZ128rr $xmm16
4063 ; CHECK: $xmm16 = VPABSWZ128rm $rip, 1, $noreg, 0, $noreg
4064 $xmm16 = VPABSWZ128rm $rip, 1, $noreg, 0, $noreg
4065 ; CHECK: $xmm16 = VPABSWZ128rr $xmm16
4066 $xmm16 = VPABSWZ128rr $xmm16
4067 ; CHECK: $xmm16 = VPALIGNRZ128rmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 15
4068 $xmm16 = VPALIGNRZ128rmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 15
4069 ; CHECK: $xmm16 = VPALIGNRZ128rri $xmm16, $xmm1, 15
4070 $xmm16 = VPALIGNRZ128rri $xmm16, $xmm1, 15
4071 ; CHECK: VEXTRACTPSZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 1
4072 VEXTRACTPSZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 1
4073 ; CHECK: $eax = VEXTRACTPSZrr $xmm16, 1
4074 $eax = VEXTRACTPSZrr $xmm16, 1
4075 ; CHECK: $xmm16 = VINSERTPSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
4076 $xmm16 = VINSERTPSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
4077 ; CHECK: $xmm16 = VINSERTPSZrr $xmm16, $xmm16, 1
4078 $xmm16 = VINSERTPSZrr $xmm16, $xmm16, 1
4079 ; CHECK: $xmm16 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4080 $xmm16 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4081 ; CHECK: $xmm16 = VRNDSCALEPDZ128rri $xmm16, 15, implicit $mxcsr
4082 $xmm16 = VRNDSCALEPDZ128rri $xmm16, 15, implicit $mxcsr
4083 ; CHECK: $xmm16 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4084 $xmm16 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4085 ; CHECK: $xmm16 = VRNDSCALEPSZ128rri $xmm16, 15, implicit $mxcsr
4086 $xmm16 = VRNDSCALEPSZ128rri $xmm16, 15, implicit $mxcsr
4087 ; CHECK: $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4088 $xmm0 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4089 ; CHECK: $xmm0 = VRNDSCALEPDZ128rri $xmm0, 31, implicit $mxcsr
4090 $xmm0 = VRNDSCALEPDZ128rri $xmm0, 31, implicit $mxcsr
4091 ; CHECK: $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4092 $xmm0 = VRNDSCALEPSZ128rmi $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4093 ; CHECK: $xmm0 = VRNDSCALEPSZ128rri $xmm0, 31, implicit $mxcsr
4094 $xmm0 = VRNDSCALEPSZ128rri $xmm0, 31, implicit $mxcsr
4096 RET64
4097 ...
4098 ---
4099 # CHECK-LABEL: name: evex_scalar_to_evex_test
4100 # CHECK: bb.0:
4102 name: evex_scalar_to_evex_test
4103 body: |
4104 bb.0:
4105 ; CHECK: $xmm16 = VADDSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4106 $xmm16 = VADDSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4107 ; CHECK: $xmm16 = VADDSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4108 $xmm16 = VADDSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4109 ; CHECK: $xmm16 = VADDSDZrr $xmm16, $xmm1, implicit $mxcsr
4110 $xmm16 = VADDSDZrr $xmm16, $xmm1, implicit $mxcsr
4111 ; CHECK: $xmm16 = VADDSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4112 $xmm16 = VADDSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4113 ; CHECK: $xmm16 = VADDSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4114 $xmm16 = VADDSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4115 ; CHECK: $xmm16 = VADDSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4116 $xmm16 = VADDSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4117 ; CHECK: $xmm16 = VADDSSZrr $xmm16, $xmm1, implicit $mxcsr
4118 $xmm16 = VADDSSZrr $xmm16, $xmm1, implicit $mxcsr
4119 ; CHECK: $xmm16 = VADDSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4120 $xmm16 = VADDSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4121 ; CHECK: $xmm16 = VDIVSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4122 $xmm16 = VDIVSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4123 ; CHECK: $xmm16 = VDIVSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4124 $xmm16 = VDIVSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4125 ; CHECK: $xmm16 = VDIVSDZrr $xmm16, $xmm1, implicit $mxcsr
4126 $xmm16 = VDIVSDZrr $xmm16, $xmm1, implicit $mxcsr
4127 ; CHECK: $xmm16 = VDIVSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4128 $xmm16 = VDIVSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4129 ; CHECK: $xmm16 = VDIVSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4130 $xmm16 = VDIVSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4131 ; CHECK: $xmm16 = VDIVSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4132 $xmm16 = VDIVSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4133 ; CHECK: $xmm16 = VDIVSSZrr $xmm16, $xmm1, implicit $mxcsr
4134 $xmm16 = VDIVSSZrr $xmm16, $xmm1, implicit $mxcsr
4135 ; CHECK: $xmm16 = VDIVSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4136 $xmm16 = VDIVSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4137 ; CHECK: $xmm16 = VMAXCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4138 $xmm16 = VMAXCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4139 ; CHECK: $xmm16 = VMAXCSDZrr $xmm16, $xmm1, implicit $mxcsr
4140 $xmm16 = VMAXCSDZrr $xmm16, $xmm1, implicit $mxcsr
4141 ; CHECK: $xmm16 = VMAXCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4142 $xmm16 = VMAXCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4143 ; CHECK: $xmm16 = VMAXCSSZrr $xmm16, $xmm1, implicit $mxcsr
4144 $xmm16 = VMAXCSSZrr $xmm16, $xmm1, implicit $mxcsr
4145 ; CHECK: $xmm16 = VMAXSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4146 $xmm16 = VMAXSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4147 ; CHECK: $xmm16 = VMAXSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4148 $xmm16 = VMAXSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4149 ; CHECK: $xmm16 = VMAXSDZrr $xmm16, $xmm1, implicit $mxcsr
4150 $xmm16 = VMAXSDZrr $xmm16, $xmm1, implicit $mxcsr
4151 ; CHECK: $xmm16 = VMAXSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4152 $xmm16 = VMAXSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4153 ; CHECK: $xmm16 = VMAXSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4154 $xmm16 = VMAXSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4155 ; CHECK: $xmm16 = VMAXSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4156 $xmm16 = VMAXSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4157 ; CHECK: $xmm16 = VMAXSSZrr $xmm16, $xmm1, implicit $mxcsr
4158 $xmm16 = VMAXSSZrr $xmm16, $xmm1, implicit $mxcsr
4159 ; CHECK: $xmm16 = VMAXSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4160 $xmm16 = VMAXSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4161 ; CHECK: $xmm16 = VMINCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4162 $xmm16 = VMINCSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4163 ; CHECK: $xmm16 = VMINCSDZrr $xmm16, $xmm1, implicit $mxcsr
4164 $xmm16 = VMINCSDZrr $xmm16, $xmm1, implicit $mxcsr
4165 ; CHECK: $xmm16 = VMINCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4166 $xmm16 = VMINCSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4167 ; CHECK: $xmm16 = VMINCSSZrr $xmm16, $xmm1, implicit $mxcsr
4168 $xmm16 = VMINCSSZrr $xmm16, $xmm1, implicit $mxcsr
4169 ; CHECK: $xmm16 = VMINSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4170 $xmm16 = VMINSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4171 ; CHECK: $xmm16 = VMINSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4172 $xmm16 = VMINSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4173 ; CHECK: $xmm16 = VMINSDZrr $xmm16, $xmm1, implicit $mxcsr
4174 $xmm16 = VMINSDZrr $xmm16, $xmm1, implicit $mxcsr
4175 ; CHECK: $xmm16 = VMINSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4176 $xmm16 = VMINSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4177 ; CHECK: $xmm16 = VMINSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4178 $xmm16 = VMINSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4179 ; CHECK: $xmm16 = VMINSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4180 $xmm16 = VMINSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4181 ; CHECK: $xmm16 = VMINSSZrr $xmm16, $xmm1, implicit $mxcsr
4182 $xmm16 = VMINSSZrr $xmm16, $xmm1, implicit $mxcsr
4183 ; CHECK: $xmm16 = VMINSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4184 $xmm16 = VMINSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4185 ; CHECK: $xmm16 = VMULSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4186 $xmm16 = VMULSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4187 ; CHECK: $xmm16 = VMULSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4188 $xmm16 = VMULSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4189 ; CHECK: $xmm16 = VMULSDZrr $xmm16, $xmm1, implicit $mxcsr
4190 $xmm16 = VMULSDZrr $xmm16, $xmm1, implicit $mxcsr
4191 ; CHECK: $xmm16 = VMULSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4192 $xmm16 = VMULSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4193 ; CHECK: $xmm16 = VMULSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4194 $xmm16 = VMULSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4195 ; CHECK: $xmm16 = VMULSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4196 $xmm16 = VMULSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4197 ; CHECK: $xmm16 = VMULSSZrr $xmm16, $xmm1, implicit $mxcsr
4198 $xmm16 = VMULSSZrr $xmm16, $xmm1, implicit $mxcsr
4199 ; CHECK: $xmm16 = VMULSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4200 $xmm16 = VMULSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4201 ; CHECK: $xmm16 = VSUBSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4202 $xmm16 = VSUBSDZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4203 ; CHECK: $xmm16 = VSUBSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4204 $xmm16 = VSUBSDZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4205 ; CHECK: $xmm16 = VSUBSDZrr $xmm16, $xmm1, implicit $mxcsr
4206 $xmm16 = VSUBSDZrr $xmm16, $xmm1, implicit $mxcsr
4207 ; CHECK: $xmm16 = VSUBSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4208 $xmm16 = VSUBSDZrr_Int $xmm16, $xmm1, implicit $mxcsr
4209 ; CHECK: $xmm16 = VSUBSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4210 $xmm16 = VSUBSSZrm $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4211 ; CHECK: $xmm16 = VSUBSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4212 $xmm16 = VSUBSSZrm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, implicit $mxcsr
4213 ; CHECK: $xmm16 = VSUBSSZrr $xmm16, $xmm1, implicit $mxcsr
4214 $xmm16 = VSUBSSZrr $xmm16, $xmm1, implicit $mxcsr
4215 ; CHECK: $xmm16 = VSUBSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4216 $xmm16 = VSUBSSZrr_Int $xmm16, $xmm1, implicit $mxcsr
4217 ; CHECK: $xmm16 = VFMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4218 $xmm16 = VFMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4219 ; CHECK: $xmm16 = VFMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4220 $xmm16 = VFMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4221 ; CHECK: $xmm16 = VFMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4222 $xmm16 = VFMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4223 ; CHECK: $xmm16 = VFMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4224 $xmm16 = VFMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4225 ; CHECK: $xmm16 = VFMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4226 $xmm16 = VFMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4227 ; CHECK: $xmm16 = VFMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4228 $xmm16 = VFMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4229 ; CHECK: $xmm16 = VFMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4230 $xmm16 = VFMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4231 ; CHECK: $xmm16 = VFMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4232 $xmm16 = VFMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4233 ; CHECK: $xmm16 = VFMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4234 $xmm16 = VFMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4235 ; CHECK: $xmm16 = VFMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4236 $xmm16 = VFMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4237 ; CHECK: $xmm16 = VFMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4238 $xmm16 = VFMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4239 ; CHECK: $xmm16 = VFMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4240 $xmm16 = VFMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4241 ; CHECK: $xmm16 = VFMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4242 $xmm16 = VFMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4243 ; CHECK: $xmm16 = VFMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4244 $xmm16 = VFMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4245 ; CHECK: $xmm16 = VFMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4246 $xmm16 = VFMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4247 ; CHECK: $xmm16 = VFMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4248 $xmm16 = VFMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4249 ; CHECK: $xmm16 = VFMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4250 $xmm16 = VFMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4251 ; CHECK: $xmm16 = VFMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4252 $xmm16 = VFMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4253 ; CHECK: $xmm16 = VFMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4254 $xmm16 = VFMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4255 ; CHECK: $xmm16 = VFMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4256 $xmm16 = VFMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4257 ; CHECK: $xmm16 = VFMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4258 $xmm16 = VFMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4259 ; CHECK: $xmm16 = VFMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4260 $xmm16 = VFMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4261 ; CHECK: $xmm16 = VFMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4262 $xmm16 = VFMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4263 ; CHECK: $xmm16 = VFMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4264 $xmm16 = VFMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4265 ; CHECK: $xmm16 = VFMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4266 $xmm16 = VFMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4267 ; CHECK: $xmm16 = VFMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4268 $xmm16 = VFMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4269 ; CHECK: $xmm16 = VFMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4270 $xmm16 = VFMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4271 ; CHECK: $xmm16 = VFMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4272 $xmm16 = VFMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4273 ; CHECK: $xmm16 = VFMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4274 $xmm16 = VFMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4275 ; CHECK: $xmm16 = VFMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4276 $xmm16 = VFMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4277 ; CHECK: $xmm16 = VFMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4278 $xmm16 = VFMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4279 ; CHECK: $xmm16 = VFMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4280 $xmm16 = VFMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4281 ; CHECK: $xmm16 = VFMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4282 $xmm16 = VFMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4283 ; CHECK: $xmm16 = VFMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4284 $xmm16 = VFMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4285 ; CHECK: $xmm16 = VFMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4286 $xmm16 = VFMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4287 ; CHECK: $xmm16 = VFMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4288 $xmm16 = VFMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4289 ; CHECK: $xmm16 = VFMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4290 $xmm16 = VFMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4291 ; CHECK: $xmm16 = VFMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4292 $xmm16 = VFMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4293 ; CHECK: $xmm16 = VFMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4294 $xmm16 = VFMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4295 ; CHECK: $xmm16 = VFMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4296 $xmm16 = VFMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4297 ; CHECK: $xmm16 = VFMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4298 $xmm16 = VFMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4299 ; CHECK: $xmm16 = VFMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4300 $xmm16 = VFMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4301 ; CHECK: $xmm16 = VFMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4302 $xmm16 = VFMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4303 ; CHECK: $xmm16 = VFMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4304 $xmm16 = VFMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4305 ; CHECK: $xmm16 = VFMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4306 $xmm16 = VFMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4307 ; CHECK: $xmm16 = VFMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4308 $xmm16 = VFMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4309 ; CHECK: $xmm16 = VFMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4310 $xmm16 = VFMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4311 ; CHECK: $xmm16 = VFMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4312 $xmm16 = VFMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4313 ; CHECK: $xmm16 = VFNMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4314 $xmm16 = VFNMADD132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4315 ; CHECK: $xmm16 = VFNMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4316 $xmm16 = VFNMADD132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4317 ; CHECK: $xmm16 = VFNMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4318 $xmm16 = VFNMADD132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4319 ; CHECK: $xmm16 = VFNMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4320 $xmm16 = VFNMADD132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4321 ; CHECK: $xmm16 = VFNMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4322 $xmm16 = VFNMADD132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4323 ; CHECK: $xmm16 = VFNMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4324 $xmm16 = VFNMADD132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4325 ; CHECK: $xmm16 = VFNMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4326 $xmm16 = VFNMADD132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4327 ; CHECK: $xmm16 = VFNMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4328 $xmm16 = VFNMADD132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4329 ; CHECK: $xmm16 = VFNMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4330 $xmm16 = VFNMADD213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4331 ; CHECK: $xmm16 = VFNMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4332 $xmm16 = VFNMADD213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4333 ; CHECK: $xmm16 = VFNMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4334 $xmm16 = VFNMADD213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4335 ; CHECK: $xmm16 = VFNMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4336 $xmm16 = VFNMADD213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4337 ; CHECK: $xmm16 = VFNMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4338 $xmm16 = VFNMADD213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4339 ; CHECK: $xmm16 = VFNMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4340 $xmm16 = VFNMADD213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4341 ; CHECK: $xmm16 = VFNMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4342 $xmm16 = VFNMADD213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4343 ; CHECK: $xmm16 = VFNMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4344 $xmm16 = VFNMADD213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4345 ; CHECK: $xmm16 = VFNMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4346 $xmm16 = VFNMADD231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4347 ; CHECK: $xmm16 = VFNMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4348 $xmm16 = VFNMADD231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4349 ; CHECK: $xmm16 = VFNMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4350 $xmm16 = VFNMADD231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4351 ; CHECK: $xmm16 = VFNMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4352 $xmm16 = VFNMADD231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4353 ; CHECK: $xmm16 = VFNMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4354 $xmm16 = VFNMADD231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4355 ; CHECK: $xmm16 = VFNMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4356 $xmm16 = VFNMADD231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4357 ; CHECK: $xmm16 = VFNMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4358 $xmm16 = VFNMADD231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4359 ; CHECK: $xmm16 = VFNMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4360 $xmm16 = VFNMADD231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4361 ; CHECK: $xmm16 = VFNMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4362 $xmm16 = VFNMSUB132SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4363 ; CHECK: $xmm16 = VFNMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4364 $xmm16 = VFNMSUB132SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4365 ; CHECK: $xmm16 = VFNMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4366 $xmm16 = VFNMSUB132SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4367 ; CHECK: $xmm16 = VFNMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4368 $xmm16 = VFNMSUB132SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4369 ; CHECK: $xmm16 = VFNMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4370 $xmm16 = VFNMSUB132SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4371 ; CHECK: $xmm16 = VFNMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4372 $xmm16 = VFNMSUB132SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4373 ; CHECK: $xmm16 = VFNMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4374 $xmm16 = VFNMSUB132SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4375 ; CHECK: $xmm16 = VFNMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4376 $xmm16 = VFNMSUB132SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4377 ; CHECK: $xmm16 = VFNMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4378 $xmm16 = VFNMSUB213SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4379 ; CHECK: $xmm16 = VFNMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4380 $xmm16 = VFNMSUB213SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4381 ; CHECK: $xmm16 = VFNMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4382 $xmm16 = VFNMSUB213SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4383 ; CHECK: $xmm16 = VFNMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4384 $xmm16 = VFNMSUB213SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4385 ; CHECK: $xmm16 = VFNMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4386 $xmm16 = VFNMSUB213SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4387 ; CHECK: $xmm16 = VFNMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4388 $xmm16 = VFNMSUB213SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4389 ; CHECK: $xmm16 = VFNMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4390 $xmm16 = VFNMSUB213SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4391 ; CHECK: $xmm16 = VFNMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4392 $xmm16 = VFNMSUB213SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4393 ; CHECK: $xmm16 = VFNMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4394 $xmm16 = VFNMSUB231SDZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4395 ; CHECK: $xmm16 = VFNMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4396 $xmm16 = VFNMSUB231SDZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4397 ; CHECK: $xmm16 = VFNMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4398 $xmm16 = VFNMSUB231SDZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4399 ; CHECK: $xmm16 = VFNMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4400 $xmm16 = VFNMSUB231SDZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4401 ; CHECK: $xmm16 = VFNMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4402 $xmm16 = VFNMSUB231SSZm $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4403 ; CHECK: $xmm16 = VFNMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4404 $xmm16 = VFNMSUB231SSZm_Int $xmm16, $xmm16, $rsi, 1, $noreg, 0, $noreg, implicit $mxcsr
4405 ; CHECK: $xmm16 = VFNMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4406 $xmm16 = VFNMSUB231SSZr $xmm16, $xmm1, $xmm2, implicit $mxcsr
4407 ; CHECK: $xmm16 = VFNMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4408 $xmm16 = VFNMSUB231SSZr_Int $xmm16, $xmm1, $xmm2, implicit $mxcsr
4409 ; CHECK: VPEXTRBZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
4410 VPEXTRBZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
4411 ; CHECK: $eax = VPEXTRBZrr $xmm16, 1
4412 $eax = VPEXTRBZrr $xmm16, 1
4413 ; CHECK: VPEXTRDZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
4414 VPEXTRDZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
4415 ; CHECK: $eax = VPEXTRDZrr $xmm16, 1
4416 $eax = VPEXTRDZrr $xmm16, 1
4417 ; CHECK: VPEXTRQZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
4418 VPEXTRQZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
4419 ; CHECK: $rax = VPEXTRQZrr $xmm16, 1
4420 $rax = VPEXTRQZrr $xmm16, 1
4421 ; CHECK: VPEXTRWZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
4422 VPEXTRWZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 3
4423 ; CHECK: $eax = VPEXTRWZrr $xmm16, 1
4424 $eax = VPEXTRWZrr $xmm16, 1
4425 ; CHECK: $xmm16 = VPINSRBZrm $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
4426 $xmm16 = VPINSRBZrm $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
4427 ; CHECK: $xmm16 = VPINSRBZrr $xmm16, $edi, 5
4428 $xmm16 = VPINSRBZrr $xmm16, $edi, 5
4429 ; CHECK: $xmm16 = VPINSRDZrm $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
4430 $xmm16 = VPINSRDZrm $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
4431 ; CHECK: $xmm16 = VPINSRDZrr $xmm16, $edi, 5
4432 $xmm16 = VPINSRDZrr $xmm16, $edi, 5
4433 ; CHECK: $xmm16 = VPINSRQZrm $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
4434 $xmm16 = VPINSRQZrm $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
4435 ; CHECK: $xmm16 = VPINSRQZrr $xmm16, $rdi, 5
4436 $xmm16 = VPINSRQZrr $xmm16, $rdi, 5
4437 ; CHECK: $xmm16 = VPINSRWZrm $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
4438 $xmm16 = VPINSRWZrm $xmm16, $rsi, 1, $noreg, 0, $noreg, 3
4439 ; CHECK: $xmm16 = VPINSRWZrr $xmm16, $edi, 5
4440 $xmm16 = VPINSRWZrr $xmm16, $edi, 5
4441 ; CHECK: $xmm16 = VSQRTSDZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4442 $xmm16 = VSQRTSDZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4443 ; CHECK: $xmm16 = VSQRTSDZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4444 $xmm16 = VSQRTSDZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4445 ; CHECK: $xmm16 = VSQRTSDZr $xmm16, $xmm1, implicit $mxcsr
4446 $xmm16 = VSQRTSDZr $xmm16, $xmm1, implicit $mxcsr
4447 ; CHECK: $xmm16 = VSQRTSDZr_Int $xmm16, $xmm1, implicit $mxcsr
4448 $xmm16 = VSQRTSDZr_Int $xmm16, $xmm1, implicit $mxcsr
4449 ; CHECK: $xmm16 = VSQRTSSZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4450 $xmm16 = VSQRTSSZm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4451 ; CHECK: $xmm16 = VSQRTSSZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4452 $xmm16 = VSQRTSSZm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4453 ; CHECK: $xmm16 = VSQRTSSZr $xmm16, $xmm1, implicit $mxcsr
4454 $xmm16 = VSQRTSSZr $xmm16, $xmm1, implicit $mxcsr
4455 ; CHECK: $xmm16 = VSQRTSSZr_Int $xmm16, $xmm1, implicit $mxcsr
4456 $xmm16 = VSQRTSSZr_Int $xmm16, $xmm1, implicit $mxcsr
4457 ; CHECK: $rdi = VCVTSD2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4458 $rdi = VCVTSD2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4459 ; CHECK: $rdi = VCVTSD2SI64Zrr_Int $xmm16, implicit $mxcsr
4460 $rdi = VCVTSD2SI64Zrr_Int $xmm16, implicit $mxcsr
4461 ; CHECK: $edi = VCVTSD2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4462 $edi = VCVTSD2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4463 ; CHECK: $edi = VCVTSD2SIZrr_Int $xmm16, implicit $mxcsr
4464 $edi = VCVTSD2SIZrr_Int $xmm16, implicit $mxcsr
4465 ; CHECK: $xmm16 = VCVTSD2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4466 $xmm16 = VCVTSD2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4467 ; CHECK: $xmm16 = VCVTSD2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4468 $xmm16 = VCVTSD2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4469 ; CHECK: $xmm16 = VCVTSD2SSZrr $xmm16, $xmm16, implicit $mxcsr
4470 $xmm16 = VCVTSD2SSZrr $xmm16, $xmm16, implicit $mxcsr
4471 ; CHECK: $xmm16 = VCVTSD2SSZrr_Int $xmm16, $xmm16, implicit $mxcsr
4472 $xmm16 = VCVTSD2SSZrr_Int $xmm16, $xmm16, implicit $mxcsr
4473 ; CHECK: $xmm16 = VCVTSI2SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg
4474 $xmm16 = VCVTSI2SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg
4475 ; CHECK: $xmm16 = VCVTSI2SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg
4476 $xmm16 = VCVTSI2SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg
4477 ; CHECK: $xmm16 = VCVTSI2SDZrr $xmm16, $edi
4478 $xmm16 = VCVTSI2SDZrr $xmm16, $edi
4479 ; CHECK: $xmm16 = VCVTSI2SDZrr_Int $xmm16, $edi
4480 $xmm16 = VCVTSI2SDZrr_Int $xmm16, $edi
4481 ; CHECK: $xmm16 = VCVTSI2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4482 $xmm16 = VCVTSI2SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4483 ; CHECK: $xmm16 = VCVTSI2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4484 $xmm16 = VCVTSI2SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4485 ; CHECK: $xmm16 = VCVTSI2SSZrr $xmm16, $edi, implicit $mxcsr
4486 $xmm16 = VCVTSI2SSZrr $xmm16, $edi, implicit $mxcsr
4487 ; CHECK: $xmm16 = VCVTSI2SSZrr_Int $xmm16, $edi, implicit $mxcsr
4488 $xmm16 = VCVTSI2SSZrr_Int $xmm16, $edi, implicit $mxcsr
4489 ; CHECK: $xmm16 = VCVTSI642SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4490 $xmm16 = VCVTSI642SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4491 ; CHECK: $xmm16 = VCVTSI642SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4492 $xmm16 = VCVTSI642SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4493 ; CHECK: $xmm16 = VCVTSI642SDZrr $xmm16, $rdi, implicit $mxcsr
4494 $xmm16 = VCVTSI642SDZrr $xmm16, $rdi, implicit $mxcsr
4495 ; CHECK: $xmm16 = VCVTSI642SDZrr_Int $xmm16, $rdi, implicit $mxcsr
4496 $xmm16 = VCVTSI642SDZrr_Int $xmm16, $rdi, implicit $mxcsr
4497 ; CHECK: $xmm16 = VCVTSI642SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4498 $xmm16 = VCVTSI642SSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4499 ; CHECK: $xmm16 = VCVTSI642SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4500 $xmm16 = VCVTSI642SSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4501 ; CHECK: $xmm16 = VCVTSI642SSZrr $xmm16, $rdi, implicit $mxcsr
4502 $xmm16 = VCVTSI642SSZrr $xmm16, $rdi, implicit $mxcsr
4503 ; CHECK: $xmm16 = VCVTSI642SSZrr_Int $xmm16, $rdi, implicit $mxcsr
4504 $xmm16 = VCVTSI642SSZrr_Int $xmm16, $rdi, implicit $mxcsr
4505 ; CHECK: $xmm16 = VCVTSS2SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4506 $xmm16 = VCVTSS2SDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4507 ; CHECK: $xmm16 = VCVTSS2SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4508 $xmm16 = VCVTSS2SDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4509 ; CHECK: $xmm16 = VCVTSS2SDZrr $xmm16, $xmm16, implicit $mxcsr
4510 $xmm16 = VCVTSS2SDZrr $xmm16, $xmm16, implicit $mxcsr
4511 ; CHECK: $xmm16 = VCVTSS2SDZrr_Int $xmm16, $xmm16, implicit $mxcsr
4512 $xmm16 = VCVTSS2SDZrr_Int $xmm16, $xmm16, implicit $mxcsr
4513 ; CHECK: $rdi = VCVTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4514 $rdi = VCVTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4515 ; CHECK: $rdi = VCVTSS2SI64Zrr_Int $xmm16, implicit $mxcsr
4516 $rdi = VCVTSS2SI64Zrr_Int $xmm16, implicit $mxcsr
4517 ; CHECK: $edi = VCVTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4518 $edi = VCVTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4519 ; CHECK: $edi = VCVTSS2SIZrr_Int $xmm16, implicit $mxcsr
4520 $edi = VCVTSS2SIZrr_Int $xmm16, implicit $mxcsr
4521 ; CHECK: $rdi = VCVTTSD2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4522 $rdi = VCVTTSD2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4523 ; CHECK: $rdi = VCVTTSD2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4524 $rdi = VCVTTSD2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4525 ; CHECK: $rdi = VCVTTSD2SI64Zrr $xmm16, implicit $mxcsr
4526 $rdi = VCVTTSD2SI64Zrr $xmm16, implicit $mxcsr
4527 ; CHECK: $rdi = VCVTTSD2SI64Zrr_Int $xmm16, implicit $mxcsr
4528 $rdi = VCVTTSD2SI64Zrr_Int $xmm16, implicit $mxcsr
4529 ; CHECK: $edi = VCVTTSD2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4530 $edi = VCVTTSD2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4531 ; CHECK: $edi = VCVTTSD2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4532 $edi = VCVTTSD2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4533 ; CHECK: $edi = VCVTTSD2SIZrr $xmm16, implicit $mxcsr
4534 $edi = VCVTTSD2SIZrr $xmm16, implicit $mxcsr
4535 ; CHECK: $edi = VCVTTSD2SIZrr_Int $xmm16, implicit $mxcsr
4536 $edi = VCVTTSD2SIZrr_Int $xmm16, implicit $mxcsr
4537 ; CHECK: $rdi = VCVTTSS2SI64rm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4538 $rdi = VCVTTSS2SI64Zrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4539 ; CHECK: $rdi = VCVTTSS2SI64rm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4540 $rdi = VCVTTSS2SI64Zrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4541 ; CHECK: $rdi = VCVTTSS2SI64Zrr $xmm16, implicit $mxcsr
4542 $rdi = VCVTTSS2SI64Zrr $xmm16, implicit $mxcsr
4543 ; CHECK: $rdi = VCVTTSS2SI64Zrr_Int $xmm16, implicit $mxcsr
4544 $rdi = VCVTTSS2SI64Zrr_Int $xmm16, implicit $mxcsr
4545 ; CHECK: $edi = VCVTTSS2SIrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4546 $edi = VCVTTSS2SIZrm $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4547 ; CHECK: $edi = VCVTTSS2SIrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4548 $edi = VCVTTSS2SIZrm_Int $rdi, 1, $noreg, 0, $noreg, implicit $mxcsr
4549 ; CHECK: $edi = VCVTTSS2SIZrr $xmm16, implicit $mxcsr
4550 $edi = VCVTTSS2SIZrr $xmm16, implicit $mxcsr
4551 ; CHECK: $edi = VCVTTSS2SIZrr_Int $xmm16, implicit $mxcsr
4552 $edi = VCVTTSS2SIZrr_Int $xmm16, implicit $mxcsr
4553 ; CHECK: $xmm16 = VMOV64toSDZrr $rdi
4554 $xmm16 = VMOV64toSDZrr $rdi
4555 ; CHECK: $xmm16 = VMOVDI2SSZrr $eax
4556 $xmm16 = VMOVDI2SSZrr $eax
4557 ; CHECK: VMOVSDZmr $rdi, 1, $noreg, 0, $noreg, $xmm16
4558 VMOVSDZmr $rdi, 1, $noreg, 0, $noreg, $xmm16
4559 ; CHECK: $xmm16 = VMOVSDZrm $rip, 1, $noreg, 0, $noreg
4560 $xmm16 = VMOVSDZrm $rip, 1, $noreg, 0, $noreg
4561 ; CHECK: $xmm16 = VMOVSDZrm_alt $rip, 1, $noreg, 0, $noreg
4562 $xmm16 = VMOVSDZrm_alt $rip, 1, $noreg, 0, $noreg
4563 ; CHECK: $xmm16 = VMOVSDZrr $xmm16, $xmm1
4564 $xmm16 = VMOVSDZrr $xmm16, $xmm1
4565 ; CHECK: $rax = VMOVSDto64Zrr $xmm16
4566 $rax = VMOVSDto64Zrr $xmm16
4567 ; CHECK: VMOVSSZmr $rdi, 1, $noreg, 0, $noreg, $xmm16
4568 VMOVSSZmr $rdi, 1, $noreg, 0, $noreg, $xmm16
4569 ; CHECK: $xmm16 = VMOVSSZrm $rip, 1, $noreg, 0, $noreg
4570 $xmm16 = VMOVSSZrm $rip, 1, $noreg, 0, $noreg
4571 ; CHECK: $xmm16 = VMOVSSZrm_alt $rip, 1, $noreg, 0, $noreg
4572 $xmm16 = VMOVSSZrm_alt $rip, 1, $noreg, 0, $noreg
4573 ; CHECK: $xmm16 = VMOVSSZrr $xmm16, $xmm1
4574 $xmm16 = VMOVSSZrr $xmm16, $xmm1
4575 ; CHECK: $eax = VMOVSS2DIZrr $xmm16
4576 $eax = VMOVSS2DIZrr $xmm16
4577 ; CHECK: $xmm16 = VMOV64toPQIZrr $rdi
4578 $xmm16 = VMOV64toPQIZrr $rdi
4579 ; CHECK: $xmm16 = VMOV64toPQIZrm $rdi, 1, $noreg, 0, $noreg
4580 $xmm16 = VMOV64toPQIZrm $rdi, 1, $noreg, 0, $noreg
4581 ; CHECK: $xmm16 = VMOV64toSDZrr $rdi
4582 $xmm16 = VMOV64toSDZrr $rdi
4583 ; CHECK: $xmm16 = VMOVDI2PDIZrm $rip, 1, $noreg, 0, $noreg
4584 $xmm16 = VMOVDI2PDIZrm $rip, 1, $noreg, 0, $noreg
4585 ; CHECK: $xmm16 = VMOVDI2PDIZrr $edi
4586 $xmm16 = VMOVDI2PDIZrr $edi
4587 ; CHECK: $xmm16 = VMOVLHPSZrr $xmm16, $xmm1
4588 $xmm16 = VMOVLHPSZrr $xmm16, $xmm1
4589 ; CHECK: $xmm16 = VMOVHLPSZrr $xmm16, $xmm1
4590 $xmm16 = VMOVHLPSZrr $xmm16, $xmm1
4591 ; CHECK: VMOVPDI2DIZmr $rdi, 1, $noreg, 0, $noreg, $xmm16
4592 VMOVPDI2DIZmr $rdi, 1, $noreg, 0, $noreg, $xmm16
4593 ; CHECK: $edi = VMOVPDI2DIZrr $xmm16
4594 $edi = VMOVPDI2DIZrr $xmm16
4595 ; CHECK: $xmm16 = VMOVPQI2QIZrr $xmm16
4596 $xmm16 = VMOVPQI2QIZrr $xmm16
4597 ; CHECK: VMOVPQI2QIZmr $rdi, 1, $noreg, 0, $noreg, $xmm16
4598 VMOVPQI2QIZmr $rdi, 1, $noreg, 0, $noreg, $xmm16
4599 ; CHECK: $rdi = VMOVPQIto64Zrr $xmm16
4600 $rdi = VMOVPQIto64Zrr $xmm16
4601 ; CHECK: VMOVPQIto64Zmr $rdi, 1, $noreg, 0, $noreg, $xmm16
4602 VMOVPQIto64Zmr $rdi, 1, $noreg, 0, $noreg, $xmm16
4603 ; CHECK: $xmm16 = VMOVQI2PQIZrm $rip, 1, $noreg, 0, $noreg
4604 $xmm16 = VMOVQI2PQIZrm $rip, 1, $noreg, 0, $noreg
4605 ; CHECK: $xmm16 = VMOVZPQILo2PQIZrr $xmm16
4606 $xmm16 = VMOVZPQILo2PQIZrr $xmm16
4607 ; CHECK: VCOMISDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4608 VCOMISDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4609 ; CHECK: VCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4610 VCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4611 ; CHECK: VCOMISSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4612 VCOMISSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4613 ; CHECK: VCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4614 VCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4615 ; CHECK: VUCOMISDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4616 VUCOMISDZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4617 ; CHECK: VUCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4618 VUCOMISDZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4619 ; CHECK: VUCOMISSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4620 VUCOMISSZrm_Int $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4621 ; CHECK: VUCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4622 VUCOMISSZrr_Int $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4623 ; CHECK: VCOMISDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4624 VCOMISDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4625 ; CHECK: VCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4626 VCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4627 ; CHECK: VCOMISSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4628 VCOMISSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4629 ; CHECK: VCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4630 VCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4631 ; CHECK: VUCOMISDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4632 VUCOMISDZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4633 ; CHECK: VUCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4634 VUCOMISDZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4635 ; CHECK: VUCOMISSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4636 VUCOMISSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
4637 ; CHECK: VUCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4638 VUCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4639 ; CHECK: $xmm16 = VRNDSCALESDZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4640 $xmm16 = VRNDSCALESDZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4641 ; CHECK: $xmm16 = VRNDSCALESDZr $xmm16, $xmm1, 15, implicit $mxcsr
4642 $xmm16 = VRNDSCALESDZr $xmm16, $xmm1, 15, implicit $mxcsr
4643 ; CHECK: $xmm16 = VRNDSCALESSZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4644 $xmm16 = VRNDSCALESSZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4645 ; CHECK: $xmm16 = VRNDSCALESSZr $xmm16, $xmm1, 15, implicit $mxcsr
4646 $xmm16 = VRNDSCALESSZr $xmm16, $xmm1, 15, implicit $mxcsr
4647 ; CHECK: $xmm16 = VRNDSCALESDZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4648 $xmm16 = VRNDSCALESDZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4649 ; CHECK: $xmm16 = VRNDSCALESDZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4650 $xmm16 = VRNDSCALESDZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4651 ; CHECK: $xmm16 = VRNDSCALESSZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4652 $xmm16 = VRNDSCALESSZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4653 ; CHECK: $xmm16 = VRNDSCALESSZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4654 $xmm16 = VRNDSCALESSZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4655 ; CHECK: $xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4656 $xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4657 ; CHECK: $xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 31, implicit $mxcsr
4658 $xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 31, implicit $mxcsr
4659 ; CHECK: $xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4660 $xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4661 ; CHECK: $xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 31, implicit $mxcsr
4662 $xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 31, implicit $mxcsr
4663 ; CHECK: $xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4664 $xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4665 ; CHECK: $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4666 $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4667 ; CHECK: $xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4668 $xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4669 ; CHECK: $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4670 $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4672 RET64
4673 ...