1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X86
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X64,X64-AVX1
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,X64,X64-AVX2
6 define <2 x double> @signbits_sext_v2i64_sitofp_v2f64(i32 %a0, i32 %a1) nounwind {
7 ; X86-LABEL: signbits_sext_v2i64_sitofp_v2f64:
9 ; X86-NEXT: vcvtdq2pd {{[0-9]+}}(%esp), %xmm0
12 ; X64-LABEL: signbits_sext_v2i64_sitofp_v2f64:
14 ; X64-NEXT: vmovd %edi, %xmm0
15 ; X64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
16 ; X64-NEXT: vcvtdq2pd %xmm0, %xmm0
18 %1 = sext i32 %a0 to i64
19 %2 = sext i32 %a1 to i64
20 %3 = insertelement <2 x i64> undef, i64 %1, i32 0
21 %4 = insertelement <2 x i64> %3, i64 %2, i32 1
22 %5 = sitofp <2 x i64> %4 to <2 x double>
26 define <4 x float> @signbits_sext_v4i64_sitofp_v4f32(i8 signext %a0, i16 signext %a1, i32 %a2, i32 %a3) nounwind {
27 ; X86-LABEL: signbits_sext_v4i64_sitofp_v4f32:
29 ; X86-NEXT: movswl {{[0-9]+}}(%esp), %eax
30 ; X86-NEXT: movsbl {{[0-9]+}}(%esp), %ecx
31 ; X86-NEXT: vmovd %ecx, %xmm0
32 ; X86-NEXT: vpinsrd $1, %eax, %xmm0, %xmm0
33 ; X86-NEXT: vpinsrd $2, {{[0-9]+}}(%esp), %xmm0, %xmm0
34 ; X86-NEXT: vpinsrd $3, {{[0-9]+}}(%esp), %xmm0, %xmm0
35 ; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
38 ; X64-LABEL: signbits_sext_v4i64_sitofp_v4f32:
40 ; X64-NEXT: vmovd %edi, %xmm0
41 ; X64-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
42 ; X64-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
43 ; X64-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
44 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
46 %1 = sext i8 %a0 to i64
47 %2 = sext i16 %a1 to i64
48 %3 = sext i32 %a2 to i64
49 %4 = sext i32 %a3 to i64
50 %5 = insertelement <4 x i64> undef, i64 %1, i32 0
51 %6 = insertelement <4 x i64> %5, i64 %2, i32 1
52 %7 = insertelement <4 x i64> %6, i64 %3, i32 2
53 %8 = insertelement <4 x i64> %7, i64 %4, i32 3
54 %9 = sitofp <4 x i64> %8 to <4 x float>
58 define <4 x double> @signbits_ashr_sitofp_0(<4 x i64> %a0) nounwind {
59 ; X86-LABEL: signbits_ashr_sitofp_0:
61 ; X86-NEXT: vextractf128 $1, %ymm0, %xmm1
62 ; X86-NEXT: vpsrlq $36, %xmm1, %xmm2
63 ; X86-NEXT: vpsrlq $35, %xmm1, %xmm1
64 ; X86-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
65 ; X86-NEXT: vmovdqa {{.*#+}} xmm2 = [268435456,0,134217728,0]
66 ; X86-NEXT: vpxor %xmm2, %xmm1, %xmm1
67 ; X86-NEXT: vpsubq %xmm2, %xmm1, %xmm1
68 ; X86-NEXT: vpsrlq $34, %xmm0, %xmm2
69 ; X86-NEXT: vpsrlq $33, %xmm0, %xmm0
70 ; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
71 ; X86-NEXT: vmovdqa {{.*#+}} xmm2 = [1073741824,0,536870912,0]
72 ; X86-NEXT: vpxor %xmm2, %xmm0, %xmm0
73 ; X86-NEXT: vpsubq %xmm2, %xmm0, %xmm0
74 ; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
75 ; X86-NEXT: vcvtdq2pd %xmm0, %ymm0
78 ; X64-AVX1-LABEL: signbits_ashr_sitofp_0:
80 ; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
81 ; X64-AVX1-NEXT: vpsrlq $36, %xmm1, %xmm2
82 ; X64-AVX1-NEXT: vpsrlq $35, %xmm1, %xmm1
83 ; X64-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7]
84 ; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [268435456,134217728]
85 ; X64-AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm1
86 ; X64-AVX1-NEXT: vpsubq %xmm2, %xmm1, %xmm1
87 ; X64-AVX1-NEXT: vpsrlq $34, %xmm0, %xmm2
88 ; X64-AVX1-NEXT: vpsrlq $33, %xmm0, %xmm0
89 ; X64-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
90 ; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [1073741824,536870912]
91 ; X64-AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0
92 ; X64-AVX1-NEXT: vpsubq %xmm2, %xmm0, %xmm0
93 ; X64-AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
94 ; X64-AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
97 ; X64-AVX2-LABEL: signbits_ashr_sitofp_0:
99 ; X64-AVX2-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
100 ; X64-AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [1073741824,536870912,268435456,134217728]
101 ; X64-AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
102 ; X64-AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
103 ; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
104 ; X64-AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
105 ; X64-AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
106 ; X64-AVX2-NEXT: retq
107 %1 = ashr <4 x i64> %a0, <i64 33, i64 34, i64 35, i64 36>
108 %2 = sitofp <4 x i64> %1 to <4 x double>
113 define <4 x float> @signbits_ashr_sitofp_1(<4 x i64> %a0) nounwind {
114 ; X86-LABEL: signbits_ashr_sitofp_1:
116 ; X86-NEXT: vextractf128 $1, %ymm0, %xmm1
117 ; X86-NEXT: vpsrad $16, %xmm1, %xmm1
118 ; X86-NEXT: vpsrad $16, %xmm0, %xmm0
119 ; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
120 ; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
121 ; X86-NEXT: vzeroupper
124 ; X64-AVX1-LABEL: signbits_ashr_sitofp_1:
126 ; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
127 ; X64-AVX1-NEXT: vpsrad $16, %xmm1, %xmm1
128 ; X64-AVX1-NEXT: vpsrad $16, %xmm0, %xmm0
129 ; X64-AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
130 ; X64-AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
131 ; X64-AVX1-NEXT: vzeroupper
132 ; X64-AVX1-NEXT: retq
134 ; X64-AVX2-LABEL: signbits_ashr_sitofp_1:
136 ; X64-AVX2-NEXT: vpsrad $16, %ymm0, %ymm0
137 ; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
138 ; X64-AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[1,3]
139 ; X64-AVX2-NEXT: vcvtdq2ps %xmm0, %xmm0
140 ; X64-AVX2-NEXT: vzeroupper
141 ; X64-AVX2-NEXT: retq
142 %1 = ashr <4 x i64> %a0, <i64 48, i64 48, i64 48, i64 48>
143 %2 = sitofp <4 x i64> %1 to <4 x float>
147 define float @signbits_ashr_extract_sitofp_0(<2 x i64> %a0) nounwind {
148 ; X86-LABEL: signbits_ashr_extract_sitofp_0:
150 ; X86-NEXT: pushl %eax
151 ; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
152 ; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
153 ; X86-NEXT: vmovss %xmm0, (%esp)
154 ; X86-NEXT: flds (%esp)
155 ; X86-NEXT: popl %eax
158 ; X64-LABEL: signbits_ashr_extract_sitofp_0:
160 ; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
161 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
163 %1 = ashr <2 x i64> %a0, <i64 32, i64 32>
164 %2 = extractelement <2 x i64> %1, i32 0
165 %3 = sitofp i64 %2 to float
169 define float @signbits_ashr_extract_sitofp_1(<2 x i64> %a0) nounwind {
170 ; X86-LABEL: signbits_ashr_extract_sitofp_1:
172 ; X86-NEXT: pushl %eax
173 ; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
174 ; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
175 ; X86-NEXT: vmovss %xmm0, (%esp)
176 ; X86-NEXT: flds (%esp)
177 ; X86-NEXT: popl %eax
180 ; X64-LABEL: signbits_ashr_extract_sitofp_1:
182 ; X64-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
183 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
185 %1 = ashr <2 x i64> %a0, <i64 32, i64 63>
186 %2 = extractelement <2 x i64> %1, i32 0
187 %3 = sitofp i64 %2 to float
191 define float @signbits_ashr_shl_extract_sitofp(<2 x i64> %a0) nounwind {
192 ; X86-LABEL: signbits_ashr_shl_extract_sitofp:
194 ; X86-NEXT: pushl %eax
195 ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
196 ; X86-NEXT: vpsrad $29, %xmm0, %xmm0
197 ; X86-NEXT: vpsllq $20, %xmm0, %xmm0
198 ; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
199 ; X86-NEXT: vmovss %xmm0, (%esp)
200 ; X86-NEXT: flds (%esp)
201 ; X86-NEXT: popl %eax
204 ; X64-LABEL: signbits_ashr_shl_extract_sitofp:
206 ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
207 ; X64-NEXT: vpsrad $29, %xmm0, %xmm0
208 ; X64-NEXT: vpsllq $20, %xmm0, %xmm0
209 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
211 %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
212 %2 = shl <2 x i64> %1, <i64 20, i64 16>
213 %3 = extractelement <2 x i64> %2, i32 0
214 %4 = sitofp i64 %3 to float
218 define float @signbits_ashr_insert_ashr_extract_sitofp(i64 %a0, i64 %a1) nounwind {
219 ; X86-LABEL: signbits_ashr_insert_ashr_extract_sitofp:
221 ; X86-NEXT: pushl %eax
222 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
223 ; X86-NEXT: movl %eax, %ecx
224 ; X86-NEXT: sarl $30, %ecx
225 ; X86-NEXT: shll $2, %eax
226 ; X86-NEXT: vmovd %eax, %xmm0
227 ; X86-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
228 ; X86-NEXT: vpsrlq $3, %xmm0, %xmm0
229 ; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
230 ; X86-NEXT: vmovss %xmm0, (%esp)
231 ; X86-NEXT: flds (%esp)
232 ; X86-NEXT: popl %eax
235 ; X64-LABEL: signbits_ashr_insert_ashr_extract_sitofp:
237 ; X64-NEXT: sarq $30, %rdi
238 ; X64-NEXT: vmovq %rdi, %xmm0
239 ; X64-NEXT: vpsrlq $3, %xmm0, %xmm0
240 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
242 %1 = ashr i64 %a0, 30
243 %2 = insertelement <2 x i64> undef, i64 %1, i32 0
244 %3 = insertelement <2 x i64> %2, i64 %a1, i32 1
245 %4 = ashr <2 x i64> %3, <i64 3, i64 3>
246 %5 = extractelement <2 x i64> %4, i32 0
247 %6 = sitofp i64 %5 to float
251 define <4 x double> @signbits_sext_shuffle_sitofp(<4 x i32> %a0, <4 x i64> %a1) nounwind {
252 ; X86-LABEL: signbits_sext_shuffle_sitofp:
254 ; X86-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero
255 ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
256 ; X86-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
257 ; X86-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[1,0,3,2]
258 ; X86-NEXT: vextractf128 $1, %ymm0, %xmm1
259 ; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
260 ; X86-NEXT: vcvtdq2pd %xmm0, %ymm0
263 ; X64-AVX1-LABEL: signbits_sext_shuffle_sitofp:
265 ; X64-AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero
266 ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
267 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
268 ; X64-AVX1-NEXT: vshufpd {{.*#+}} ymm0 = ymm0[1,0,3,2]
269 ; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
270 ; X64-AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
271 ; X64-AVX1-NEXT: vcvtdq2pd %xmm0, %ymm0
272 ; X64-AVX1-NEXT: retq
274 ; X64-AVX2-LABEL: signbits_sext_shuffle_sitofp:
276 ; X64-AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
277 ; X64-AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[3,2,1,0]
278 ; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
279 ; X64-AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
280 ; X64-AVX2-NEXT: vcvtdq2pd %xmm0, %ymm0
281 ; X64-AVX2-NEXT: retq
282 %1 = sext <4 x i32> %a0 to <4 x i64>
283 %2 = shufflevector <4 x i64> %1, <4 x i64>%a1, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
284 %3 = sitofp <4 x i64> %2 to <4 x double>
288 define <2 x double> @signbits_sext_shl_sitofp(<2 x i16> %a0) nounwind {
289 ; X86-LABEL: signbits_sext_shl_sitofp:
291 ; X86-NEXT: vpmovsxwq %xmm0, %xmm0
292 ; X86-NEXT: vpsllq $5, %xmm0, %xmm1
293 ; X86-NEXT: vpsllq $11, %xmm0, %xmm0
294 ; X86-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
295 ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
296 ; X86-NEXT: vcvtdq2pd %xmm0, %xmm0
299 ; X64-AVX1-LABEL: signbits_sext_shl_sitofp:
301 ; X64-AVX1-NEXT: vpmovsxwq %xmm0, %xmm0
302 ; X64-AVX1-NEXT: vpsllq $5, %xmm0, %xmm1
303 ; X64-AVX1-NEXT: vpsllq $11, %xmm0, %xmm0
304 ; X64-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
305 ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
306 ; X64-AVX1-NEXT: vcvtdq2pd %xmm0, %xmm0
307 ; X64-AVX1-NEXT: retq
309 ; X64-AVX2-LABEL: signbits_sext_shl_sitofp:
311 ; X64-AVX2-NEXT: vpmovsxwq %xmm0, %xmm0
312 ; X64-AVX2-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
313 ; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
314 ; X64-AVX2-NEXT: vcvtdq2pd %xmm0, %xmm0
315 ; X64-AVX2-NEXT: retq
316 %1 = sext <2 x i16> %a0 to <2 x i64>
317 %2 = shl <2 x i64> %1, <i64 11, i64 5>
318 %3 = sitofp <2 x i64> %2 to <2 x double>
322 define <2 x double> @signbits_ashr_concat_ashr_extract_sitofp(<2 x i64> %a0, <4 x i64> %a1) nounwind {
323 ; CHECK-LABEL: signbits_ashr_concat_ashr_extract_sitofp:
325 ; CHECK-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,3,2,3]
326 ; CHECK-NEXT: vcvtdq2pd %xmm0, %xmm0
327 ; CHECK-NEXT: ret{{[l|q]}}
328 %1 = ashr <2 x i64> %a0, <i64 16, i64 16>
329 %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
330 %3 = shufflevector <4 x i64> %a1, <4 x i64> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
331 %4 = ashr <4 x i64> %3, <i64 16, i64 16, i64 16, i64 16>
332 %5 = shufflevector <4 x i64> %4, <4 x i64> undef, <2 x i32> <i32 2, i32 3>
333 %6 = sitofp <2 x i64> %5 to <2 x double>
337 define float @signbits_ashr_sext_sextinreg_and_extract_sitofp(<2 x i64> %a0, <2 x i64> %a1, i32 %a2) nounwind {
338 ; X86-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp:
340 ; X86-NEXT: pushl %eax
341 ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
342 ; X86-NEXT: vpsrad $29, %xmm0, %xmm0
343 ; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
344 ; X86-NEXT: vpand %xmm0, %xmm1, %xmm0
345 ; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
346 ; X86-NEXT: vmovss %xmm0, (%esp)
347 ; X86-NEXT: flds (%esp)
348 ; X86-NEXT: popl %eax
351 ; X64-LABEL: signbits_ashr_sext_sextinreg_and_extract_sitofp:
353 ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
354 ; X64-NEXT: vpsrad $29, %xmm0, %xmm0
355 ; X64-NEXT: vmovd %edi, %xmm1
356 ; X64-NEXT: vpand %xmm1, %xmm0, %xmm0
357 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
359 %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
360 %2 = sext i32 %a2 to i64
361 %3 = insertelement <2 x i64> %a1, i64 %2, i32 0
362 %4 = shl <2 x i64> %3, <i64 20, i64 20>
363 %5 = ashr <2 x i64> %4, <i64 20, i64 20>
364 %6 = and <2 x i64> %1, %5
365 %7 = extractelement <2 x i64> %6, i32 0
366 %8 = sitofp i64 %7 to float
370 define float @signbits_ashr_sextvecinreg_bitops_extract_sitofp(<2 x i64> %a0, <4 x i32> %a1) nounwind {
371 ; X86-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
373 ; X86-NEXT: pushl %eax
374 ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
375 ; X86-NEXT: vpsrad $29, %xmm0, %xmm0
376 ; X86-NEXT: vpxor %xmm0, %xmm1, %xmm0
377 ; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
378 ; X86-NEXT: vmovss %xmm0, (%esp)
379 ; X86-NEXT: flds (%esp)
380 ; X86-NEXT: popl %eax
383 ; X64-LABEL: signbits_ashr_sextvecinreg_bitops_extract_sitofp:
385 ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
386 ; X64-NEXT: vpsrad $29, %xmm0, %xmm0
387 ; X64-NEXT: vpxor %xmm0, %xmm1, %xmm0
388 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
390 %1 = ashr <2 x i64> %a0, <i64 61, i64 60>
391 %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
392 %3 = sext <2 x i32> %2 to <2 x i64>
393 %4 = and <2 x i64> %1, %3
394 %5 = or <2 x i64> %4, %3
395 %6 = xor <2 x i64> %5, %1
396 %7 = extractelement <2 x i64> %6, i32 0
397 %8 = sitofp i64 %7 to float
401 define <4 x float> @signbits_ashr_sext_select_shuffle_sitofp(<4 x i64> %a0, <4 x i64> %a1, <4 x i64> %a2, <4 x i32> %a3) nounwind {
402 ; X86-LABEL: signbits_ashr_sext_select_shuffle_sitofp:
404 ; X86-NEXT: pushl %ebp
405 ; X86-NEXT: movl %esp, %ebp
406 ; X86-NEXT: andl $-16, %esp
407 ; X86-NEXT: subl $16, %esp
408 ; X86-NEXT: vmovapd 8(%ebp), %xmm3
409 ; X86-NEXT: vpsrad $31, %xmm2, %xmm4
410 ; X86-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[1,1,3,3]
411 ; X86-NEXT: vpsrad $1, %xmm5, %xmm5
412 ; X86-NEXT: vpblendw {{.*#+}} xmm4 = xmm5[0,1],xmm4[2,3],xmm5[4,5],xmm4[6,7]
413 ; X86-NEXT: vextractf128 $1, %ymm2, %xmm2
414 ; X86-NEXT: vpsrad $31, %xmm2, %xmm5
415 ; X86-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
416 ; X86-NEXT: vpsrad $1, %xmm2, %xmm2
417 ; X86-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm5[2,3],xmm2[4,5],xmm5[6,7]
418 ; X86-NEXT: vshufps {{.*#+}} xmm5 = xmm3[2,2,3,3]
419 ; X86-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm6
420 ; X86-NEXT: vextractf128 $1, %ymm1, %xmm1
421 ; X86-NEXT: vextractf128 $1, %ymm0, %xmm0
422 ; X86-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
423 ; X86-NEXT: vblendvpd %xmm0, %xmm2, %xmm5, %xmm0
424 ; X86-NEXT: vblendvpd %xmm6, %xmm4, %xmm3, %xmm1
425 ; X86-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
426 ; X86-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
427 ; X86-NEXT: vextractf128 $1, %ymm0, %xmm1
428 ; X86-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
429 ; X86-NEXT: vcvtdq2ps %xmm0, %xmm0
430 ; X86-NEXT: movl %ebp, %esp
431 ; X86-NEXT: popl %ebp
432 ; X86-NEXT: vzeroupper
435 ; X64-AVX1-LABEL: signbits_ashr_sext_select_shuffle_sitofp:
437 ; X64-AVX1-NEXT: vpsrad $31, %xmm2, %xmm4
438 ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[1,1,3,3]
439 ; X64-AVX1-NEXT: vpsrad $1, %xmm5, %xmm5
440 ; X64-AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm5[0,1],xmm4[2,3],xmm5[4,5],xmm4[6,7]
441 ; X64-AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
442 ; X64-AVX1-NEXT: vpsrad $31, %xmm2, %xmm5
443 ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
444 ; X64-AVX1-NEXT: vpsrad $1, %xmm2, %xmm2
445 ; X64-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0,1],xmm5[2,3],xmm2[4,5],xmm5[6,7]
446 ; X64-AVX1-NEXT: vshufps {{.*#+}} xmm5 = xmm3[2,2,3,3]
447 ; X64-AVX1-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm6
448 ; X64-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
449 ; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
450 ; X64-AVX1-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
451 ; X64-AVX1-NEXT: vblendvpd %xmm0, %xmm2, %xmm5, %xmm0
452 ; X64-AVX1-NEXT: vblendvpd %xmm6, %xmm4, %xmm3, %xmm1
453 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
454 ; X64-AVX1-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2]
455 ; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
456 ; X64-AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
457 ; X64-AVX1-NEXT: vcvtdq2ps %xmm0, %xmm0
458 ; X64-AVX1-NEXT: vzeroupper
459 ; X64-AVX1-NEXT: retq
461 ; X64-AVX2-LABEL: signbits_ashr_sext_select_shuffle_sitofp:
463 ; X64-AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[1,1,3,3,5,5,7,7]
464 ; X64-AVX2-NEXT: vpsrad $1, %ymm2, %ymm2
465 ; X64-AVX2-NEXT: vpmovzxdq {{.*#+}} ymm3 = xmm3[0],zero,xmm3[1],zero,xmm3[2],zero,xmm3[3],zero
466 ; X64-AVX2-NEXT: vpcmpeqq %ymm1, %ymm0, %ymm0
467 ; X64-AVX2-NEXT: vblendvpd %ymm0, %ymm2, %ymm3, %ymm0
468 ; X64-AVX2-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,1,0,1,4,5,4,5]
469 ; X64-AVX2-NEXT: vextractf128 $1, %ymm0, %xmm1
470 ; X64-AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
471 ; X64-AVX2-NEXT: vcvtdq2ps %xmm0, %xmm0
472 ; X64-AVX2-NEXT: vzeroupper
473 ; X64-AVX2-NEXT: retq
474 %1 = ashr <4 x i64> %a2, <i64 33, i64 63, i64 33, i64 63>
475 %2 = sext <4 x i32> %a3 to <4 x i64>
476 %3 = icmp eq <4 x i64> %a0, %a1
477 %4 = select <4 x i1> %3, <4 x i64> %1, <4 x i64> %2
478 %5 = shufflevector <4 x i64> %4, <4 x i64> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
479 %6 = sitofp <4 x i64> %5 to <4 x float>
483 define <4 x i32> @signbits_mask_ashr_smax(<4 x i32> %a0, <4 x i32> %a1) {
484 ; X86-LABEL: signbits_mask_ashr_smax:
486 ; X86-NEXT: vpand %xmm1, %xmm0, %xmm0
487 ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
488 ; X86-NEXT: vpsrad $25, %xmm0, %xmm0
489 ; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
492 ; X64-AVX1-LABEL: signbits_mask_ashr_smax:
494 ; X64-AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
495 ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
496 ; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0
497 ; X64-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
498 ; X64-AVX1-NEXT: retq
500 ; X64-AVX2-LABEL: signbits_mask_ashr_smax:
502 ; X64-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
503 ; X64-AVX2-NEXT: vpsrad $25, %xmm0, %xmm0
504 ; X64-AVX2-NEXT: vpbroadcastd %xmm0, %xmm0
505 ; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
506 ; X64-AVX2-NEXT: retq
507 %1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 0>
508 %2 = ashr <4 x i32> %a1, <i32 25, i32 26, i32 27, i32 0>
509 %3 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %1, <4 x i32> %2)
510 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer
511 %5 = ashr <4 x i32> %4, <i32 1, i32 2, i32 3, i32 4>
512 %6 = and <4 x i32> %5, <i32 -32768, i32 -65536, i32 -32768, i32 -65536>
515 declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
517 define <4 x i32> @signbits_mask_ashr_smin(<4 x i32> %a0, <4 x i32> %a1) {
518 ; X86-LABEL: signbits_mask_ashr_smin:
520 ; X86-NEXT: vpor %xmm1, %xmm0, %xmm0
521 ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
522 ; X86-NEXT: vpsrad $25, %xmm0, %xmm0
523 ; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
526 ; X64-AVX1-LABEL: signbits_mask_ashr_smin:
528 ; X64-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
529 ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
530 ; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0
531 ; X64-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
532 ; X64-AVX1-NEXT: retq
534 ; X64-AVX2-LABEL: signbits_mask_ashr_smin:
536 ; X64-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
537 ; X64-AVX2-NEXT: vpsrad $25, %xmm0, %xmm0
538 ; X64-AVX2-NEXT: vpbroadcastd %xmm0, %xmm0
539 ; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
540 ; X64-AVX2-NEXT: retq
541 %1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 0>
542 %2 = ashr <4 x i32> %a1, <i32 25, i32 26, i32 27, i32 0>
543 %3 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %1, <4 x i32> %2)
544 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer
545 %5 = ashr <4 x i32> %4, <i32 1, i32 2, i32 3, i32 4>
546 %6 = and <4 x i32> %5, <i32 -32768, i32 -65536, i32 -32768, i32 -65536>
549 declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
551 define <4 x i32> @signbits_mask_ashr_umax(<4 x i32> %a0, <4 x i32> %a1) {
552 ; X86-LABEL: signbits_mask_ashr_umax:
554 ; X86-NEXT: vpor %xmm1, %xmm0, %xmm0
555 ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
556 ; X86-NEXT: vpsrad $25, %xmm0, %xmm0
557 ; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
560 ; X64-AVX1-LABEL: signbits_mask_ashr_umax:
562 ; X64-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
563 ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
564 ; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0
565 ; X64-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
566 ; X64-AVX1-NEXT: retq
568 ; X64-AVX2-LABEL: signbits_mask_ashr_umax:
570 ; X64-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
571 ; X64-AVX2-NEXT: vpsrad $25, %xmm0, %xmm0
572 ; X64-AVX2-NEXT: vpbroadcastd %xmm0, %xmm0
573 ; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
574 ; X64-AVX2-NEXT: retq
575 %1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 0>
576 %2 = ashr <4 x i32> %a1, <i32 25, i32 26, i32 27, i32 0>
577 %3 = call <4 x i32> @llvm.umax.v4i32(<4 x i32> %1, <4 x i32> %2)
578 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer
579 %5 = ashr <4 x i32> %4, <i32 1, i32 2, i32 3, i32 4>
580 %6 = and <4 x i32> %5, <i32 -32768, i32 -65536, i32 -32768, i32 -65536>
583 declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
585 define <4 x i32> @signbits_mask_ashr_umin(<4 x i32> %a0, <4 x i32> %a1) {
586 ; X86-LABEL: signbits_mask_ashr_umin:
588 ; X86-NEXT: vpand %xmm1, %xmm0, %xmm0
589 ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
590 ; X86-NEXT: vpsrad $25, %xmm0, %xmm0
591 ; X86-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
594 ; X64-AVX1-LABEL: signbits_mask_ashr_umin:
596 ; X64-AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
597 ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
598 ; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0
599 ; X64-AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
600 ; X64-AVX1-NEXT: retq
602 ; X64-AVX2-LABEL: signbits_mask_ashr_umin:
604 ; X64-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
605 ; X64-AVX2-NEXT: vpsrad $25, %xmm0, %xmm0
606 ; X64-AVX2-NEXT: vpbroadcastd %xmm0, %xmm0
607 ; X64-AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
608 ; X64-AVX2-NEXT: retq
609 %1 = ashr <4 x i32> %a0, <i32 25, i32 26, i32 27, i32 0>
610 %2 = ashr <4 x i32> %a1, <i32 25, i32 26, i32 27, i32 0>
611 %3 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %1, <4 x i32> %2)
612 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <4 x i32> zeroinitializer
613 %5 = ashr <4 x i32> %4, <i32 1, i32 2, i32 3, i32 4>
614 %6 = and <4 x i32> %5, <i32 -32768, i32 -65536, i32 -32768, i32 -65536>
617 declare <4 x i32> @llvm.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
619 define i32 @signbits_cmpss(float %0, float %1) {
620 ; X86-LABEL: signbits_cmpss:
622 ; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
623 ; X86-NEXT: vcmpeqss {{[0-9]+}}(%esp), %xmm0, %xmm0
624 ; X86-NEXT: vmovd %xmm0, %eax
627 ; X64-LABEL: signbits_cmpss:
629 ; X64-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0
630 ; X64-NEXT: vmovd %xmm0, %eax
632 %3 = fcmp oeq float %0, %1
633 %4 = sext i1 %3 to i32
637 define i32 @signbits_cmpss_int(<4 x float> %0, <4 x float> %1) {
638 ; CHECK-LABEL: signbits_cmpss_int:
640 ; CHECK-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0
641 ; CHECK-NEXT: vextractps $0, %xmm0, %eax
642 ; CHECK-NEXT: ret{{[l|q]}}
643 %3 = tail call <4 x float> @llvm.x86.sse.cmp.ss(<4 x float> %0, <4 x float> %1, i8 0)
644 %4 = bitcast <4 x float> %3 to <4 x i32>
645 %5 = extractelement <4 x i32> %4, i32 0
649 declare <4 x float> @llvm.x86.sse.cmp.ss(<4 x float>, <4 x float>, i8 immarg)
651 define i64 @signbits_cmpsd(double %0, double %1) {
652 ; X86-LABEL: signbits_cmpsd:
654 ; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
655 ; X86-NEXT: vcmpeqsd {{[0-9]+}}(%esp), %xmm0, %xmm0
656 ; X86-NEXT: vmovd %xmm0, %eax
657 ; X86-NEXT: andl $1, %eax
658 ; X86-NEXT: negl %eax
659 ; X86-NEXT: movl %eax, %edx
662 ; X64-LABEL: signbits_cmpsd:
664 ; X64-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0
665 ; X64-NEXT: vmovq %xmm0, %rax
667 %3 = fcmp oeq double %0, %1
668 %4 = sext i1 %3 to i64
672 define i64 @signbits_cmpsd_int(<2 x double> %0, <2 x double> %1) {
673 ; X86-LABEL: signbits_cmpsd_int:
675 ; X86-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0
676 ; X86-NEXT: vextractps $1, %xmm0, %eax
677 ; X86-NEXT: movl %eax, %edx
680 ; X64-LABEL: signbits_cmpsd_int:
682 ; X64-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0
683 ; X64-NEXT: vmovq %xmm0, %rax
685 %3 = tail call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %0, <2 x double> %1, i8 0)
686 %4 = bitcast <2 x double> %3 to <2 x i64>
687 %5 = extractelement <2 x i64> %4, i32 0
691 declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg)
693 ; Make sure we can preserve sign bit information into the second basic block
694 ; so we can avoid having to shift bit 0 into bit 7 for each element due to
695 ; v32i1->v32i8 promotion and the splitting of v32i8 into 2xv16i8. This requires
696 ; ComputeNumSignBits handling for insert_subvector.
697 define void @cross_bb_signbits_insert_subvec(ptr %ptr, <32 x i8> %x, <32 x i8> %z) {
698 ; X86-LABEL: cross_bb_signbits_insert_subvec:
700 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
701 ; X86-NEXT: vextractf128 $1, %ymm0, %xmm2
702 ; X86-NEXT: vpxor %xmm3, %xmm3, %xmm3
703 ; X86-NEXT: vpcmpeqb %xmm3, %xmm2, %xmm2
704 ; X86-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
705 ; X86-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
706 ; X86-NEXT: vandnps %ymm1, %ymm0, %ymm1
707 ; X86-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
708 ; X86-NEXT: vorps %ymm1, %ymm0, %ymm0
709 ; X86-NEXT: vmovaps %ymm0, (%eax)
710 ; X86-NEXT: vzeroupper
713 ; X64-AVX1-LABEL: cross_bb_signbits_insert_subvec:
715 ; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
716 ; X64-AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
717 ; X64-AVX1-NEXT: vpcmpeqb %xmm3, %xmm2, %xmm2
718 ; X64-AVX1-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
719 ; X64-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
720 ; X64-AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm1
721 ; X64-AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
722 ; X64-AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
723 ; X64-AVX1-NEXT: vmovaps %ymm0, (%rdi)
724 ; X64-AVX1-NEXT: vzeroupper
725 ; X64-AVX1-NEXT: retq
727 ; X64-AVX2-LABEL: cross_bb_signbits_insert_subvec:
729 ; X64-AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
730 ; X64-AVX2-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0
731 ; X64-AVX2-NEXT: vpblendvb %ymm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
732 ; X64-AVX2-NEXT: vmovdqa %ymm0, (%rdi)
733 ; X64-AVX2-NEXT: vzeroupper
734 ; X64-AVX2-NEXT: retq
735 %a = icmp eq <32 x i8> %x, zeroinitializer
736 %b = icmp eq <32 x i8> %x, zeroinitializer
737 %c = and <32 x i1> %a, %b
741 %d = select <32 x i1> %c, <32 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>, <32 x i8> %z
742 store <32 x i8> %d, ptr %ptr, align 32