1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-darwin | FileCheck %s
4 ;; X's live range extends beyond the shift, so the register allocator
5 ;; cannot coalesce it with Y. Because of this, a copy needs to be
6 ;; emitted before the shift to save the register value before it is
7 ;; clobbered. However, this copy is not needed if the register
8 ;; allocator turns the shift into an LEA. This also occurs for ADD.
10 ; Check that the shift gets turned into an LEA.
12 @G = external global i32
14 define i32 @test1(i32 %X) nounwind {
17 ; CHECK-NEXT: movl %edi, %eax
18 ; CHECK-NEXT: leal 1(%rax), %ecx
19 ; CHECK-NEXT: movq _G@GOTPCREL(%rip), %rdx
20 ; CHECK-NEXT: movl %ecx, (%rdx)
21 ; CHECK-NEXT: ## kill: def $eax killed $eax killed $rax
24 store volatile i32 %Z, ptr @G
29 ; The second add should not be transformed to leal nor should it be
30 ; commutted (which would require inserting a copy).
31 define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind {
33 ; CHECK: ## %bb.0: ## %entry
34 ; CHECK-NEXT: ## kill: def $ecx killed $ecx def $rcx
35 ; CHECK-NEXT: ## kill: def $edx killed $edx def $rdx
36 ; CHECK-NEXT: ## kill: def $esi killed $esi def $rsi
37 ; CHECK-NEXT: ## kill: def $edi killed $edi def $rdi
38 ; CHECK-NEXT: addl %edi, %esi
39 ; CHECK-NEXT: leal (%rdx,%rcx), %eax
40 ; CHECK-NEXT: addl %esi, %eax
44 %add3 = add i32 %add, %c
45 %add5 = add i32 %add3, %d
50 define i64 @test3(i64 %x) nounwind readnone ssp {
52 ; CHECK: ## %bb.0: ## %entry
53 ; CHECK-NEXT: leaq (%rdi,%rdi), %rax
60 @global = external global i32, align 4
61 @global2 = external global i64, align 8
63 ; Test that liveness is properly updated and we do not encounter the
64 ; assert/crash from http://llvm.org/PR28301
67 ; CHECK: ## %bb.0: ## %bb
68 ; CHECK-NEXT: xorl %ecx, %ecx
69 ; CHECK-NEXT: movq _global@GOTPCREL(%rip), %rdx
70 ; CHECK-NEXT: movq _global2@GOTPCREL(%rip), %rsi
71 ; CHECK-NEXT: xorl %eax, %eax
72 ; CHECK-NEXT: testb %cl, %cl
73 ; CHECK-NEXT: je LBB3_2
74 ; CHECK-NEXT: .p2align 4, 0x90
75 ; CHECK-NEXT: LBB3_6: ## %bb2
76 ; CHECK-NEXT: ## =>This Loop Header: Depth=1
77 ; CHECK-NEXT: ## Child Loop BB3_7 Depth 2
78 ; CHECK-NEXT: movl (%rdx), %edi
79 ; CHECK-NEXT: leal (%rdi,%rax), %r8d
80 ; CHECK-NEXT: movslq %r8d, %r8
81 ; CHECK-NEXT: .p2align 4, 0x90
82 ; CHECK-NEXT: LBB3_7: ## %bb6
83 ; CHECK-NEXT: ## Parent Loop BB3_6 Depth=1
84 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
85 ; CHECK-NEXT: movq %rax, (%rsi)
86 ; CHECK-NEXT: movq %r8, (%rsi)
87 ; CHECK-NEXT: movl %edi, (%rdx)
88 ; CHECK-NEXT: testb %cl, %cl
89 ; CHECK-NEXT: jne LBB3_7
90 ; CHECK-NEXT: ## %bb.8: ## %bb9
91 ; CHECK-NEXT: ## in Loop: Header=BB3_6 Depth=1
92 ; CHECK-NEXT: addq $4, %rax
93 ; CHECK-NEXT: testb %cl, %cl
94 ; CHECK-NEXT: jne LBB3_6
95 ; CHECK-NEXT: LBB3_2: ## %bb3.preheader
96 ; CHECK-NEXT: xorl %ecx, %ecx
97 ; CHECK-NEXT: .p2align 4, 0x90
98 ; CHECK-NEXT: LBB3_3: ## %bb3
99 ; CHECK-NEXT: ## =>This Loop Header: Depth=1
100 ; CHECK-NEXT: ## Child Loop BB3_4 Depth 2
101 ; CHECK-NEXT: movq %rcx, %rdx
102 ; CHECK-NEXT: addq $4, %rcx
103 ; CHECK-NEXT: movl %eax, %esi
104 ; CHECK-NEXT: subl %edx, %esi
105 ; CHECK-NEXT: .p2align 4, 0x90
106 ; CHECK-NEXT: LBB3_4: ## %bb4
107 ; CHECK-NEXT: ## Parent Loop BB3_3 Depth=1
108 ; CHECK-NEXT: ## => This Inner Loop Header: Depth=2
109 ; CHECK-NEXT: testl %esi, %esi
110 ; CHECK-NEXT: jne LBB3_9
111 ; CHECK-NEXT: ## %bb.5: ## %bb5
112 ; CHECK-NEXT: ## in Loop: Header=BB3_4 Depth=2
113 ; CHECK-NEXT: incq %rdx
114 ; CHECK-NEXT: cmpq %rcx, %rdx
115 ; CHECK-NEXT: jl LBB3_4
116 ; CHECK-NEXT: jmp LBB3_3
117 ; CHECK-NEXT: LBB3_9: ## %bb8
123 %tmp = phi i64 [ %tmp40, %bb9 ], [ 0, %bb ]
124 %tmp2 = phi i32 [ %tmp39, %bb9 ], [ 0, %bb ]
125 %tmp3 = icmp sgt i32 undef, 10
126 br i1 %tmp3, label %bb2, label %bb3
129 %tmp6 = load i32, ptr @global, align 4
130 %tmp8 = add nsw i32 %tmp6, %tmp2
131 %tmp9 = sext i32 %tmp8 to i64
135 %tmp14 = phi i64 [ %tmp15, %bb5 ], [ 0, %bb1 ]
136 %tmp15 = add nuw i64 %tmp14, 4
137 %tmp16 = trunc i64 %tmp14 to i32
138 %tmp17 = sub i32 %tmp2, %tmp16
142 %tmp20 = phi i64 [ %tmp14, %bb3 ], [ %tmp34, %bb5 ]
143 %tmp28 = icmp eq i32 %tmp17, 0
144 br i1 %tmp28, label %bb5, label %bb8
147 %tmp34 = add nuw nsw i64 %tmp20, 1
148 %tmp35 = icmp slt i64 %tmp34, %tmp15
149 br i1 %tmp35, label %bb4, label %bb3
152 store volatile i64 %tmp, ptr @global2, align 8
153 store volatile i64 %tmp9, ptr @global2, align 8
154 store volatile i32 %tmp6, ptr @global, align 4
155 %tmp45 = icmp slt i32 undef, undef
156 br i1 %tmp45, label %bb6, label %bb9
162 %tmp39 = add nuw nsw i32 %tmp2, 4
163 %tmp40 = add nuw i64 %tmp, 4