| blob | ffc929c1237cdf5504e7aa31074b722f1b46324f |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX12,AVX1
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX12,AVX2
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=CHECK,AVX,AVX512,AVX512F
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512vl | FileCheck %s --check-prefixes=CHECK,AVX,AVX512,AVX512VL
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=xop | FileCheck %s --check-prefixes=CHECK,XOP
8 ; The condition vector for BLENDV* only cares about the sign bit of each element.
9 ; So in these tests, if we generate BLENDV*, we should be able to remove the redundant cmp op.
11 ; Test 128-bit vectors for all legal element types.
13 define <16 x i8> @signbit_sel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %mask) {
14 ; CHECK-LABEL: signbit_sel_v16i8:
15 ; CHECK: # %bb.0:
16 ; CHECK-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
17 ; CHECK-NEXT: retq
18 %tr = icmp slt <16 x i8> %mask, zeroinitializer
19 %z = select <16 x i1> %tr, <16 x i8> %x, <16 x i8> %y
20 ret <16 x i8> %z
21 }
23 ; Sorry 16-bit, you're not important enough to support?
25 define <8 x i16> @signbit_sel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) {
26 ; AVX12-LABEL: signbit_sel_v8i16:
27 ; AVX12: # %bb.0:
28 ; AVX12-NEXT: vpxor %xmm3, %xmm3, %xmm3
29 ; AVX12-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2
30 ; AVX12-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
31 ; AVX12-NEXT: retq
32 ;
33 ; AVX512F-LABEL: signbit_sel_v8i16:
34 ; AVX512F: # %bb.0:
35 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
36 ; AVX512F-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2
37 ; AVX512F-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
38 ; AVX512F-NEXT: retq
39 ;
40 ; AVX512VL-LABEL: signbit_sel_v8i16:
41 ; AVX512VL: # %bb.0:
42 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
43 ; AVX512VL-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2
44 ; AVX512VL-NEXT: vpternlogq $226, %xmm1, %xmm2, %xmm0
45 ; AVX512VL-NEXT: retq
46 ;
47 ; XOP-LABEL: signbit_sel_v8i16:
48 ; XOP: # %bb.0:
49 ; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
50 ; XOP-NEXT: vpcomltw %xmm3, %xmm2, %xmm2
51 ; XOP-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm0
52 ; XOP-NEXT: retq
53 %tr = icmp slt <8 x i16> %mask, zeroinitializer
54 %z = select <8 x i1> %tr, <8 x i16> %x, <8 x i16> %y
55 ret <8 x i16> %z
56 }
58 define <4 x i32> @signbit_sel_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %mask) {
59 ; AVX12-LABEL: signbit_sel_v4i32:
60 ; AVX12: # %bb.0:
61 ; AVX12-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
62 ; AVX12-NEXT: retq
63 ;
64 ; AVX512F-LABEL: signbit_sel_v4i32:
65 ; AVX512F: # %bb.0:
66 ; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
67 ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
68 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
69 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
70 ; AVX512F-NEXT: vpcmpgtd %zmm2, %zmm3, %k1
71 ; AVX512F-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
72 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
73 ; AVX512F-NEXT: vzeroupper
74 ; AVX512F-NEXT: retq
75 ;
76 ; AVX512VL-LABEL: signbit_sel_v4i32:
77 ; AVX512VL: # %bb.0:
78 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
79 ; AVX512VL-NEXT: vpcmpgtd %xmm2, %xmm3, %k1
80 ; AVX512VL-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
81 ; AVX512VL-NEXT: retq
82 ;
83 ; XOP-LABEL: signbit_sel_v4i32:
84 ; XOP: # %bb.0:
85 ; XOP-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
86 ; XOP-NEXT: retq
87 %tr = icmp slt <4 x i32> %mask, zeroinitializer
88 %z = select <4 x i1> %tr, <4 x i32> %x, <4 x i32> %y
89 ret <4 x i32> %z
90 }
92 define <2 x i64> @signbit_sel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %mask) {
93 ; AVX12-LABEL: signbit_sel_v2i64:
94 ; AVX12: # %bb.0:
95 ; AVX12-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
96 ; AVX12-NEXT: retq
97 ;
98 ; AVX512F-LABEL: signbit_sel_v2i64:
99 ; AVX512F: # %bb.0:
100 ; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
101 ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
102 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
103 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
104 ; AVX512F-NEXT: vpcmpgtq %zmm2, %zmm3, %k1
105 ; AVX512F-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
106 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
107 ; AVX512F-NEXT: vzeroupper
108 ; AVX512F-NEXT: retq
109 ;
110 ; AVX512VL-LABEL: signbit_sel_v2i64:
111 ; AVX512VL: # %bb.0:
112 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
113 ; AVX512VL-NEXT: vpcmpgtq %xmm2, %xmm3, %k1
114 ; AVX512VL-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
115 ; AVX512VL-NEXT: retq
116 ;
117 ; XOP-LABEL: signbit_sel_v2i64:
118 ; XOP: # %bb.0:
119 ; XOP-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
120 ; XOP-NEXT: retq
121 %tr = icmp slt <2 x i64> %mask, zeroinitializer
122 %z = select <2 x i1> %tr, <2 x i64> %x, <2 x i64> %y
123 ret <2 x i64> %z
124 }
126 define <4 x float> @signbit_sel_v4f32(<4 x float> %x, <4 x float> %y, <4 x i32> %mask) {
127 ; AVX12-LABEL: signbit_sel_v4f32:
128 ; AVX12: # %bb.0:
129 ; AVX12-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
130 ; AVX12-NEXT: retq
131 ;
132 ; AVX512F-LABEL: signbit_sel_v4f32:
133 ; AVX512F: # %bb.0:
134 ; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
135 ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
136 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
137 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
138 ; AVX512F-NEXT: vpcmpgtd %zmm2, %zmm3, %k1
139 ; AVX512F-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1}
140 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
141 ; AVX512F-NEXT: vzeroupper
142 ; AVX512F-NEXT: retq
143 ;
144 ; AVX512VL-LABEL: signbit_sel_v4f32:
145 ; AVX512VL: # %bb.0:
146 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
147 ; AVX512VL-NEXT: vpcmpgtd %xmm2, %xmm3, %k1
148 ; AVX512VL-NEXT: vblendmps %xmm0, %xmm1, %xmm0 {%k1}
149 ; AVX512VL-NEXT: retq
150 ;
151 ; XOP-LABEL: signbit_sel_v4f32:
152 ; XOP: # %bb.0:
153 ; XOP-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
154 ; XOP-NEXT: retq
155 %tr = icmp slt <4 x i32> %mask, zeroinitializer
156 %z = select <4 x i1> %tr, <4 x float> %x, <4 x float> %y
157 ret <4 x float> %z
158 }
160 define <2 x double> @signbit_sel_v2f64(<2 x double> %x, <2 x double> %y, <2 x i64> %mask) {
161 ; AVX12-LABEL: signbit_sel_v2f64:
162 ; AVX12: # %bb.0:
163 ; AVX12-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
164 ; AVX12-NEXT: retq
165 ;
166 ; AVX512F-LABEL: signbit_sel_v2f64:
167 ; AVX512F: # %bb.0:
168 ; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
169 ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
170 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
171 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
172 ; AVX512F-NEXT: vpcmpgtq %zmm2, %zmm3, %k1
173 ; AVX512F-NEXT: vblendmpd %zmm0, %zmm1, %zmm0 {%k1}
174 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
175 ; AVX512F-NEXT: vzeroupper
176 ; AVX512F-NEXT: retq
177 ;
178 ; AVX512VL-LABEL: signbit_sel_v2f64:
179 ; AVX512VL: # %bb.0:
180 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
181 ; AVX512VL-NEXT: vpcmpgtq %xmm2, %xmm3, %k1
182 ; AVX512VL-NEXT: vblendmpd %xmm0, %xmm1, %xmm0 {%k1}
183 ; AVX512VL-NEXT: retq
184 ;
185 ; XOP-LABEL: signbit_sel_v2f64:
186 ; XOP: # %bb.0:
187 ; XOP-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
188 ; XOP-NEXT: retq
189 %tr = icmp slt <2 x i64> %mask, zeroinitializer
190 %z = select <2 x i1> %tr, <2 x double> %x, <2 x double> %y
191 ret <2 x double> %z
192 }
194 ; Test 256-bit vectors to see differences between AVX1 and AVX2.
196 define <32 x i8> @signbit_sel_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %mask) {
197 ; AVX1-LABEL: signbit_sel_v32i8:
198 ; AVX1: # %bb.0:
199 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
200 ; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
201 ; AVX1-NEXT: vpcmpgtb %xmm3, %xmm4, %xmm3
202 ; AVX1-NEXT: vpcmpgtb %xmm2, %xmm4, %xmm2
203 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
204 ; AVX1-NEXT: vandnps %ymm1, %ymm2, %ymm1
205 ; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
206 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
207 ; AVX1-NEXT: retq
208 ;
209 ; AVX2-LABEL: signbit_sel_v32i8:
210 ; AVX2: # %bb.0:
211 ; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
212 ; AVX2-NEXT: retq
213 ;
214 ; AVX512-LABEL: signbit_sel_v32i8:
215 ; AVX512: # %bb.0:
216 ; AVX512-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
217 ; AVX512-NEXT: retq
218 ;
219 ; XOP-LABEL: signbit_sel_v32i8:
220 ; XOP: # %bb.0:
221 ; XOP-NEXT: vextractf128 $1, %ymm2, %xmm3
222 ; XOP-NEXT: vpxor %xmm4, %xmm4, %xmm4
223 ; XOP-NEXT: vpcomltb %xmm4, %xmm3, %xmm3
224 ; XOP-NEXT: vpcomltb %xmm4, %xmm2, %xmm2
225 ; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
226 ; XOP-NEXT: vpcmov %ymm2, %ymm1, %ymm0, %ymm0
227 ; XOP-NEXT: retq
228 %tr = icmp slt <32 x i8> %mask, zeroinitializer
229 %z = select <32 x i1> %tr, <32 x i8> %x, <32 x i8> %y
230 ret <32 x i8> %z
231 }
233 ; Sorry 16-bit, you'll never be important enough to support?
235 define <16 x i16> @signbit_sel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %mask) {
236 ; AVX1-LABEL: signbit_sel_v16i16:
237 ; AVX1: # %bb.0:
238 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
239 ; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
240 ; AVX1-NEXT: vpcmpgtw %xmm3, %xmm4, %xmm3
241 ; AVX1-NEXT: vpcmpgtw %xmm2, %xmm4, %xmm2
242 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
243 ; AVX1-NEXT: vandnps %ymm1, %ymm2, %ymm1
244 ; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
245 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
246 ; AVX1-NEXT: retq
247 ;
248 ; AVX2-LABEL: signbit_sel_v16i16:
249 ; AVX2: # %bb.0:
250 ; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
251 ; AVX2-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2
252 ; AVX2-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
253 ; AVX2-NEXT: retq
254 ;
255 ; AVX512F-LABEL: signbit_sel_v16i16:
256 ; AVX512F: # %bb.0:
257 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
258 ; AVX512F-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2
259 ; AVX512F-NEXT: vpblendvb %ymm2, %ymm0, %ymm1, %ymm0
260 ; AVX512F-NEXT: retq
261 ;
262 ; AVX512VL-LABEL: signbit_sel_v16i16:
263 ; AVX512VL: # %bb.0:
264 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
265 ; AVX512VL-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2
266 ; AVX512VL-NEXT: vpternlogq $226, %ymm1, %ymm2, %ymm0
267 ; AVX512VL-NEXT: retq
268 ;
269 ; XOP-LABEL: signbit_sel_v16i16:
270 ; XOP: # %bb.0:
271 ; XOP-NEXT: vextractf128 $1, %ymm2, %xmm3
272 ; XOP-NEXT: vpxor %xmm4, %xmm4, %xmm4
273 ; XOP-NEXT: vpcomltw %xmm4, %xmm3, %xmm3
274 ; XOP-NEXT: vpcomltw %xmm4, %xmm2, %xmm2
275 ; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm2, %ymm2
276 ; XOP-NEXT: vpcmov %ymm2, %ymm1, %ymm0, %ymm0
277 ; XOP-NEXT: retq
278 %tr = icmp slt <16 x i16> %mask, zeroinitializer
279 %z = select <16 x i1> %tr, <16 x i16> %x, <16 x i16> %y
280 ret <16 x i16> %z
281 }
283 define <8 x i32> @signbit_sel_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %mask) {
284 ; AVX12-LABEL: signbit_sel_v8i32:
285 ; AVX12: # %bb.0:
286 ; AVX12-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
287 ; AVX12-NEXT: retq
288 ;
289 ; AVX512F-LABEL: signbit_sel_v8i32:
290 ; AVX512F: # %bb.0:
291 ; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
292 ; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
293 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
294 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
295 ; AVX512F-NEXT: vpcmpgtd %zmm2, %zmm3, %k1
296 ; AVX512F-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
297 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
298 ; AVX512F-NEXT: retq
299 ;
300 ; AVX512VL-LABEL: signbit_sel_v8i32:
301 ; AVX512VL: # %bb.0:
302 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
303 ; AVX512VL-NEXT: vpcmpgtd %ymm2, %ymm3, %k1
304 ; AVX512VL-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
305 ; AVX512VL-NEXT: retq
306 ;
307 ; XOP-LABEL: signbit_sel_v8i32:
308 ; XOP: # %bb.0:
309 ; XOP-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
310 ; XOP-NEXT: retq
311 %tr = icmp slt <8 x i32> %mask, zeroinitializer
312 %z = select <8 x i1> %tr, <8 x i32> %x, <8 x i32> %y
313 ret <8 x i32> %z
314 }
316 define <4 x i64> @signbit_sel_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %mask) {
317 ; AVX12-LABEL: signbit_sel_v4i64:
318 ; AVX12: # %bb.0:
319 ; AVX12-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
320 ; AVX12-NEXT: retq
321 ;
322 ; AVX512F-LABEL: signbit_sel_v4i64:
323 ; AVX512F: # %bb.0:
324 ; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
325 ; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
326 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
327 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
328 ; AVX512F-NEXT: vpcmpgtq %zmm2, %zmm3, %k1
329 ; AVX512F-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
330 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
331 ; AVX512F-NEXT: retq
332 ;
333 ; AVX512VL-LABEL: signbit_sel_v4i64:
334 ; AVX512VL: # %bb.0:
335 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
336 ; AVX512VL-NEXT: vpcmpgtq %ymm2, %ymm3, %k1
337 ; AVX512VL-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
338 ; AVX512VL-NEXT: retq
339 ;
340 ; XOP-LABEL: signbit_sel_v4i64:
341 ; XOP: # %bb.0:
342 ; XOP-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
343 ; XOP-NEXT: retq
344 %tr = icmp slt <4 x i64> %mask, zeroinitializer
345 %z = select <4 x i1> %tr, <4 x i64> %x, <4 x i64> %y
346 ret <4 x i64> %z
347 }
349 define <4 x double> @signbit_sel_v4f64(<4 x double> %x, <4 x double> %y, <4 x i64> %mask) {
350 ; AVX12-LABEL: signbit_sel_v4f64:
351 ; AVX12: # %bb.0:
352 ; AVX12-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
353 ; AVX12-NEXT: retq
354 ;
355 ; AVX512F-LABEL: signbit_sel_v4f64:
356 ; AVX512F: # %bb.0:
357 ; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
358 ; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
359 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
360 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
361 ; AVX512F-NEXT: vpcmpgtq %zmm2, %zmm3, %k1
362 ; AVX512F-NEXT: vblendmpd %zmm0, %zmm1, %zmm0 {%k1}
363 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
364 ; AVX512F-NEXT: retq
365 ;
366 ; AVX512VL-LABEL: signbit_sel_v4f64:
367 ; AVX512VL: # %bb.0:
368 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
369 ; AVX512VL-NEXT: vpcmpgtq %ymm2, %ymm3, %k1
370 ; AVX512VL-NEXT: vblendmpd %ymm0, %ymm1, %ymm0 {%k1}
371 ; AVX512VL-NEXT: retq
372 ;
373 ; XOP-LABEL: signbit_sel_v4f64:
374 ; XOP: # %bb.0:
375 ; XOP-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
376 ; XOP-NEXT: retq
377 %tr = icmp slt <4 x i64> %mask, zeroinitializer
378 %z = select <4 x i1> %tr, <4 x double> %x, <4 x double> %y
379 ret <4 x double> %z
380 }
382 ; Try a condition with a different type than the select operands.
384 define <4 x double> @signbit_sel_v4f64_small_mask(<4 x double> %x, <4 x double> %y, <4 x i32> %mask) {
385 ; AVX1-LABEL: signbit_sel_v4f64_small_mask:
386 ; AVX1: # %bb.0:
387 ; AVX1-NEXT: vpmovsxdq %xmm2, %xmm3
388 ; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
389 ; AVX1-NEXT: vpmovsxdq %xmm2, %xmm2
390 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
391 ; AVX1-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
392 ; AVX1-NEXT: retq
393 ;
394 ; AVX2-LABEL: signbit_sel_v4f64_small_mask:
395 ; AVX2: # %bb.0:
396 ; AVX2-NEXT: vpmovsxdq %xmm2, %ymm2
397 ; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
398 ; AVX2-NEXT: retq
399 ;
400 ; AVX512F-LABEL: signbit_sel_v4f64_small_mask:
401 ; AVX512F: # %bb.0:
402 ; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
403 ; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
404 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
405 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
406 ; AVX512F-NEXT: vpcmpgtd %zmm2, %zmm3, %k1
407 ; AVX512F-NEXT: vblendmpd %zmm0, %zmm1, %zmm0 {%k1}
408 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
409 ; AVX512F-NEXT: retq
410 ;
411 ; AVX512VL-LABEL: signbit_sel_v4f64_small_mask:
412 ; AVX512VL: # %bb.0:
413 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
414 ; AVX512VL-NEXT: vpcmpgtd %xmm2, %xmm3, %k1
415 ; AVX512VL-NEXT: vblendmpd %ymm0, %ymm1, %ymm0 {%k1}
416 ; AVX512VL-NEXT: retq
417 ;
418 ; XOP-LABEL: signbit_sel_v4f64_small_mask:
419 ; XOP: # %bb.0:
420 ; XOP-NEXT: vpmovsxdq %xmm2, %xmm3
421 ; XOP-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
422 ; XOP-NEXT: vpmovsxdq %xmm2, %xmm2
423 ; XOP-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
424 ; XOP-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
425 ; XOP-NEXT: retq
426 %tr = icmp slt <4 x i32> %mask, zeroinitializer
427 %z = select <4 x i1> %tr, <4 x double> %x, <4 x double> %y
428 ret <4 x double> %z
429 }
431 ; Try a 512-bit vector to make sure AVX-512 is handled as expected.
433 define <8 x double> @signbit_sel_v8f64(<8 x double> %x, <8 x double> %y, <8 x i64> %mask) {
434 ; AVX12-LABEL: signbit_sel_v8f64:
435 ; AVX12: # %bb.0:
436 ; AVX12-NEXT: vblendvpd %ymm4, %ymm0, %ymm2, %ymm0
437 ; AVX12-NEXT: vblendvpd %ymm5, %ymm1, %ymm3, %ymm1
438 ; AVX12-NEXT: retq
439 ;
440 ; AVX512-LABEL: signbit_sel_v8f64:
441 ; AVX512: # %bb.0:
442 ; AVX512-NEXT: vpxor %xmm3, %xmm3, %xmm3
443 ; AVX512-NEXT: vpcmpgtq %zmm2, %zmm3, %k1
444 ; AVX512-NEXT: vblendmpd %zmm0, %zmm1, %zmm0 {%k1}
445 ; AVX512-NEXT: retq
446 ;
447 ; XOP-LABEL: signbit_sel_v8f64:
448 ; XOP: # %bb.0:
449 ; XOP-NEXT: vblendvpd %ymm4, %ymm0, %ymm2, %ymm0
450 ; XOP-NEXT: vblendvpd %ymm5, %ymm1, %ymm3, %ymm1
451 ; XOP-NEXT: retq
452 %tr = icmp slt <8 x i64> %mask, zeroinitializer
453 %z = select <8 x i1> %tr, <8 x double> %x, <8 x double> %y
454 ret <8 x double> %z
455 }
457 ; If we have a floating-point compare:
458 ; (1) Don't die.
459 ; (2) FIXME: If we don't care about signed-zero (and NaN?), the compare should still get folded.
461 define <4 x float> @signbit_sel_v4f32_fcmp(<4 x float> %x, <4 x float> %y, <4 x float> %mask) #0 {
462 ; AVX12-LABEL: signbit_sel_v4f32_fcmp:
463 ; AVX12: # %bb.0:
464 ; AVX12-NEXT: vxorps %xmm2, %xmm2, %xmm2
465 ; AVX12-NEXT: vcmpltps %xmm2, %xmm0, %xmm2
466 ; AVX12-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
467 ; AVX12-NEXT: retq
468 ;
469 ; AVX512F-LABEL: signbit_sel_v4f32_fcmp:
470 ; AVX512F: # %bb.0:
471 ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
472 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
473 ; AVX512F-NEXT: vxorps %xmm2, %xmm2, %xmm2
474 ; AVX512F-NEXT: vcmpltps %zmm2, %zmm0, %k1
475 ; AVX512F-NEXT: vblendmps %zmm0, %zmm1, %zmm0 {%k1}
476 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
477 ; AVX512F-NEXT: vzeroupper
478 ; AVX512F-NEXT: retq
479 ;
480 ; AVX512VL-LABEL: signbit_sel_v4f32_fcmp:
481 ; AVX512VL: # %bb.0:
482 ; AVX512VL-NEXT: vxorps %xmm2, %xmm2, %xmm2
483 ; AVX512VL-NEXT: vcmpltps %xmm2, %xmm0, %k1
484 ; AVX512VL-NEXT: vblendmps %xmm0, %xmm1, %xmm0 {%k1}
485 ; AVX512VL-NEXT: retq
486 ;
487 ; XOP-LABEL: signbit_sel_v4f32_fcmp:
488 ; XOP: # %bb.0:
489 ; XOP-NEXT: vxorps %xmm2, %xmm2, %xmm2
490 ; XOP-NEXT: vcmpltps %xmm2, %xmm0, %xmm2
491 ; XOP-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
492 ; XOP-NEXT: retq
493 %cmp = fcmp olt <4 x float> %x, zeroinitializer
494 %sel = select <4 x i1> %cmp, <4 x float> %x, <4 x float> %y
495 ret <4 x float> %sel
496 }
498 define <4 x i64> @blend_splat1_mask_cond_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %z) {
499 ; AVX1-LABEL: blend_splat1_mask_cond_v4i64:
500 ; AVX1: # %bb.0:
501 ; AVX1-NEXT: vpsllq $63, %xmm0, %xmm3
502 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
503 ; AVX1-NEXT: vpsllq $63, %xmm0, %xmm0
504 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
505 ; AVX1-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
506 ; AVX1-NEXT: retq
507 ;
508 ; AVX2-LABEL: blend_splat1_mask_cond_v4i64:
509 ; AVX2: # %bb.0:
510 ; AVX2-NEXT: vpsllq $63, %ymm0, %ymm0
511 ; AVX2-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
512 ; AVX2-NEXT: retq
513 ;
514 ; AVX512F-LABEL: blend_splat1_mask_cond_v4i64:
515 ; AVX512F: # %bb.0:
516 ; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
517 ; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
518 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
519 ; AVX512F-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
520 ; AVX512F-NEXT: vpblendmq %zmm1, %zmm2, %zmm0 {%k1}
521 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
522 ; AVX512F-NEXT: retq
523 ;
524 ; AVX512VL-LABEL: blend_splat1_mask_cond_v4i64:
525 ; AVX512VL: # %bb.0:
526 ; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
527 ; AVX512VL-NEXT: vpblendmq %ymm1, %ymm2, %ymm0 {%k1}
528 ; AVX512VL-NEXT: retq
529 ;
530 ; XOP-LABEL: blend_splat1_mask_cond_v4i64:
531 ; XOP: # %bb.0:
532 ; XOP-NEXT: vextractf128 $1, %ymm0, %xmm3
533 ; XOP-NEXT: vpsllq $63, %xmm3, %xmm3
534 ; XOP-NEXT: vmovddup {{.*#+}} xmm4 = [18446744073709551553,18446744073709551553]
535 ; XOP-NEXT: # xmm4 = mem[0,0]
536 ; XOP-NEXT: vpshaq %xmm4, %xmm3, %xmm3
537 ; XOP-NEXT: vpsllq $63, %xmm0, %xmm0
538 ; XOP-NEXT: vpshaq %xmm4, %xmm0, %xmm0
539 ; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
540 ; XOP-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
541 ; XOP-NEXT: retq
542 %a = and <4 x i64> %x, <i64 1, i64 1, i64 1, i64 1>
543 %c = icmp eq <4 x i64> %a, zeroinitializer
544 %r = select <4 x i1> %c, <4 x i64> %y, <4 x i64> %z
545 ret <4 x i64> %r
546 }
548 define <4 x i32> @blend_splat1_mask_cond_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
549 ; AVX12-LABEL: blend_splat1_mask_cond_v4i32:
550 ; AVX12: # %bb.0:
551 ; AVX12-NEXT: vpslld $31, %xmm0, %xmm0
552 ; AVX12-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
553 ; AVX12-NEXT: retq
554 ;
555 ; AVX512F-LABEL: blend_splat1_mask_cond_v4i32:
556 ; AVX512F: # %bb.0:
557 ; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
558 ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
559 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
560 ; AVX512F-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
561 ; AVX512F-NEXT: vpblendmd %zmm1, %zmm2, %zmm0 {%k1}
562 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
563 ; AVX512F-NEXT: vzeroupper
564 ; AVX512F-NEXT: retq
565 ;
566 ; AVX512VL-LABEL: blend_splat1_mask_cond_v4i32:
567 ; AVX512VL: # %bb.0:
568 ; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
569 ; AVX512VL-NEXT: vpblendmd %xmm1, %xmm2, %xmm0 {%k1}
570 ; AVX512VL-NEXT: retq
571 ;
572 ; XOP-LABEL: blend_splat1_mask_cond_v4i32:
573 ; XOP: # %bb.0:
574 ; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
575 ; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
576 ; XOP-NEXT: vpcomneqd %xmm3, %xmm0, %xmm0
577 ; XOP-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
578 ; XOP-NEXT: retq
579 %a = and <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
580 %c = icmp eq <4 x i32> %a, zeroinitializer
581 %r = select <4 x i1> %c, <4 x i32> %y, <4 x i32> %z
582 ret <4 x i32> %r
583 }
585 define <16 x i16> @blend_splat1_mask_cond_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %z) {
586 ; AVX1-LABEL: blend_splat1_mask_cond_v16i16:
587 ; AVX1: # %bb.0:
588 ; AVX1-NEXT: vpsllw $15, %xmm0, %xmm3
589 ; AVX1-NEXT: vpsraw $15, %xmm3, %xmm3
590 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
591 ; AVX1-NEXT: vpsllw $15, %xmm0, %xmm0
592 ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0
593 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
594 ; AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm1
595 ; AVX1-NEXT: vandps %ymm0, %ymm2, %ymm0
596 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
597 ; AVX1-NEXT: retq
598 ;
599 ; AVX2-LABEL: blend_splat1_mask_cond_v16i16:
600 ; AVX2: # %bb.0:
601 ; AVX2-NEXT: vpsllw $15, %ymm0, %ymm0
602 ; AVX2-NEXT: vpsraw $15, %ymm0, %ymm0
603 ; AVX2-NEXT: vpblendvb %ymm0, %ymm2, %ymm1, %ymm0
604 ; AVX2-NEXT: retq
605 ;
606 ; AVX512F-LABEL: blend_splat1_mask_cond_v16i16:
607 ; AVX512F: # %bb.0:
608 ; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
609 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
610 ; AVX512F-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
611 ; AVX512F-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
612 ; AVX512F-NEXT: retq
613 ;
614 ; AVX512VL-LABEL: blend_splat1_mask_cond_v16i16:
615 ; AVX512VL: # %bb.0:
616 ; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
617 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
618 ; AVX512VL-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
619 ; AVX512VL-NEXT: vpternlogq $202, %ymm2, %ymm1, %ymm0
620 ; AVX512VL-NEXT: retq
621 ;
622 ; XOP-LABEL: blend_splat1_mask_cond_v16i16:
623 ; XOP: # %bb.0:
624 ; XOP-NEXT: vpsllw $15, %xmm0, %xmm3
625 ; XOP-NEXT: vpsraw $15, %xmm3, %xmm3
626 ; XOP-NEXT: vextractf128 $1, %ymm0, %xmm0
627 ; XOP-NEXT: vpsllw $15, %xmm0, %xmm0
628 ; XOP-NEXT: vpsraw $15, %xmm0, %xmm0
629 ; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
630 ; XOP-NEXT: vpcmov %ymm0, %ymm1, %ymm2, %ymm0
631 ; XOP-NEXT: retq
632 %a = and <16 x i16> %x, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
633 %c = icmp eq <16 x i16> %a, zeroinitializer
634 %r = select <16 x i1> %c, <16 x i16> %y, <16 x i16> %z
635 ret <16 x i16> %r
636 }
638 define <16 x i8> @blend_splat1_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %z) {
639 ; AVX12-LABEL: blend_splat1_mask_cond_v16i8:
640 ; AVX12: # %bb.0:
641 ; AVX12-NEXT: vpsllw $7, %xmm0, %xmm0
642 ; AVX12-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
643 ; AVX12-NEXT: retq
644 ;
645 ; AVX512F-LABEL: blend_splat1_mask_cond_v16i8:
646 ; AVX512F: # %bb.0:
647 ; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
648 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
649 ; AVX512F-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
650 ; AVX512F-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
651 ; AVX512F-NEXT: retq
652 ;
653 ; AVX512VL-LABEL: blend_splat1_mask_cond_v16i8:
654 ; AVX512VL: # %bb.0:
655 ; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
656 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
657 ; AVX512VL-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
658 ; AVX512VL-NEXT: vpternlogq $202, %xmm2, %xmm1, %xmm0
659 ; AVX512VL-NEXT: retq
660 ;
661 ; XOP-LABEL: blend_splat1_mask_cond_v16i8:
662 ; XOP: # %bb.0:
663 ; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
664 ; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
665 ; XOP-NEXT: vpcomneqb %xmm3, %xmm0, %xmm0
666 ; XOP-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
667 ; XOP-NEXT: retq
668 %a = and <16 x i8> %x, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
669 %c = icmp eq <16 x i8> %a, zeroinitializer
670 %r = select <16 x i1> %c, <16 x i8> %y, <16 x i8> %z
671 ret <16 x i8> %r
672 }
674 define <2 x i64> @blend_splatmax_mask_cond_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
675 ; AVX12-LABEL: blend_splatmax_mask_cond_v2i64:
676 ; AVX12: # %bb.0:
677 ; AVX12-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
678 ; AVX12-NEXT: retq
679 ;
680 ; AVX512F-LABEL: blend_splatmax_mask_cond_v2i64:
681 ; AVX512F: # %bb.0:
682 ; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
683 ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
684 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
685 ; AVX512F-NEXT: vpbroadcastq {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]
686 ; AVX512F-NEXT: vptestnmq %zmm3, %zmm0, %k1
687 ; AVX512F-NEXT: vpblendmq %zmm1, %zmm2, %zmm0 {%k1}
688 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
689 ; AVX512F-NEXT: vzeroupper
690 ; AVX512F-NEXT: retq
691 ;
692 ; AVX512VL-LABEL: blend_splatmax_mask_cond_v2i64:
693 ; AVX512VL: # %bb.0:
694 ; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm0, %k1
695 ; AVX512VL-NEXT: vpblendmq %xmm1, %xmm2, %xmm0 {%k1}
696 ; AVX512VL-NEXT: retq
697 ;
698 ; XOP-LABEL: blend_splatmax_mask_cond_v2i64:
699 ; XOP: # %bb.0:
700 ; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
701 ; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
702 ; XOP-NEXT: vpcomneqq %xmm3, %xmm0, %xmm0
703 ; XOP-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
704 ; XOP-NEXT: retq
705 %a = and <2 x i64> %x, <i64 9223372036854775808, i64 9223372036854775808>
706 %c = icmp eq <2 x i64> %a, zeroinitializer
707 %r = select <2 x i1> %c, <2 x i64> %y, <2 x i64> %z
708 ret <2 x i64> %r
709 }
711 define <8 x i32> @blend_splatmax_mask_cond_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
712 ; AVX12-LABEL: blend_splatmax_mask_cond_v8i32:
713 ; AVX12: # %bb.0:
714 ; AVX12-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
715 ; AVX12-NEXT: retq
716 ;
717 ; AVX512F-LABEL: blend_splatmax_mask_cond_v8i32:
718 ; AVX512F: # %bb.0:
719 ; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
720 ; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
721 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
722 ; AVX512F-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
723 ; AVX512F-NEXT: vpblendmd %zmm1, %zmm2, %zmm0 {%k1}
724 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
725 ; AVX512F-NEXT: retq
726 ;
727 ; AVX512VL-LABEL: blend_splatmax_mask_cond_v8i32:
728 ; AVX512VL: # %bb.0:
729 ; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %k1
730 ; AVX512VL-NEXT: vpblendmd %ymm1, %ymm2, %ymm0 {%k1}
731 ; AVX512VL-NEXT: retq
732 ;
733 ; XOP-LABEL: blend_splatmax_mask_cond_v8i32:
734 ; XOP: # %bb.0:
735 ; XOP-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
736 ; XOP-NEXT: retq
737 %a = and <8 x i32> %x, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
738 %c = icmp eq <8 x i32> %a, zeroinitializer
739 %r = select <8 x i1> %c, <8 x i32> %y, <8 x i32> %z
740 ret <8 x i32> %r
741 }
743 define <8 x i16> @blend_splatmax_mask_cond_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %z) {
744 ; AVX12-LABEL: blend_splatmax_mask_cond_v8i16:
745 ; AVX12: # %bb.0:
746 ; AVX12-NEXT: vpsraw $15, %xmm0, %xmm0
747 ; AVX12-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
748 ; AVX12-NEXT: retq
749 ;
750 ; AVX512F-LABEL: blend_splatmax_mask_cond_v8i16:
751 ; AVX512F: # %bb.0:
752 ; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
753 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
754 ; AVX512F-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm0
755 ; AVX512F-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
756 ; AVX512F-NEXT: retq
757 ;
758 ; AVX512VL-LABEL: blend_splatmax_mask_cond_v8i16:
759 ; AVX512VL: # %bb.0:
760 ; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
761 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
762 ; AVX512VL-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm0
763 ; AVX512VL-NEXT: vpternlogq $202, %xmm2, %xmm1, %xmm0
764 ; AVX512VL-NEXT: retq
765 ;
766 ; XOP-LABEL: blend_splatmax_mask_cond_v8i16:
767 ; XOP: # %bb.0:
768 ; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
769 ; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
770 ; XOP-NEXT: vpcomneqw %xmm3, %xmm0, %xmm0
771 ; XOP-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
772 ; XOP-NEXT: retq
773 %a = and <8 x i16> %x, <i16 32768, i16 32768, i16 32768, i16 32768, i16 32768, i16 32768, i16 32768, i16 32768>
774 %c = icmp eq <8 x i16> %a, zeroinitializer
775 %r = select <8 x i1> %c, <8 x i16> %y, <8 x i16> %z
776 ret <8 x i16> %r
777 }
779 define <32 x i8> @blend_splatmax_mask_cond_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %z) {
780 ; AVX1-LABEL: blend_splatmax_mask_cond_v32i8:
781 ; AVX1: # %bb.0:
782 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
783 ; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
784 ; AVX1-NEXT: vpcmpgtb %xmm3, %xmm4, %xmm3
785 ; AVX1-NEXT: vpcmpgtb %xmm0, %xmm4, %xmm0
786 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
787 ; AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm1
788 ; AVX1-NEXT: vandps %ymm0, %ymm2, %ymm0
789 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
790 ; AVX1-NEXT: retq
791 ;
792 ; AVX2-LABEL: blend_splatmax_mask_cond_v32i8:
793 ; AVX2: # %bb.0:
794 ; AVX2-NEXT: vpblendvb %ymm0, %ymm2, %ymm1, %ymm0
795 ; AVX2-NEXT: retq
796 ;
797 ; AVX512F-LABEL: blend_splatmax_mask_cond_v32i8:
798 ; AVX512F: # %bb.0:
799 ; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
800 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
801 ; AVX512F-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm0
802 ; AVX512F-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
803 ; AVX512F-NEXT: retq
804 ;
805 ; AVX512VL-LABEL: blend_splatmax_mask_cond_v32i8:
806 ; AVX512VL: # %bb.0:
807 ; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
808 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
809 ; AVX512VL-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm0
810 ; AVX512VL-NEXT: vpternlogq $202, %ymm2, %ymm1, %ymm0
811 ; AVX512VL-NEXT: retq
812 ;
813 ; XOP-LABEL: blend_splatmax_mask_cond_v32i8:
814 ; XOP: # %bb.0:
815 ; XOP-NEXT: vextractf128 $1, %ymm0, %xmm3
816 ; XOP-NEXT: vpxor %xmm4, %xmm4, %xmm4
817 ; XOP-NEXT: vpcmpgtb %xmm3, %xmm4, %xmm3
818 ; XOP-NEXT: vpcmpgtb %xmm0, %xmm4, %xmm0
819 ; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
820 ; XOP-NEXT: vpcmov %ymm0, %ymm1, %ymm2, %ymm0
821 ; XOP-NEXT: retq
822 %a = and <32 x i8> %x, <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>
823 %c = icmp eq <32 x i8> %a, zeroinitializer
824 %r = select <32 x i1> %c, <32 x i8> %y, <32 x i8> %z
825 ret <32 x i8> %r
826 }
828 define <4 x i64> @blend_splat_mask_cond_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %z) {
829 ; AVX1-LABEL: blend_splat_mask_cond_v4i64:
830 ; AVX1: # %bb.0:
831 ; AVX1-NEXT: vpsllq $62, %xmm0, %xmm3
832 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
833 ; AVX1-NEXT: vpsllq $62, %xmm0, %xmm0
834 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
835 ; AVX1-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
836 ; AVX1-NEXT: retq
837 ;
838 ; AVX2-LABEL: blend_splat_mask_cond_v4i64:
839 ; AVX2: # %bb.0:
840 ; AVX2-NEXT: vpsllq $62, %ymm0, %ymm0
841 ; AVX2-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
842 ; AVX2-NEXT: retq
843 ;
844 ; AVX512F-LABEL: blend_splat_mask_cond_v4i64:
845 ; AVX512F: # %bb.0:
846 ; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
847 ; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
848 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
849 ; AVX512F-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm0, %k1
850 ; AVX512F-NEXT: vpblendmq %zmm1, %zmm2, %zmm0 {%k1}
851 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
852 ; AVX512F-NEXT: retq
853 ;
854 ; AVX512VL-LABEL: blend_splat_mask_cond_v4i64:
855 ; AVX512VL: # %bb.0:
856 ; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %ymm0, %k1
857 ; AVX512VL-NEXT: vpblendmq %ymm1, %ymm2, %ymm0 {%k1}
858 ; AVX512VL-NEXT: retq
859 ;
860 ; XOP-LABEL: blend_splat_mask_cond_v4i64:
861 ; XOP: # %bb.0:
862 ; XOP-NEXT: vextractf128 $1, %ymm0, %xmm3
863 ; XOP-NEXT: vpsllq $62, %xmm3, %xmm3
864 ; XOP-NEXT: vmovddup {{.*#+}} xmm4 = [18446744073709551553,18446744073709551553]
865 ; XOP-NEXT: # xmm4 = mem[0,0]
866 ; XOP-NEXT: vpshaq %xmm4, %xmm3, %xmm3
867 ; XOP-NEXT: vpsllq $62, %xmm0, %xmm0
868 ; XOP-NEXT: vpshaq %xmm4, %xmm0, %xmm0
869 ; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
870 ; XOP-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
871 ; XOP-NEXT: retq
872 %a = and <4 x i64> %x, <i64 2, i64 2, i64 2, i64 2>
873 %c = icmp eq <4 x i64> %a, zeroinitializer
874 %r = select <4 x i1> %c, <4 x i64> %y, <4 x i64> %z
875 ret <4 x i64> %r
876 }
878 define <4 x i32> @blend_splat_mask_cond_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
879 ; AVX12-LABEL: blend_splat_mask_cond_v4i32:
880 ; AVX12: # %bb.0:
881 ; AVX12-NEXT: vpslld $15, %xmm0, %xmm0
882 ; AVX12-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
883 ; AVX12-NEXT: retq
884 ;
885 ; AVX512F-LABEL: blend_splat_mask_cond_v4i32:
886 ; AVX512F: # %bb.0:
887 ; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
888 ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
889 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
890 ; AVX512F-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %k1
891 ; AVX512F-NEXT: vpblendmd %zmm1, %zmm2, %zmm0 {%k1}
892 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
893 ; AVX512F-NEXT: vzeroupper
894 ; AVX512F-NEXT: retq
895 ;
896 ; AVX512VL-LABEL: blend_splat_mask_cond_v4i32:
897 ; AVX512VL: # %bb.0:
898 ; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %k1
899 ; AVX512VL-NEXT: vpblendmd %xmm1, %xmm2, %xmm0 {%k1}
900 ; AVX512VL-NEXT: retq
901 ;
902 ; XOP-LABEL: blend_splat_mask_cond_v4i32:
903 ; XOP: # %bb.0:
904 ; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
905 ; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
906 ; XOP-NEXT: vpcomneqd %xmm3, %xmm0, %xmm0
907 ; XOP-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
908 ; XOP-NEXT: retq
909 %a = and <4 x i32> %x, <i32 65536, i32 65536, i32 65536, i32 65536>
910 %c = icmp eq <4 x i32> %a, zeroinitializer
911 %r = select <4 x i1> %c, <4 x i32> %y, <4 x i32> %z
912 ret <4 x i32> %r
913 }
915 define <16 x i16> @blend_splat_mask_cond_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %z) {
916 ; AVX1-LABEL: blend_splat_mask_cond_v16i16:
917 ; AVX1: # %bb.0:
918 ; AVX1-NEXT: vpsllw $5, %xmm0, %xmm3
919 ; AVX1-NEXT: vpsraw $15, %xmm3, %xmm3
920 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
921 ; AVX1-NEXT: vpsllw $5, %xmm0, %xmm0
922 ; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0
923 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
924 ; AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm1
925 ; AVX1-NEXT: vandps %ymm0, %ymm2, %ymm0
926 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
927 ; AVX1-NEXT: retq
928 ;
929 ; AVX2-LABEL: blend_splat_mask_cond_v16i16:
930 ; AVX2: # %bb.0:
931 ; AVX2-NEXT: vpsllw $5, %ymm0, %ymm0
932 ; AVX2-NEXT: vpsraw $15, %ymm0, %ymm0
933 ; AVX2-NEXT: vpblendvb %ymm0, %ymm2, %ymm1, %ymm0
934 ; AVX2-NEXT: retq
935 ;
936 ; AVX512F-LABEL: blend_splat_mask_cond_v16i16:
937 ; AVX512F: # %bb.0:
938 ; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
939 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
940 ; AVX512F-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
941 ; AVX512F-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
942 ; AVX512F-NEXT: retq
943 ;
944 ; AVX512VL-LABEL: blend_splat_mask_cond_v16i16:
945 ; AVX512VL: # %bb.0:
946 ; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
947 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
948 ; AVX512VL-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
949 ; AVX512VL-NEXT: vpternlogq $202, %ymm2, %ymm1, %ymm0
950 ; AVX512VL-NEXT: retq
951 ;
952 ; XOP-LABEL: blend_splat_mask_cond_v16i16:
953 ; XOP: # %bb.0:
954 ; XOP-NEXT: vpsllw $5, %xmm0, %xmm3
955 ; XOP-NEXT: vpsraw $15, %xmm3, %xmm3
956 ; XOP-NEXT: vextractf128 $1, %ymm0, %xmm0
957 ; XOP-NEXT: vpsllw $5, %xmm0, %xmm0
958 ; XOP-NEXT: vpsraw $15, %xmm0, %xmm0
959 ; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
960 ; XOP-NEXT: vpcmov %ymm0, %ymm1, %ymm2, %ymm0
961 ; XOP-NEXT: retq
962 %a = and <16 x i16> %x, <i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024>
963 %c = icmp eq <16 x i16> %a, zeroinitializer
964 %r = select <16 x i1> %c, <16 x i16> %y, <16 x i16> %z
965 ret <16 x i16> %r
966 }
968 define <16 x i8> @blend_splat_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %z) {
969 ; AVX12-LABEL: blend_splat_mask_cond_v16i8:
970 ; AVX12: # %bb.0:
971 ; AVX12-NEXT: vpsllw $5, %xmm0, %xmm0
972 ; AVX12-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
973 ; AVX12-NEXT: retq
974 ;
975 ; AVX512F-LABEL: blend_splat_mask_cond_v16i8:
976 ; AVX512F: # %bb.0:
977 ; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
978 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
979 ; AVX512F-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
980 ; AVX512F-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
981 ; AVX512F-NEXT: retq
982 ;
983 ; AVX512VL-LABEL: blend_splat_mask_cond_v16i8:
984 ; AVX512VL: # %bb.0:
985 ; AVX512VL-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
986 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
987 ; AVX512VL-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
988 ; AVX512VL-NEXT: vpternlogq $202, %xmm2, %xmm1, %xmm0
989 ; AVX512VL-NEXT: retq
990 ;
991 ; XOP-LABEL: blend_splat_mask_cond_v16i8:
992 ; XOP: # %bb.0:
993 ; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
994 ; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
995 ; XOP-NEXT: vpcomneqb %xmm3, %xmm0, %xmm0
996 ; XOP-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
997 ; XOP-NEXT: retq
998 %a = and <16 x i8> %x, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
999 %c = icmp eq <16 x i8> %a, zeroinitializer
1000 %r = select <16 x i1> %c, <16 x i8> %y, <16 x i8> %z
1001 ret <16 x i8> %r
1002 }
1004 define <2 x i64> @blend_mask_cond_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) {
1005 ; AVX1-LABEL: blend_mask_cond_v2i64:
1006 ; AVX1: # %bb.0:
1007 ; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1008 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
1009 ; AVX1-NEXT: vpcmpeqq %xmm3, %xmm0, %xmm0
1010 ; AVX1-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
1011 ; AVX1-NEXT: retq
1012 ;
1013 ; AVX2-LABEL: blend_mask_cond_v2i64:
1014 ; AVX2: # %bb.0:
1015 ; AVX2-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1016 ; AVX2-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
1017 ; AVX2-NEXT: retq
1018 ;
1019 ; AVX512F-LABEL: blend_mask_cond_v2i64:
1020 ; AVX512F: # %bb.0:
1021 ; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
1022 ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
1023 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
1024 ; AVX512F-NEXT: vmovdqa {{.*#+}} xmm3 = [1,4]
1025 ; AVX512F-NEXT: vptestnmq %zmm3, %zmm0, %k1
1026 ; AVX512F-NEXT: vpblendmq %zmm1, %zmm2, %zmm0 {%k1}
1027 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
1028 ; AVX512F-NEXT: vzeroupper
1029 ; AVX512F-NEXT: retq
1030 ;
1031 ; AVX512VL-LABEL: blend_mask_cond_v2i64:
1032 ; AVX512VL: # %bb.0:
1033 ; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
1034 ; AVX512VL-NEXT: vpblendmq %xmm1, %xmm2, %xmm0 {%k1}
1035 ; AVX512VL-NEXT: retq
1036 ;
1037 ; XOP-LABEL: blend_mask_cond_v2i64:
1038 ; XOP: # %bb.0:
1039 ; XOP-NEXT: vpshlq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1040 ; XOP-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
1041 ; XOP-NEXT: retq
1042 %a = and <2 x i64> %x, <i64 1, i64 4>
1043 %c = icmp eq <2 x i64> %a, zeroinitializer
1044 %r = select <2 x i1> %c, <2 x i64> %y, <2 x i64> %z
1045 ret <2 x i64> %r
1046 }
1048 define <4 x i32> @blend_mask_cond_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
1049 ; AVX1-LABEL: blend_mask_cond_v4i32:
1050 ; AVX1: # %bb.0:
1051 ; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1052 ; AVX1-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
1053 ; AVX1-NEXT: retq
1054 ;
1055 ; AVX2-LABEL: blend_mask_cond_v4i32:
1056 ; AVX2: # %bb.0:
1057 ; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1058 ; AVX2-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
1059 ; AVX2-NEXT: retq
1060 ;
1061 ; AVX512F-LABEL: blend_mask_cond_v4i32:
1062 ; AVX512F: # %bb.0:
1063 ; AVX512F-NEXT: # kill: def $xmm2 killed $xmm2 def $zmm2
1064 ; AVX512F-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
1065 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
1066 ; AVX512F-NEXT: vmovdqa {{.*#+}} xmm3 = [65536,512,2,1]
1067 ; AVX512F-NEXT: vptestnmd %zmm3, %zmm0, %k1
1068 ; AVX512F-NEXT: vpblendmd %zmm1, %zmm2, %zmm0 {%k1}
1069 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
1070 ; AVX512F-NEXT: vzeroupper
1071 ; AVX512F-NEXT: retq
1072 ;
1073 ; AVX512VL-LABEL: blend_mask_cond_v4i32:
1074 ; AVX512VL: # %bb.0:
1075 ; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k1
1076 ; AVX512VL-NEXT: vpblendmd %xmm1, %xmm2, %xmm0 {%k1}
1077 ; AVX512VL-NEXT: retq
1078 ;
1079 ; XOP-LABEL: blend_mask_cond_v4i32:
1080 ; XOP: # %bb.0:
1081 ; XOP-NEXT: vpshld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1082 ; XOP-NEXT: vblendvps %xmm0, %xmm2, %xmm1, %xmm0
1083 ; XOP-NEXT: retq
1084 %a = and <4 x i32> %x, <i32 65536, i32 512, i32 2, i32 1>
1085 %c = icmp eq <4 x i32> %a, zeroinitializer
1086 %r = select <4 x i1> %c, <4 x i32> %y, <4 x i32> %z
1087 ret <4 x i32> %r
1088 }
1090 define <8 x i16> @blend_mask_cond_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %z) {
1091 ; AVX12-LABEL: blend_mask_cond_v8i16:
1092 ; AVX12: # %bb.0:
1093 ; AVX12-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1094 ; AVX12-NEXT: vpxor %xmm3, %xmm3, %xmm3
1095 ; AVX12-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm0
1096 ; AVX12-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
1097 ; AVX12-NEXT: retq
1098 ;
1099 ; AVX512F-LABEL: blend_mask_cond_v8i16:
1100 ; AVX512F: # %bb.0:
1101 ; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1102 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
1103 ; AVX512F-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm0
1104 ; AVX512F-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
1105 ; AVX512F-NEXT: retq
1106 ;
1107 ; AVX512VL-LABEL: blend_mask_cond_v8i16:
1108 ; AVX512VL: # %bb.0:
1109 ; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1110 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
1111 ; AVX512VL-NEXT: vpcmpeqw %xmm3, %xmm0, %xmm0
1112 ; AVX512VL-NEXT: vpternlogq $202, %xmm2, %xmm1, %xmm0
1113 ; AVX512VL-NEXT: retq
1114 ;
1115 ; XOP-LABEL: blend_mask_cond_v8i16:
1116 ; XOP: # %bb.0:
1117 ; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
1118 ; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1119 ; XOP-NEXT: vpcomltw %xmm3, %xmm0, %xmm0
1120 ; XOP-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
1121 ; XOP-NEXT: retq
1122 %a = and <8 x i16> %x, <i16 1, i16 2, i16 8, i16 4, i16 8, i16 1024, i16 2, i16 4096>
1123 %c = icmp eq <8 x i16> %a, zeroinitializer
1124 %r = select <8 x i1> %c, <8 x i16> %y, <8 x i16> %z
1125 ret <8 x i16> %r
1126 }
1128 define <16 x i8> @blend_mask_cond_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %z) {
1129 ; AVX12-LABEL: blend_mask_cond_v16i8:
1130 ; AVX12: # %bb.0:
1131 ; AVX12-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1132 ; AVX12-NEXT: vpxor %xmm3, %xmm3, %xmm3
1133 ; AVX12-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
1134 ; AVX12-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
1135 ; AVX12-NEXT: retq
1136 ;
1137 ; AVX512F-LABEL: blend_mask_cond_v16i8:
1138 ; AVX512F: # %bb.0:
1139 ; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1140 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
1141 ; AVX512F-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
1142 ; AVX512F-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0
1143 ; AVX512F-NEXT: retq
1144 ;
1145 ; AVX512VL-LABEL: blend_mask_cond_v16i8:
1146 ; AVX512VL: # %bb.0:
1147 ; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1148 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
1149 ; AVX512VL-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
1150 ; AVX512VL-NEXT: vpternlogq $202, %xmm2, %xmm1, %xmm0
1151 ; AVX512VL-NEXT: retq
1152 ;
1153 ; XOP-LABEL: blend_mask_cond_v16i8:
1154 ; XOP: # %bb.0:
1155 ; XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1156 ; XOP-NEXT: vpblendvb %xmm0, %xmm2, %xmm1, %xmm0
1157 ; XOP-NEXT: retq
1158 %a = and <16 x i8> %x, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 128, i8 4, i8 4, i8 4, i8 4, i8 2, i8 2, i8 2, i8 2>
1159 %c = icmp eq <16 x i8> %a, zeroinitializer
1160 %r = select <16 x i1> %c, <16 x i8> %y, <16 x i8> %z
1161 ret <16 x i8> %r
1162 }
1164 define <4 x i64> @blend_mask_cond_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i64> %z) {
1165 ; AVX1-LABEL: blend_mask_cond_v4i64:
1166 ; AVX1: # %bb.0:
1167 ; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1168 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1169 ; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
1170 ; AVX1-NEXT: vpcmpeqq %xmm4, %xmm3, %xmm3
1171 ; AVX1-NEXT: vpcmpeqq %xmm4, %xmm0, %xmm0
1172 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
1173 ; AVX1-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
1174 ; AVX1-NEXT: retq
1175 ;
1176 ; AVX2-LABEL: blend_mask_cond_v4i64:
1177 ; AVX2: # %bb.0:
1178 ; AVX2-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1179 ; AVX2-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
1180 ; AVX2-NEXT: retq
1181 ;
1182 ; AVX512F-LABEL: blend_mask_cond_v4i64:
1183 ; AVX512F: # %bb.0:
1184 ; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
1185 ; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
1186 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
1187 ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [2,4,32768,1]
1188 ; AVX512F-NEXT: vptestnmq %zmm3, %zmm0, %k1
1189 ; AVX512F-NEXT: vpblendmq %zmm1, %zmm2, %zmm0 {%k1}
1190 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
1191 ; AVX512F-NEXT: retq
1192 ;
1193 ; AVX512VL-LABEL: blend_mask_cond_v4i64:
1194 ; AVX512VL: # %bb.0:
1195 ; AVX512VL-NEXT: vptestnmq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k1
1196 ; AVX512VL-NEXT: vpblendmq %ymm1, %ymm2, %ymm0 {%k1}
1197 ; AVX512VL-NEXT: retq
1198 ;
1199 ; XOP-LABEL: blend_mask_cond_v4i64:
1200 ; XOP: # %bb.0:
1201 ; XOP-NEXT: vpshlq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
1202 ; XOP-NEXT: vextractf128 $1, %ymm0, %xmm0
1203 ; XOP-NEXT: vpshlq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1204 ; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
1205 ; XOP-NEXT: vblendvpd %ymm0, %ymm2, %ymm1, %ymm0
1206 ; XOP-NEXT: retq
1207 %a = and <4 x i64> %x, <i64 2, i64 4, i64 32768, i64 1>
1208 %c = icmp eq <4 x i64> %a, zeroinitializer
1209 %r = select <4 x i1> %c, <4 x i64> %y, <4 x i64> %z
1210 ret <4 x i64> %r
1211 }
1213 define <8 x i32> @blend_mask_cond_v8i32(<8 x i32> %x, <8 x i32> %y, <8 x i32> %z) {
1214 ; AVX1-LABEL: blend_mask_cond_v8i32:
1215 ; AVX1: # %bb.0:
1216 ; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
1217 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1218 ; AVX1-NEXT: vpmulld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1219 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
1220 ; AVX1-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
1221 ; AVX1-NEXT: retq
1222 ;
1223 ; AVX2-LABEL: blend_mask_cond_v8i32:
1224 ; AVX2: # %bb.0:
1225 ; AVX2-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1226 ; AVX2-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
1227 ; AVX2-NEXT: retq
1228 ;
1229 ; AVX512F-LABEL: blend_mask_cond_v8i32:
1230 ; AVX512F: # %bb.0:
1231 ; AVX512F-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
1232 ; AVX512F-NEXT: # kill: def $ymm1 killed $ymm1 def $zmm1
1233 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
1234 ; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [1,2,8,4,8,1024,2,4096]
1235 ; AVX512F-NEXT: vptestnmd %zmm3, %zmm0, %k1
1236 ; AVX512F-NEXT: vpblendmd %zmm1, %zmm2, %zmm0 {%k1}
1237 ; AVX512F-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
1238 ; AVX512F-NEXT: retq
1239 ;
1240 ; AVX512VL-LABEL: blend_mask_cond_v8i32:
1241 ; AVX512VL: # %bb.0:
1242 ; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %k1
1243 ; AVX512VL-NEXT: vpblendmd %ymm1, %ymm2, %ymm0 {%k1}
1244 ; AVX512VL-NEXT: retq
1245 ;
1246 ; XOP-LABEL: blend_mask_cond_v8i32:
1247 ; XOP: # %bb.0:
1248 ; XOP-NEXT: vpshld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm3
1249 ; XOP-NEXT: vextractf128 $1, %ymm0, %xmm0
1250 ; XOP-NEXT: vpshld {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1251 ; XOP-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0
1252 ; XOP-NEXT: vblendvps %ymm0, %ymm2, %ymm1, %ymm0
1253 ; XOP-NEXT: retq
1254 %a = and <8 x i32> %x, <i32 1, i32 2, i32 8, i32 4, i32 8, i32 1024, i32 2, i32 4096>
1255 %c = icmp eq <8 x i32> %a, zeroinitializer
1256 %r = select <8 x i1> %c, <8 x i32> %y, <8 x i32> %z
1257 ret <8 x i32> %r
1258 }
1260 define <16 x i16> @blend_mask_cond_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %z) {
1261 ; AVX1-LABEL: blend_mask_cond_v16i16:
1262 ; AVX1: # %bb.0:
1263 ; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1264 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1265 ; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
1266 ; AVX1-NEXT: vpcmpeqw %xmm4, %xmm3, %xmm3
1267 ; AVX1-NEXT: vpcmpeqw %xmm4, %xmm0, %xmm0
1268 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
1269 ; AVX1-NEXT: vandnps %ymm2, %ymm0, %ymm2
1270 ; AVX1-NEXT: vandps %ymm0, %ymm1, %ymm0
1271 ; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
1272 ; AVX1-NEXT: retq
1273 ;
1274 ; AVX2-LABEL: blend_mask_cond_v16i16:
1275 ; AVX2: # %bb.0:
1276 ; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1277 ; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
1278 ; AVX2-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
1279 ; AVX2-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
1280 ; AVX2-NEXT: retq
1281 ;
1282 ; AVX512F-LABEL: blend_mask_cond_v16i16:
1283 ; AVX512F: # %bb.0:
1284 ; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1285 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
1286 ; AVX512F-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
1287 ; AVX512F-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
1288 ; AVX512F-NEXT: retq
1289 ;
1290 ; AVX512VL-LABEL: blend_mask_cond_v16i16:
1291 ; AVX512VL: # %bb.0:
1292 ; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1293 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
1294 ; AVX512VL-NEXT: vpcmpeqw %ymm3, %ymm0, %ymm0
1295 ; AVX512VL-NEXT: vpternlogq $202, %ymm2, %ymm1, %ymm0
1296 ; AVX512VL-NEXT: retq
1297 ;
1298 ; XOP-LABEL: blend_mask_cond_v16i16:
1299 ; XOP: # %bb.0:
1300 ; XOP-NEXT: vextractf128 $1, %ymm0, %xmm3
1301 ; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
1302 ; XOP-NEXT: vpxor %xmm4, %xmm4, %xmm4
1303 ; XOP-NEXT: vpcomltw %xmm4, %xmm3, %xmm3
1304 ; XOP-NEXT: vpshlw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1305 ; XOP-NEXT: vpcomltw %xmm4, %xmm0, %xmm0
1306 ; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
1307 ; XOP-NEXT: vpcmov %ymm0, %ymm1, %ymm2, %ymm0
1308 ; XOP-NEXT: retq
1309 %a = and <16 x i16> %x, <i16 1, i16 2, i16 8, i16 4, i16 8, i16 2, i16 2, i16 2, i16 2, i16 8, i16 8, i16 64, i16 64, i16 1024, i16 4096, i16 1024>
1310 %c = icmp eq <16 x i16> %a, zeroinitializer
1311 %r = select <16 x i1> %c, <16 x i16> %y, <16 x i16> %z
1312 ret <16 x i16> %r
1313 }
1315 define <32 x i8> @blend_mask_cond_v32i8(<32 x i8> %x, <32 x i8> %y, <32 x i8> %z) {
1316 ; AVX1-LABEL: blend_mask_cond_v32i8:
1317 ; AVX1: # %bb.0:
1318 ; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1319 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1320 ; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
1321 ; AVX1-NEXT: vpcmpeqb %xmm4, %xmm3, %xmm3
1322 ; AVX1-NEXT: vpcmpeqb %xmm4, %xmm0, %xmm0
1323 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
1324 ; AVX1-NEXT: vandnps %ymm2, %ymm0, %ymm2
1325 ; AVX1-NEXT: vandps %ymm0, %ymm1, %ymm0
1326 ; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
1327 ; AVX1-NEXT: retq
1328 ;
1329 ; AVX2-LABEL: blend_mask_cond_v32i8:
1330 ; AVX2: # %bb.0:
1331 ; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1332 ; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
1333 ; AVX2-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm0
1334 ; AVX2-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
1335 ; AVX2-NEXT: retq
1336 ;
1337 ; AVX512F-LABEL: blend_mask_cond_v32i8:
1338 ; AVX512F: # %bb.0:
1339 ; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1340 ; AVX512F-NEXT: vpxor %xmm3, %xmm3, %xmm3
1341 ; AVX512F-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm0
1342 ; AVX512F-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0
1343 ; AVX512F-NEXT: retq
1344 ;
1345 ; AVX512VL-LABEL: blend_mask_cond_v32i8:
1346 ; AVX512VL: # %bb.0:
1347 ; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
1348 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
1349 ; AVX512VL-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm0
1350 ; AVX512VL-NEXT: vpternlogq $202, %ymm2, %ymm1, %ymm0
1351 ; AVX512VL-NEXT: retq
1352 ;
1353 ; XOP-LABEL: blend_mask_cond_v32i8:
1354 ; XOP: # %bb.0:
1355 ; XOP-NEXT: vextractf128 $1, %ymm0, %xmm3
1356 ; XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3, %xmm3
1357 ; XOP-NEXT: vpxor %xmm4, %xmm4, %xmm4
1358 ; XOP-NEXT: vpcomltb %xmm4, %xmm3, %xmm3
1359 ; XOP-NEXT: vpshlb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
1360 ; XOP-NEXT: vpcomltb %xmm4, %xmm0, %xmm0
1361 ; XOP-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
1362 ; XOP-NEXT: vpcmov %ymm0, %ymm1, %ymm2, %ymm0
1363 ; XOP-NEXT: retq
1364 %a = and <32 x i8> %x, <i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 128, i8 4, i8 4, i8 4, i8 4, i8 2, i8 2, i8 2, i8 2, i8 1, i8 2, i8 4, i8 8, i8 16, i8 32, i8 64, i8 128, i8 4, i8 4, i8 4, i8 4, i8 128, i8 4, i8 2, i8 16>
1365 %c = icmp eq <32 x i8> %a, zeroinitializer
1366 %r = select <32 x i1> %c, <32 x i8> %y, <32 x i8> %z
1367 ret <32 x i8> %r
1368 }
1370 define void @PR46531(ptr %x, ptr %y, ptr %z) {
1371 ; AVX12-LABEL: PR46531:
1372 ; AVX12: # %bb.0:
1373 ; AVX12-NEXT: vmovdqu (%rsi), %xmm0
1374 ; AVX12-NEXT: vmovdqu (%rdx), %xmm1
1375 ; AVX12-NEXT: vpor %xmm0, %xmm1, %xmm2
1376 ; AVX12-NEXT: vpxor %xmm0, %xmm1, %xmm0
1377 ; AVX12-NEXT: vpslld $31, %xmm1, %xmm1
1378 ; AVX12-NEXT: vblendvps %xmm1, %xmm0, %xmm2, %xmm0
1379 ; AVX12-NEXT: vmovups %xmm0, (%rdi)
1380 ; AVX12-NEXT: retq
1381 ;
1382 ; AVX512F-LABEL: PR46531:
1383 ; AVX512F: # %bb.0:
1384 ; AVX512F-NEXT: vmovdqu (%rsi), %xmm0
1385 ; AVX512F-NEXT: vmovdqu (%rdx), %xmm1
1386 ; AVX512F-NEXT: vpor %xmm0, %xmm1, %xmm2
1387 ; AVX512F-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %k1
1388 ; AVX512F-NEXT: vpxor %xmm0, %xmm1, %xmm0
1389 ; AVX512F-NEXT: vmovdqa32 %zmm2, %zmm0 {%k1}
1390 ; AVX512F-NEXT: vmovdqu %xmm0, (%rdi)
1391 ; AVX512F-NEXT: vzeroupper
1392 ; AVX512F-NEXT: retq
1393 ;
1394 ; AVX512VL-LABEL: PR46531:
1395 ; AVX512VL: # %bb.0:
1396 ; AVX512VL-NEXT: vmovdqu (%rsi), %xmm0
1397 ; AVX512VL-NEXT: vmovdqu (%rdx), %xmm1
1398 ; AVX512VL-NEXT: vptestnmd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %k1
1399 ; AVX512VL-NEXT: vpxor %xmm0, %xmm1, %xmm2
1400 ; AVX512VL-NEXT: vpord %xmm0, %xmm1, %xmm2 {%k1}
1401 ; AVX512VL-NEXT: vmovdqu %xmm2, (%rdi)
1402 ; AVX512VL-NEXT: retq
1403 ;
1404 ; XOP-LABEL: PR46531:
1405 ; XOP: # %bb.0:
1406 ; XOP-NEXT: vmovdqu (%rsi), %xmm0
1407 ; XOP-NEXT: vmovdqu (%rdx), %xmm1
1408 ; XOP-NEXT: vpor %xmm0, %xmm1, %xmm2
1409 ; XOP-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm3
1410 ; XOP-NEXT: vpxor %xmm4, %xmm4, %xmm4
1411 ; XOP-NEXT: vpcomneqd %xmm4, %xmm3, %xmm3
1412 ; XOP-NEXT: vpxor %xmm0, %xmm1, %xmm0
1413 ; XOP-NEXT: vblendvps %xmm3, %xmm0, %xmm2, %xmm0
1414 ; XOP-NEXT: vmovups %xmm0, (%rdi)
1415 ; XOP-NEXT: retq
1416 %a = load <4 x i32>, ptr %y, align 4
1417 %b = load <4 x i32>, ptr %z, align 4
1418 %or = or <4 x i32> %b, %a
1419 %and = and <4 x i32> %b, <i32 1, i32 1, i32 1, i32 1>
1420 %cmp = icmp eq <4 x i32> %and, zeroinitializer
1421 %xor = xor <4 x i32> %b, %a
1422 %sel = select <4 x i1> %cmp, <4 x i32> %or, <4 x i32> %xor
1423 store <4 x i32> %sel, ptr %x, align 4
1424 ret void
1425 }
1427 attributes #0 = { "no-nans-fp-math"="true" }
1428 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
1429 ; AVX: {{.*}}