llvm/test/MC/AArch64/FP8_SVE2/fmlall-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+ssve-fp8fma  2>&1 < %s| FileCheck %s
   2
   3 // ------------------------------------------------------------------------- //
   4 // z register out of range for index
   5
   6 fmlallbb z0.s, z1.b, z8.b[0]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: fmlallbb z0.s, z1.b, z8.b[0]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 fmlallbt z0.s, z1.b, z8.b[0]
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  13 // CHECK-NEXT: fmlallbt z0.s, z1.b, z8.b[0]
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 fmlalltb z0.s, z1.b, z8.b[0]
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  18 // CHECK-NEXT: fmlalltb z0.s, z1.b, z8.b[0]
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 fmlalltt z0.s, z1.b, z8.b[0]
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  23 // CHECK-NEXT: fmlalltt z0.s, z1.b, z8.b[0]
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 // ------------------------------------------------------------------------- //
  27 // Index out of bounds
  28
  29 fmlallbb z0.s, z1.b, z7.b[-1]
  30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
  31 // CHECK-NEXT: fmlallbb z0.s, z1.b, z7.b[-1]
  32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  33
  34 fmlallbt z0.s, z1.b, z7.b[16]
  35 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
  36 // CHECK-NEXT: fmlallbt z0.s, z1.b, z7.b[16]
  37 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  38
  39 fmlalltb z0.s, z1.b, z7.b[-1]
  40 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
  41 // CHECK-NEXT: fmlalltb z0.s, z1.b, z7.b[-1]
  42 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  43
  44 fmlalltt z0.s, z1.b, z7.b[16]
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
  46 // CHECK-NEXT: fmlalltt z0.s, z1.b, z7.b[16]
  47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  48
  49 // ------------------------------------------------------------------------- //
  50 // Invalid element width
  51
  52 fmlallbb z0.h, z1.b, z2.b[0]
  53 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  54 // CHECK-NEXT: fmlallbb z0.h, z1.b, z2.b[0]
  55 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  56
  57 fmlallbt z0.h, z1.b, z2.b
  58 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  59 // CHECK-NEXT: fmlallbt  z0.h, z1.b, z2.b
  60 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  61
  62 fmlalltb z0.s, z1.h, z2.h[0]
  63 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  64 // CHECK-NEXT: fmlalltb z0.s, z1.h, z2.h[0]
  65 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  66
  67 fmlalltt z0.s, z1.h, z2.h
  68 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  69 // CHECK-NEXT: fmlalltt  z0.s, z1.h, z2.h
  70 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  71
  72 // --------------------------------------------------------------------------//
  73 // Negative tests for instructions that are incompatible with movprfx
  74
  75 movprfx z0.s, p0/z, z0.s
  76 fmlallbb  z0.s, z1.b, z7.b[0]
  77 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
  78 // CHECK-NEXT: fmlallbb  z0.s, z1.b, z7.b[0]
  79 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  80
  81 movprfx z29.s, p0/z, z7.s
  82 fmlalltt  z29.s, z30.b, z31.b
  83 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
  84 // CHECK-NEXT: fmlalltt  z29.s, z30.b, z31.b
  85 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: