llvm/test/MC/AArch64/SME/umops-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+sme-i16i64 2>&1 < %s| FileCheck %s
   2
   3 // ------------------------------------------------------------------------- //
   4 // Invalid tile
   5 //
   6 // expected: .s => za0-za3, .d => za0-za7
   7
   8 umops za4.s, p0/m, p0/m, z0.b, z0.b
   9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  10 // CHECK-NEXT: umops za4.s, p0/m, p0/m, z0.b, z0.b
  11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  12
  13 umops za8.d, p0/m, p0/m, z0.h, z0.h
  14 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  15 // CHECK-NEXT: umops za8.d, p0/m, p0/m, z0.h, z0.h
  16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  17
  18 // ------------------------------------------------------------------------- //
  19 // Invalid predicate (expected: p0-p7)
  20
  21 umops za0.s, p8/m, p0/m, z0.b, z0.b
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  23 // CHECK-NEXT: umops za0.s, p8/m, p0/m, z0.b, z0.b
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 umops za0.s, p0/m, p8/m, z0.b, z0.b
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  28 // CHECK-NEXT: umops za0.s, p0/m, p8/m, z0.b, z0.b
  29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  30
  31 umops za0.d, p8/m, p0/m, z0.h, z0.h
  32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  33 // CHECK-NEXT: umops za0.d, p8/m, p0/m, z0.h, z0.h
  34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  35
  36 umops za0.d, p0/m, p8/m, z0.h, z0.h
  37 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  38 // CHECK-NEXT: umops za0.d, p0/m, p8/m, z0.h, z0.h
  39 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  40
  41 // ------------------------------------------------------------------------- //
  42 // Invalid predicate qualifier (expected: /m)
  43
  44 umops za0.s, p0/z, p0/m, z0.b, z0.b
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  46 // CHECK-NEXT: umops za0.s, p0/z, p0/m, z0.b, z0.b
  47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  48
  49 umops za0.s, p0/m, p0/z, z0.b, z0.b
  50 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  51 // CHECK-NEXT: umops za0.s, p0/m, p0/z, z0.b, z0.b
  52 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  53
  54 umops za0.d, p0/z, p0/m, z0.h, z0.h
  55 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  56 // CHECK-NEXT: umops za0.d, p0/z, p0/m, z0.h, z0.h
  57 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  58
  59 umops za0.d, p0/m, p0/z, z0.h, z0.h
  60 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  61 // CHECK-NEXT: umops za0.d, p0/m, p0/z, z0.h, z0.h
  62 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  63
  64 // ------------------------------------------------------------------------- //
  65 // Invalid ZPR type suffix
  66 //
  67 // expected: .s => .b, .d => .h
  68
  69 umops za0.s, p0/m, p0/m, z0.h, z0.b
  70 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  71 // CHECK-NEXT: umops za0.s, p0/m, p0/m, z0.h, z0.b
  72 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  73
  74 umops za0.s, p0/m, p0/m, z0.b, z0.s
  75 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  76 // CHECK-NEXT: umops za0.s, p0/m, p0/m, z0.b, z0.s
  77 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  78
  79 umops za0.d, p0/m, p0/m, z0.b, z0.h
  80 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  81 // CHECK-NEXT: umops za0.d, p0/m, p0/m, z0.b, z0.h
  82 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  83
  84 umops za0.d, p0/m, p0/m, z0.h, z0.s
  85 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  86 // CHECK-NEXT: umops za0.d, p0/m, p0/m, z0.h, z0.s
  87 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: