llvm/test/MC/AArch64/SME2/bfdot-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 bfdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: bfdot za.s[w8, 0, vgx2], {z0.h-z2.h}, z0.h[0]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 bfdot za.s[w8, 0, vgx4], {z1.h-z5.h}, z0.h
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  13 // CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z1.h-z5.h}, z0.h
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 bfdot za.s[w8, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  18 // CHECK-NEXT: bfdot za.s[w8, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 // --------------------------------------------------------------------------//
  22 // Invalid single vector register
  23
  24 bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z16.h
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  26 // CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z16.h
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  28
  29 // --------------------------------------------------------------------------//
  30 // Invalid vector select register
  31
  32 bfdot za.s[w7, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
  33 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  34 // CHECK-NEXT: bfdot za.s[w7, 0, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
  35 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  36
  37 bfdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
  38 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  39 // CHECK-NEXT: bfdot za.s[w12, 0, vgx4], {z0.h-z3.h}, z0.h[0]
  40 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  41
  42 // --------------------------------------------------------------------------//
  43 // Invalid vector select offset
  44
  45 bfdot za.s[w8, -1, vgx4], {z0.h-z3.h}, z0.h[0]
  46 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
  47 // CHECK-NEXT: bfdot za.s[w8, -1, vgx4], {z0.h-z3.h}, z0.h[0]
  48 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  49
  50 bfdot za.s[w8, 8, vgx4], {z0.h-z3.h}, z0.h[0]
  51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
  52 // CHECK-NEXT: bfdot za.s[w8, 8, vgx4], {z0.h-z3.h}, z0.h[0]
  53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  54
  55 bfdot za.s[w8, -1, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
  56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
  57 // CHECK-NEXT: bfdot za.s[w8, -1, vgx2], {z0.h-z1.h}, {z3.h-z4.h}
  58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  59
  60 // --------------------------------------------------------------------------//
  61 // Invalid Register Suffix
  62
  63 bfdot za.h[w8, 0, vgx4], {z0.h-z3.h}, z0.h[0]
  64 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
  65 // CHECK-NEXT: bfdot za.h[w8, 0, vgx4], {z0.h-z3.h}, z0.h[0]
  66 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  67
  68 // --------------------------------------------------------------------------//
  69 // Invalid vector lane index
  70
  71 bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[4]
  72 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
  73 // CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[4]
  74 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  75
  76 bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[-1]
  77 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
  78 // CHECK-NEXT: bfdot za.s[w8, 0, vgx4], {z0.h-z3.h}, z0.h[-1]
  79 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: