llvm/test/MC/AArch64/SME2/smax-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 smax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: smax {z0.h, z1.h}, {z0.h-z2.h}, z0.h
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 smax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element type
  13 // CHECK-NEXT: smax {z1.d-z2.d}, {z0.d, z1.d}, z0.d
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 // --------------------------------------------------------------------------//
  17 // Invalid single register
  18
  19 smax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
  20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
  21 // CHECK-NEXT: smax {z0.b, z1.b}, {z2.b-z3.b}, z31.b
  22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  23
  24 // --------------------------------------------------------------------------//
  25 // Invalid Register Suffix
  26
  27 smax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
  28 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
  29 // CHECK-NEXT: smax {z0.b, z1.b}, {z2.b-z3.b}, z14.d
  30 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: