llvm/test/MC/AArch64/SME2/sqcvt-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 sqcvt z0.h, {z0.s-z2.s}
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: sqcvt z0.h, {z0.s-z2.s}
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 sqcvt z0.b, {z1.s-z4.s}
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element type
  13 // CHECK-NEXT: sqcvt z0.b, {z1.s-z4.s}
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 sqcvt z0.h, {z1.d-z2.d}
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  18 // CHECK-NEXT: sqcvt z0.h, {z1.d-z2.d}
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 // --------------------------------------------------------------------------//
  22 // Invalid Register Suffix
  23
  24 sqcvt z0.s, {z0.s-z1.s}
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  26 // CHECK-NEXT: sqcvt z0.s, {z0.s-z1.s}
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: