llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 sqdmulh {z0.h-z2.h}, {z0.h-z1.h}, z0.h
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: sqdmulh {z0.h-z2.h}, {z0.h-z1.h}, z0.h
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 sqdmulh {z28.s-z31.s}, {z0.s-z4.s}, z15.s
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  13 // CHECK-NEXT: sqdmulh {z28.s-z31.s}, {z0.s-z4.s}, z15.s
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 sqdmulh {z1.d-z4.d}, {z0.d-z3.d}, z0.d
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
  18 // CHECK-NEXT: sqdmulh {z1.d-z4.d}, {z0.d-z3.d}, z0.d
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 sqdmulh {z28.b-z29.b}, {z1.b-z2.b}, z15.b
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  23 // CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z1.b-z2.b}, z15.b
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  28 // CHECK-NEXT: sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b
  29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  30
  31 sqdmulh {z1.d-z4.d}, {z1.d-z4.d}, {z8.d-z11.d}
  32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
  33 // CHECK-NEXT: sqdmulh {z1.d-z4.d}, {z1.d-z4.d}, {z8.d-z11.d}
  34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  35
  36 sqdmulh {z1.d-z2.d}, {z1.d-z2.d}, {z2.d-z3.d}
  37 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  38 // CHECK-NEXT: sqdmulh {z1.d-z2.d}, {z1.d-z2.d}, {z2.d-z3.d}
  39 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}
  40
  41 // --------------------------------------------------------------------------//
  42 // Invalid single vector register
  43
  44 sqdmulh {z28.b-z29.b}, {z0.b-z1.b}, z16.b
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
  46 // CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z0.b-z1.b}, z16.b
  47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  48
  49 // --------------------------------------------------------------------------//
  50 // Invalid register suffix
  51
  52 sqdmulh {z0.d-z3.d}, {z0.d-z3.d}, z0.b
  53 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
  54 // CHECK-NEXT: sqdmulh {z0.d-z3.d}, {z0.d-z3.d}, z0.b
  55 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  56
  57 sqdmulh {z0.d-z3.h}, {z0.d-z3.d}, z0.b
  58 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
  59 // CHECK-NEXT: sqdmulh {z0.d-z3.h}, {z0.d-z3.d}, z0.b
  60 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  61
  62 // --------------------------------------------------------------------------//
  63 // The tied operands must match, even for vector groups.
  64
  65 sqdmulh {z0.s-z1.s}, {z2.s-z3.s}, z15.s
  66 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
  67 // CHECK-NEXT: sqdmulh {z0.s-z1.s}, {z2.s-z3.s}, z15.s
  68 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  69
  70 sqdmulh {z0.s,z1.s}, {z2.s,z3.s}, z15.s
  71 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
  72 // CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z2.s,z3.s}, z15.s
  73 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  74
  75 sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s
  76 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  77 // CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s
  78 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  79
  80 sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
  81 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  82 // CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
  83 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  84
  85 sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s
  86 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  87 // CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s
  88 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  89
  90 sqdmulh {z2.d,z3.d}, {z0.d,z1.d}, {z4.d,z5.d}
  91 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
  92 // CHECK-NEXT: sqdmulh {z2.d,z3.d}, {z0.d,z1.d}, {z4.d,z5.d}
  93 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  94
  95 sqdmulh {z0.d-z3.d}, {z4.d-z7.d}, {z0.d-z3.d}
  96 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
  97 // CHECK-NEXT: sqdmulh {z0.d-z3.d}, {z4.d-z7.d}, {z0.d-z3.d}
  98 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: