llvm/test/MC/AArch64/SME2/srshl-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 srshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: srshl {z0.h-z2.h}, {z0.h-z1.h}, z0.h
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 srshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  13 // CHECK-NEXT: srshl {z0.s-z1.s}, {z2.s-z4.s}, z0.s
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 srshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  18 // CHECK-NEXT: srshl {z20.d-z23.d}, {z20.d-z23.d}, {z8.d-z12.d}
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 srshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  23 // CHECK-NEXT: srshl {z29.b-z30.b}, {z30.b-z31.b}, z15.b
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 srshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
  27 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
  28 // CHECK-NEXT: srshl {z20.h-z23.h}, {z21.h-z24.h}, {z8.h-z11.h}
  29 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  30
  31 srshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
  32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
  33 // CHECK-NEXT: srshl {z28.b-z31.b}, {z28.b-z31.b}, {z27.b-z30.b}
  34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  35
  36 // --------------------------------------------------------------------------//
  37 // Invalid Single Register
  38
  39 srshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
  40 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  41 // CHECK-NEXT: srshl {z20.h-z21.h}, {z20.h-z21.h}, z16.h
  42 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  43
  44 // --------------------------------------------------------------------------//
  45 // Invalid Register Suffix
  46
  47 srshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
  48 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
  49 // CHECK-NEXT: srshl {z0.d-z3.d}, {z0.d-z3.d}, z0.s
  50 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: