llvm/test/MC/AArch64/SME2/umlsll-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 umlsll za.d[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: umlsll za.d[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 umlsll za.d[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  13 // CHECK-NEXT: umlsll za.d[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 umlsll za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
  18 // CHECK-NEXT: umlsll za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 // --------------------------------------------------------------------------//
  22 // Invalid indexed-vector register
  23
  24 umlsll za.s[w10, 0:3], z19.b, z4.s[4]
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
  26 // CHECK-NEXT: umlsll za.s[w10, 0:3], z19.b, z4.s[4]
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  28
  29 umlsll za.d[w10, 4:7], z10.h, z30.h[1]
  30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
  31 // CHECK-NEXT: umlsll za.d[w10, 4:7], z10.h, z30.h[1]
  32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  33
  34 // --------------------------------------------------------------------------//
  35 // Invalid vector select register
  36
  37 umlsll za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  38 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  39 // CHECK-NEXT: umlsll za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  40 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  41
  42 umlsll za.d[w12, 6:7, vgx2], {z12.h-z13.h}, z2.h[0]
  43 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  44 // CHECK-NEXT: umlsll za.d[w12, 6:7, vgx2], {z12.h-z13.h}, z2.h[0]
  45 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  46
  47 // --------------------------------------------------------------------------//
  48 // Invalid vector select offset
  49
  50 umlsll za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
  51 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  52 // CHECK-NEXT: umlsll za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
  53 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  54
  55 umlsll za.d[w8, 5:8, vgx2], {z22.h-z23.h}, z14.h[2]
  56 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 4 in the range [0, 4] or [0, 12] depending on the instruction, and the second immediate is immf + 3.
  57 // CHECK-NEXT: umlsll za.d[w8, 5:8, vgx2], {z22.h-z23.h}, z14.h[2]
  58 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  59
  60 // --------------------------------------------------------------------------//
  61 // Invalid Register Suffix
  62
  63 umlsll za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  64 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
  65 // CHECK-NEXT: umlsll za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
  66 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  67
  68 // --------------------------------------------------------------------------//
  69 // Invalid vector lane index
  70
  71 umlsll  za.s[w8, 0:3], {z0.b-z3.b}, z0.b[16]
  72 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
  73 // CHECK-NEXT: umlsll  za.s[w8, 0:3], {z0.b-z3.b}, z0.b[16]
  74 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: