llvm/test/MC/AArch64/SME2/usvdot-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
   2 // --------------------------------------------------------------------------//
   3 // Out of range index offset
   4
   5 usvdot za.s[w8, 8, vgx4], {z0.b-z3.b}, z0.b[0]
   6 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
   7 // CHECK-NEXT: usvdot za.s[w8, 8, vgx4], {z0.b-z3.b}, z0.b[0]
   8 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
   9
  10 usvdot za.s[w8, -1, vgx4], {z0.b-z3.b}, z0.b[0]
  11 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
  12 // CHECK-NEXT: usvdot za.s[w8, -1, vgx4], {z0.b-z3.b}, z0.b[0]
  13 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  14
  15 // --------------------------------------------------------------------------//
  16 // Invalid vector select register
  17
  18 usvdot za.s[w7, 0, vgx4], {z4.b-z7.b}, z0.b[3]
  19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  20 // CHECK-NEXT: usvdot za.s[w7, 0, vgx4], {z4.b-z7.b}, z0.b[3]
  21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  22
  23 usvdot za.s[w12, 0, vgx2], {z4.b-z5.b}, z0.b[3]
  24 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
  25 // CHECK-NEXT: usvdot za.s[w12, 0, vgx2], {z4.b-z5.b}, z0.b[3]
  26 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  27
  28 // --------------------------------------------------------------------------//
  29 // Invalid vector list
  30
  31 usvdot za.s[w8, 0, vgx4], {z0.b-z4.b}, z0.b[3]
  32 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  33 // CHECK-NEXT: usvdot za.s[w8, 0, vgx4], {z0.b-z4.b}, z0.b[3]
  34 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  35
  36 usvdot za.s[w8, 0, vgx4], {z1.b-z4.b}, z15.b[0]
  37 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
  38 // CHECK-NEXT: usvdot za.s[w8, 0, vgx4], {z1.b-z4.b}, z15.b[0]
  39 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  40
  41 // --------------------------------------------------------------------------//
  42 // Invalid Matrix Operand
  43
  44 usvdot za.h[w8, 0, vgx4], {z0.b-z3.b}, z4.b[7]
  45 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
  46 // CHECK-NEXT: usvdot za.h[w8, 0, vgx4], {z0.b-z3.b}, z4.b[7]
  47 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  48
  49 // --------------------------------------------------------------------------//
  50 // Invalid vector grouping
  51
  52 usvdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z14.b[3]
  53 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  54 // CHECK-NEXT: usvdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z14.b[3]
  55 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  56
  57 // --------------------------------------------------------------------------//
  58 // Invalid lane index
  59
  60 usvdot za.s[w8, 0, vgx4], {z0.b-z3.b}, z14.b[16]
  61 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3]
  62 // CHECK-NEXT: usvdot za.s[w8, 0, vgx4], {z0.b-z3.b}, z14.b[16]
  63 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: