llvm/test/MC/AArch64/SME2/uunpk-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid vector list
   5
   6 uunpk {z0.h-z2.h}, z0.b
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
   8 // CHECK-NEXT: uunpk {z0.h-z2.h}, z0.b
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 uunpk {z1.s-z2.s}, z0.h
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
  13 // CHECK-NEXT: uunpk {z1.s-z2.s}, z0.h
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 uunpk {z0.d-z5.d}, {z8.s-z9.s}
  17 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
  18 // CHECK-NEXT: uunpk {z0.d-z5.d}, {z8.s-z9.s}
  19 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  20
  21 uunpk {z0.s-z3.s}, {z9.h-z11.h}
  22 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  23 // CHECK-NEXT: uunpk {z0.s-z3.s}, {z9.h-z11.h}
  24 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  25
  26 // --------------------------------------------------------------------------//
  27 // Invalid Register Suffix
  28
  29 uunpk {z0.s-z3.s}, {z8.s-z9.s}
  30 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  31 // CHECK-NEXT: uunpk {z0.s-z3.s}, {z8.s-z9.s}
  32 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: