llvm/test/MC/AArch64/SVE/matrix-multiply-fp64.s

   1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve,+f64mm < %s \
   2 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
   3 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
   4 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
   5 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+f64mm < %s \
   6 // RUN:        | llvm-objdump --no-print-imm-hex -d --mattr=+sve,+f64mm - | FileCheck %s --check-prefix=CHECK-INST
   7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve,+f64mm < %s \
   8 // RUN:   | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
   9
  10 // --------------------------------------------------------------------------//
  11 // FMMLA (SVE)
  12
  13 fmmla z0.d, z1.d, z2.d
  14 // CHECK-INST: fmmla z0.d, z1.d, z2.d
  15 // CHECK-ENCODING: [0x20,0xe4,0xe2,0x64]
  16 // CHECK-ERROR: instruction requires: f64mm sve
  17 // CHECK-UNKNOWN: 64e2e420 <unknown>
  18
  19 // --------------------------------------------------------------------------//
  20 // LD1RO (SVE, scalar plus immediate)
  21
  22 // With maximum immediate (224)
  23
  24 ld1rob { z0.b }, p1/z, [x2, #224]
  25 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, #224]
  26 // CHECK-ENCODING: [0x40,0x24,0x27,0xa4]
  27 // CHECK-ERROR: instruction requires: f64mm sve
  28 // CHECK-UNKNOWN: a4272440 <unknown>
  29
  30 ld1roh { z0.h }, p1/z, [x2, #224]
  31 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, #224]
  32 // CHECK-ENCODING: [0x40,0x24,0xa7,0xa4]
  33 // CHECK-ERROR: instruction requires: f64mm sve
  34 // CHECK-UNKNOWN: a4a72440 <unknown>
  35
  36 ld1row { z0.s }, p1/z, [x2, #224]
  37 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, #224]
  38 // CHECK-ENCODING: [0x40,0x24,0x27,0xa5]
  39 // CHECK-ERROR: instruction requires: f64mm sve
  40 // CHECK-UNKNOWN: a5272440 <unknown>
  41
  42 ld1rod { z0.d }, p1/z, [x2, #224]
  43 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, #224]
  44 // CHECK-ENCODING: [0x40,0x24,0xa7,0xa5]
  45 // CHECK-ERROR: instruction requires: f64mm sve
  46 // CHECK-UNKNOWN: a5a72440 <unknown>
  47
  48 // With minimum immediate (-256)
  49
  50 ld1rob { z0.b }, p1/z, [x2, #-256]
  51 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, #-256]
  52 // CHECK-ENCODING: [0x40,0x24,0x28,0xa4]
  53 // CHECK-ERROR: instruction requires: f64mm sve
  54 // CHECK-UNKNOWN: a4282440 <unknown>
  55
  56 ld1roh { z0.h }, p1/z, [x2, #-256]
  57 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, #-256]
  58 // CHECK-ENCODING: [0x40,0x24,0xa8,0xa4]
  59 // CHECK-ERROR: instruction requires: f64mm sve
  60 // CHECK-UNKNOWN: a4a82440 <unknown>
  61
  62 ld1row { z0.s }, p1/z, [x2, #-256]
  63 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, #-256]
  64 // CHECK-ENCODING: [0x40,0x24,0x28,0xa5]
  65 // CHECK-ERROR: instruction requires: f64mm sve
  66 // CHECK-UNKNOWN: a5282440 <unknown>
  67
  68 ld1rod { z0.d }, p1/z, [x2, #-256]
  69 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, #-256]
  70 // CHECK-ENCODING: [0x40,0x24,0xa8,0xa5]
  71 // CHECK-ERROR: instruction requires: f64mm sve
  72 // CHECK-UNKNOWN: a5a82440 <unknown>
  73
  74 // Aliases with a vector first operand, and omitted offset.
  75
  76 ld1rob { z0.b }, p1/z, [x2]
  77 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2]
  78 // CHECK-ENCODING: [0x40,0x24,0x20,0xa4]
  79 // CHECK-ERROR: instruction requires: f64mm sve
  80 // CHECK-UNKNOWN: a4202440 <unknown>
  81
  82 ld1roh { z0.h }, p1/z, [x2]
  83 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2]
  84 // CHECK-ENCODING: [0x40,0x24,0xa0,0xa4]
  85 // CHECK-ERROR: instruction requires: f64mm sve
  86 // CHECK-UNKNOWN: a4a02440 <unknown>
  87
  88 ld1row { z0.s }, p1/z, [x2]
  89 // CHECK-INST: ld1row { z0.s }, p1/z, [x2]
  90 // CHECK-ENCODING: [0x40,0x24,0x20,0xa5]
  91 // CHECK-ERROR: instruction requires: f64mm sve
  92 // CHECK-UNKNOWN: a5202440 <unknown>
  93
  94 ld1rod { z0.d }, p1/z, [x2]
  95 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2]
  96 // CHECK-ENCODING: [0x40,0x24,0xa0,0xa5]
  97 // CHECK-ERROR: instruction requires: f64mm sve
  98 // CHECK-UNKNOWN: a5a02440 <unknown>
  99
 100 // Aliases with a plain (non-list) first operand, and omitted offset.
 101
 102 ld1rob z0.b, p1/z, [x2]
 103 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2]
 104 // CHECK-ENCODING: [0x40,0x24,0x20,0xa4]
 105 // CHECK-ERROR: instruction requires: f64mm sve
 106 // CHECK-UNKNOWN: a4202440 <unknown>
 107
 108 ld1roh z0.h, p1/z, [x2]
 109 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2]
 110 // CHECK-ENCODING: [0x40,0x24,0xa0,0xa4]
 111 // CHECK-ERROR: instruction requires: f64mm sve
 112 // CHECK-UNKNOWN: a4a02440 <unknown>
 113
 114 ld1row z0.s, p1/z, [x2]
 115 // CHECK-INST: ld1row { z0.s }, p1/z, [x2]
 116 // CHECK-ENCODING: [0x40,0x24,0x20,0xa5]
 117 // CHECK-ERROR: instruction requires: f64mm sve
 118 // CHECK-UNKNOWN: a5202440 <unknown>
 119
 120 ld1rod z0.d, p1/z, [x2]
 121 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2]
 122 // CHECK-ENCODING: [0x40,0x24,0xa0,0xa5]
 123 // CHECK-ERROR: instruction requires: f64mm sve
 124 // CHECK-UNKNOWN: a5a02440 <unknown>
 125
 126 // Aliases with a plain (non-list) first operand, plus offset.
 127
 128 // With maximum immediate (224)
 129
 130 ld1rob z0.b, p1/z, [x2, #224]
 131 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, #224]
 132 // CHECK-ENCODING: [0x40,0x24,0x27,0xa4]
 133 // CHECK-ERROR: instruction requires: f64mm sve
 134 // CHECK-UNKNOWN: a4272440 <unknown>
 135
 136 ld1roh z0.h, p1/z, [x2, #224]
 137 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, #224]
 138 // CHECK-ENCODING: [0x40,0x24,0xa7,0xa4]
 139 // CHECK-ERROR: instruction requires: f64mm sve
 140 // CHECK-UNKNOWN: a4a72440 <unknown>
 141
 142 ld1row z0.s, p1/z, [x2, #224]
 143 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, #224]
 144 // CHECK-ENCODING: [0x40,0x24,0x27,0xa5]
 145 // CHECK-ERROR: instruction requires: f64mm sve
 146 // CHECK-UNKNOWN: a5272440 <unknown>
 147
 148 ld1rod z0.d, p1/z, [x2, #224]
 149 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, #224]
 150 // CHECK-ENCODING: [0x40,0x24,0xa7,0xa5]
 151 // CHECK-ERROR: instruction requires: f64mm sve
 152 // CHECK-UNKNOWN: a5a72440 <unknown>
 153
 154 // With minimum immediate (-256)
 155
 156 ld1rob z0.b, p1/z, [x2, #-256]
 157 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, #-256]
 158 // CHECK-ENCODING: [0x40,0x24,0x28,0xa4]
 159 // CHECK-ERROR: instruction requires: f64mm sve
 160 // CHECK-UNKNOWN: a4282440 <unknown>
 161
 162 ld1roh z0.h, p1/z, [x2, #-256]
 163 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, #-256]
 164 // CHECK-ENCODING: [0x40,0x24,0xa8,0xa4]
 165 // CHECK-ERROR: instruction requires: f64mm sve
 166 // CHECK-UNKNOWN: a4a82440 <unknown>
 167
 168 ld1row z0.s, p1/z, [x2, #-256]
 169 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, #-256]
 170 // CHECK-ENCODING: [0x40,0x24,0x28,0xa5]
 171 // CHECK-ERROR: instruction requires: f64mm sve
 172 // CHECK-UNKNOWN: a5282440 <unknown>
 173
 174 ld1rod z0.d, p1/z, [x2, #-256]
 175 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, #-256]
 176 // CHECK-ENCODING: [0x40,0x24,0xa8,0xa5]
 177 // CHECK-ERROR: instruction requires: f64mm sve
 178 // CHECK-UNKNOWN: a5a82440 <unknown>
 179
 180
 181 // --------------------------------------------------------------------------//
 182 // LD1RO (SVE, scalar plus scalar)
 183
 184 ld1rob { z0.b }, p1/z, [x2, x3, lsl #0]
 185 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, x3]
 186 // CHECK-ENCODING: [0x40,0x04,0x23,0xa4]
 187 // CHECK-ERROR: instruction requires: f64mm sve
 188 // CHECK-UNKNOWN: a4230440 <unknown>
 189
 190 ld1roh { z0.h }, p1/z, [x2, x3, lsl #1]
 191 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, x3, lsl #1]
 192 // CHECK-ENCODING: [0x40,0x04,0xa3,0xa4]
 193 // CHECK-ERROR: instruction requires: f64mm sve
 194 // CHECK-UNKNOWN: a4a30440 <unknown>
 195
 196 ld1row { z0.s }, p1/z, [x2, x3, lsl #2]
 197 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, x3, lsl #2]
 198 // CHECK-ENCODING: [0x40,0x04,0x23,0xa5]
 199 // CHECK-ERROR: instruction requires: f64mm sve
 200 // CHECK-UNKNOWN: a5230440 <unknown>
 201
 202 ld1rod { z0.d }, p1/z, [x2, x3, lsl #3]
 203 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, x3, lsl #3]
 204 // CHECK-ENCODING: [0x40,0x04,0xa3,0xa5]
 205 // CHECK-ERROR: instruction requires: f64mm sve
 206 // CHECK-UNKNOWN: a5a30440 <unknown>
 207
 208 // Aliases with a plain (non-list) first operand, and omitted shift for the
 209 // byte variant.
 210
 211 ld1rob z0.b, p1/z, [x2, x3]
 212 // CHECK-INST: ld1rob { z0.b }, p1/z, [x2, x3]
 213 // CHECK-ENCODING: [0x40,0x04,0x23,0xa4]
 214 // CHECK-ERROR: instruction requires: f64mm sve
 215 // CHECK-UNKNOWN: a4230440 <unknown>
 216
 217 ld1roh z0.h, p1/z, [x2, x3, lsl #1]
 218 // CHECK-INST: ld1roh { z0.h }, p1/z, [x2, x3, lsl #1]
 219 // CHECK-ENCODING: [0x40,0x04,0xa3,0xa4]
 220 // CHECK-ERROR: instruction requires: f64mm sve
 221 // CHECK-UNKNOWN: a4a30440 <unknown>
 222
 223 ld1row z0.s, p1/z, [x2, x3, lsl #2]
 224 // CHECK-INST: ld1row { z0.s }, p1/z, [x2, x3, lsl #2]
 225 // CHECK-ENCODING: [0x40,0x04,0x23,0xa5]
 226 // CHECK-ERROR: instruction requires: f64mm sve
 227 // CHECK-UNKNOWN: a5230440 <unknown>
 228
 229 ld1rod z0.d, p1/z, [x2, x3, lsl #3]
 230 // CHECK-INST: ld1rod { z0.d }, p1/z, [x2, x3, lsl #3]
 231 // CHECK-ENCODING: [0x40,0x04,0xa3,0xa5]
 232 // CHECK-ERROR: instruction requires: f64mm sve
 233 // CHECK-UNKNOWN: a5a30440 <unknown>
 234
 235
 236 // --------------------------------------------------------------------------//
 237 // ZIP1, ZIP2 (SVE, 128-bit element)
 238
 239 zip1 z0.q, z1.q, z2.q
 240 // CHECK-INST: zip1 z0.q, z1.q, z2.q
 241 // CHECK-ENCODING: [0x20,0x00,0xa2,0x05]
 242 // CHECK-ERROR: instruction requires: f64mm sve or sme
 243 // CHECK-UNKNOWN: 05a20020 <unknown>
 244
 245 zip2 z0.q, z1.q, z2.q
 246 // CHECK-INST: zip2 z0.q, z1.q, z2.q
 247 // CHECK-ENCODING: [0x20,0x04,0xa2,0x05]
 248 // CHECK-ERROR: instruction requires: f64mm sve or sme
 249 // CHECK-UNKNOWN: 05a20420 <unknown>
 250
 251
 252 // --------------------------------------------------------------------------//
 253 // UZP1, UZP2 (SVE, 128-bit element)
 254
 255 uzp1 z0.q, z1.q, z2.q
 256 // CHECK-INST: uzp1 z0.q, z1.q, z2.q
 257 // CHECK-ENCODING: [0x20,0x08,0xa2,0x05]
 258 // CHECK-ERROR: instruction requires: f64mm sve or sme
 259 // CHECK-UNKNOWN: 05a20820 <unknown>
 260
 261 uzp2 z0.q, z1.q, z2.q
 262 // CHECK-INST: uzp2 z0.q, z1.q, z2.q
 263 // CHECK-ENCODING: [0x20,0x0c,0xa2,0x05]
 264 // CHECK-ERROR: instruction requires: f64mm sve or sme
 265 // CHECK-UNKNOWN: 05a20c20 <unknown>
 266
 267
 268 // --------------------------------------------------------------------------//
 269 // TRN1, TRN2 (SVE, 128-bit element)
 270
 271 trn1 z0.q, z1.q, z2.q
 272 // CHECK-INST: trn1 z0.q, z1.q, z2.q
 273 // CHECK-ENCODING: [0x20,0x18,0xa2,0x05]
 274 // CHECK-ERROR: instruction requires: f64mm sve or sme
 275 // CHECK-UNKNOWN: 05a21820 <unknown>
 276
 277 trn2 z0.q, z1.q, z2.q
 278 // CHECK-INST: trn2 z0.q, z1.q, z2.q
 279 // CHECK-ENCODING: [0x20,0x1c,0xa2,0x05]
 280 // CHECK-ERROR: instruction requires: f64mm sve or sme
 281 // CHECK-UNKNOWN: 05a21c20 <unknown>