llvm/test/MC/AArch64/SVE/sqincw.s

   1 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
   2 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
   3 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
   4 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
   5 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
   6 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
   7 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
   8 // RUN:        | llvm-objdump --no-print-imm-hex -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
   9 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
  10 // RUN:   | llvm-objdump --no-print-imm-hex -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN
  11
  12 // ---------------------------------------------------------------------------//
  13 // Test 64-bit form (x0) and its aliases
  14 // ---------------------------------------------------------------------------//
  15
  16 sqincw  x0
  17 // CHECK-INST: sqincw  x0
  18 // CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
  19 // CHECK-ERROR: instruction requires: sve or sme
  20 // CHECK-UNKNOWN: 04b0f3e0 <unknown>
  21
  22 sqincw  x0, all
  23 // CHECK-INST: sqincw  x0
  24 // CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
  25 // CHECK-ERROR: instruction requires: sve or sme
  26 // CHECK-UNKNOWN: 04b0f3e0 <unknown>
  27
  28 sqincw  x0, all, mul #1
  29 // CHECK-INST: sqincw  x0
  30 // CHECK-ENCODING: [0xe0,0xf3,0xb0,0x04]
  31 // CHECK-ERROR: instruction requires: sve or sme
  32 // CHECK-UNKNOWN: 04b0f3e0 <unknown>
  33
  34 sqincw  x0, all, mul #16
  35 // CHECK-INST: sqincw  x0, all, mul #16
  36 // CHECK-ENCODING: [0xe0,0xf3,0xbf,0x04]
  37 // CHECK-ERROR: instruction requires: sve or sme
  38 // CHECK-UNKNOWN: 04bff3e0 <unknown>
  39
  40
  41 // ---------------------------------------------------------------------------//
  42 // Test 32-bit form (x0, w0) and its aliases
  43 // ---------------------------------------------------------------------------//
  44
  45 sqincw  x0, w0
  46 // CHECK-INST: sqincw  x0, w0
  47 // CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
  48 // CHECK-ERROR: instruction requires: sve or sme
  49 // CHECK-UNKNOWN: 04a0f3e0 <unknown>
  50
  51 sqincw  x0, w0, all
  52 // CHECK-INST: sqincw  x0, w0
  53 // CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
  54 // CHECK-ERROR: instruction requires: sve or sme
  55 // CHECK-UNKNOWN: 04a0f3e0 <unknown>
  56
  57 sqincw  x0, w0, all, mul #1
  58 // CHECK-INST: sqincw  x0, w0
  59 // CHECK-ENCODING: [0xe0,0xf3,0xa0,0x04]
  60 // CHECK-ERROR: instruction requires: sve or sme
  61 // CHECK-UNKNOWN: 04a0f3e0 <unknown>
  62
  63 sqincw  x0, w0, all, mul #16
  64 // CHECK-INST: sqincw  x0, w0, all, mul #16
  65 // CHECK-ENCODING: [0xe0,0xf3,0xaf,0x04]
  66 // CHECK-ERROR: instruction requires: sve or sme
  67 // CHECK-UNKNOWN: 04aff3e0 <unknown>
  68
  69 sqincw  x0, w0, pow2
  70 // CHECK-INST: sqincw  x0, w0, pow2
  71 // CHECK-ENCODING: [0x00,0xf0,0xa0,0x04]
  72 // CHECK-ERROR: instruction requires: sve or sme
  73 // CHECK-UNKNOWN: 04a0f000 <unknown>
  74
  75 sqincw  x0, w0, pow2, mul #16
  76 // CHECK-INST: sqincw  x0, w0, pow2, mul #16
  77 // CHECK-ENCODING: [0x00,0xf0,0xaf,0x04]
  78 // CHECK-ERROR: instruction requires: sve or sme
  79 // CHECK-UNKNOWN: 04aff000 <unknown>
  80
  81
  82 // ---------------------------------------------------------------------------//
  83 // Test vector form and aliases.
  84 // ---------------------------------------------------------------------------//
  85 sqincw  z0.s
  86 // CHECK-INST: sqincw  z0.s
  87 // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
  88 // CHECK-ERROR: instruction requires: sve or sme
  89 // CHECK-UNKNOWN: 04a0c3e0 <unknown>
  90
  91 sqincw  z0.s, all
  92 // CHECK-INST: sqincw  z0.s
  93 // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
  94 // CHECK-ERROR: instruction requires: sve or sme
  95 // CHECK-UNKNOWN: 04a0c3e0 <unknown>
  96
  97 sqincw  z0.s, all, mul #1
  98 // CHECK-INST: sqincw  z0.s
  99 // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
 100 // CHECK-ERROR: instruction requires: sve or sme
 101 // CHECK-UNKNOWN: 04a0c3e0 <unknown>
 102
 103 sqincw  z0.s, all, mul #16
 104 // CHECK-INST: sqincw  z0.s, all, mul #16
 105 // CHECK-ENCODING: [0xe0,0xc3,0xaf,0x04]
 106 // CHECK-ERROR: instruction requires: sve or sme
 107 // CHECK-UNKNOWN: 04afc3e0 <unknown>
 108
 109 sqincw  z0.s, pow2
 110 // CHECK-INST: sqincw  z0.s, pow2
 111 // CHECK-ENCODING: [0x00,0xc0,0xa0,0x04]
 112 // CHECK-ERROR: instruction requires: sve or sme
 113 // CHECK-UNKNOWN: 04a0c000 <unknown>
 114
 115 sqincw  z0.s, pow2, mul #16
 116 // CHECK-INST: sqincw  z0.s, pow2, mul #16
 117 // CHECK-ENCODING: [0x00,0xc0,0xaf,0x04]
 118 // CHECK-ERROR: instruction requires: sve or sme
 119 // CHECK-UNKNOWN: 04afc000 <unknown>
 120
 121
 122 // ---------------------------------------------------------------------------//
 123 // Test all patterns for 64-bit form
 124 // ---------------------------------------------------------------------------//
 125
 126 sqincw  x0, pow2
 127 // CHECK-INST: sqincw  x0, pow2
 128 // CHECK-ENCODING: [0x00,0xf0,0xb0,0x04]
 129 // CHECK-ERROR: instruction requires: sve or sme
 130 // CHECK-UNKNOWN: 04b0f000 <unknown>
 131
 132 sqincw  x0, vl1
 133 // CHECK-INST: sqincw  x0, vl1
 134 // CHECK-ENCODING: [0x20,0xf0,0xb0,0x04]
 135 // CHECK-ERROR: instruction requires: sve or sme
 136 // CHECK-UNKNOWN: 04b0f020 <unknown>
 137
 138 sqincw  x0, vl2
 139 // CHECK-INST: sqincw  x0, vl2
 140 // CHECK-ENCODING: [0x40,0xf0,0xb0,0x04]
 141 // CHECK-ERROR: instruction requires: sve or sme
 142 // CHECK-UNKNOWN: 04b0f040 <unknown>
 143
 144 sqincw  x0, vl3
 145 // CHECK-INST: sqincw  x0, vl3
 146 // CHECK-ENCODING: [0x60,0xf0,0xb0,0x04]
 147 // CHECK-ERROR: instruction requires: sve or sme
 148 // CHECK-UNKNOWN: 04b0f060 <unknown>
 149
 150 sqincw  x0, vl4
 151 // CHECK-INST: sqincw  x0, vl4
 152 // CHECK-ENCODING: [0x80,0xf0,0xb0,0x04]
 153 // CHECK-ERROR: instruction requires: sve or sme
 154 // CHECK-UNKNOWN: 04b0f080 <unknown>
 155
 156 sqincw  x0, vl5
 157 // CHECK-INST: sqincw  x0, vl5
 158 // CHECK-ENCODING: [0xa0,0xf0,0xb0,0x04]
 159 // CHECK-ERROR: instruction requires: sve or sme
 160 // CHECK-UNKNOWN: 04b0f0a0 <unknown>
 161
 162 sqincw  x0, vl6
 163 // CHECK-INST: sqincw  x0, vl6
 164 // CHECK-ENCODING: [0xc0,0xf0,0xb0,0x04]
 165 // CHECK-ERROR: instruction requires: sve or sme
 166 // CHECK-UNKNOWN: 04b0f0c0 <unknown>
 167
 168 sqincw  x0, vl7
 169 // CHECK-INST: sqincw  x0, vl7
 170 // CHECK-ENCODING: [0xe0,0xf0,0xb0,0x04]
 171 // CHECK-ERROR: instruction requires: sve or sme
 172 // CHECK-UNKNOWN: 04b0f0e0 <unknown>
 173
 174 sqincw  x0, vl8
 175 // CHECK-INST: sqincw  x0, vl8
 176 // CHECK-ENCODING: [0x00,0xf1,0xb0,0x04]
 177 // CHECK-ERROR: instruction requires: sve or sme
 178 // CHECK-UNKNOWN: 04b0f100 <unknown>
 179
 180 sqincw  x0, vl16
 181 // CHECK-INST: sqincw  x0, vl16
 182 // CHECK-ENCODING: [0x20,0xf1,0xb0,0x04]
 183 // CHECK-ERROR: instruction requires: sve or sme
 184 // CHECK-UNKNOWN: 04b0f120 <unknown>
 185
 186 sqincw  x0, vl32
 187 // CHECK-INST: sqincw  x0, vl32
 188 // CHECK-ENCODING: [0x40,0xf1,0xb0,0x04]
 189 // CHECK-ERROR: instruction requires: sve or sme
 190 // CHECK-UNKNOWN: 04b0f140 <unknown>
 191
 192 sqincw  x0, vl64
 193 // CHECK-INST: sqincw  x0, vl64
 194 // CHECK-ENCODING: [0x60,0xf1,0xb0,0x04]
 195 // CHECK-ERROR: instruction requires: sve or sme
 196 // CHECK-UNKNOWN: 04b0f160 <unknown>
 197
 198 sqincw  x0, vl128
 199 // CHECK-INST: sqincw  x0, vl128
 200 // CHECK-ENCODING: [0x80,0xf1,0xb0,0x04]
 201 // CHECK-ERROR: instruction requires: sve or sme
 202 // CHECK-UNKNOWN: 04b0f180 <unknown>
 203
 204 sqincw  x0, vl256
 205 // CHECK-INST: sqincw  x0, vl256
 206 // CHECK-ENCODING: [0xa0,0xf1,0xb0,0x04]
 207 // CHECK-ERROR: instruction requires: sve or sme
 208 // CHECK-UNKNOWN: 04b0f1a0 <unknown>
 209
 210 sqincw  x0, #14
 211 // CHECK-INST: sqincw  x0, #14
 212 // CHECK-ENCODING: [0xc0,0xf1,0xb0,0x04]
 213 // CHECK-ERROR: instruction requires: sve or sme
 214 // CHECK-UNKNOWN: 04b0f1c0 <unknown>
 215
 216 sqincw  x0, #15
 217 // CHECK-INST: sqincw  x0, #15
 218 // CHECK-ENCODING: [0xe0,0xf1,0xb0,0x04]
 219 // CHECK-ERROR: instruction requires: sve or sme
 220 // CHECK-UNKNOWN: 04b0f1e0 <unknown>
 221
 222 sqincw  x0, #16
 223 // CHECK-INST: sqincw  x0, #16
 224 // CHECK-ENCODING: [0x00,0xf2,0xb0,0x04]
 225 // CHECK-ERROR: instruction requires: sve or sme
 226 // CHECK-UNKNOWN: 04b0f200 <unknown>
 227
 228 sqincw  x0, #17
 229 // CHECK-INST: sqincw  x0, #17
 230 // CHECK-ENCODING: [0x20,0xf2,0xb0,0x04]
 231 // CHECK-ERROR: instruction requires: sve or sme
 232 // CHECK-UNKNOWN: 04b0f220 <unknown>
 233
 234 sqincw  x0, #18
 235 // CHECK-INST: sqincw  x0, #18
 236 // CHECK-ENCODING: [0x40,0xf2,0xb0,0x04]
 237 // CHECK-ERROR: instruction requires: sve or sme
 238 // CHECK-UNKNOWN: 04b0f240 <unknown>
 239
 240 sqincw  x0, #19
 241 // CHECK-INST: sqincw  x0, #19
 242 // CHECK-ENCODING: [0x60,0xf2,0xb0,0x04]
 243 // CHECK-ERROR: instruction requires: sve or sme
 244 // CHECK-UNKNOWN: 04b0f260 <unknown>
 245
 246 sqincw  x0, #20
 247 // CHECK-INST: sqincw  x0, #20
 248 // CHECK-ENCODING: [0x80,0xf2,0xb0,0x04]
 249 // CHECK-ERROR: instruction requires: sve or sme
 250 // CHECK-UNKNOWN: 04b0f280 <unknown>
 251
 252 sqincw  x0, #21
 253 // CHECK-INST: sqincw  x0, #21
 254 // CHECK-ENCODING: [0xa0,0xf2,0xb0,0x04]
 255 // CHECK-ERROR: instruction requires: sve or sme
 256 // CHECK-UNKNOWN: 04b0f2a0 <unknown>
 257
 258 sqincw  x0, #22
 259 // CHECK-INST: sqincw  x0, #22
 260 // CHECK-ENCODING: [0xc0,0xf2,0xb0,0x04]
 261 // CHECK-ERROR: instruction requires: sve or sme
 262 // CHECK-UNKNOWN: 04b0f2c0 <unknown>
 263
 264 sqincw  x0, #23
 265 // CHECK-INST: sqincw  x0, #23
 266 // CHECK-ENCODING: [0xe0,0xf2,0xb0,0x04]
 267 // CHECK-ERROR: instruction requires: sve or sme
 268 // CHECK-UNKNOWN: 04b0f2e0 <unknown>
 269
 270 sqincw  x0, #24
 271 // CHECK-INST: sqincw  x0, #24
 272 // CHECK-ENCODING: [0x00,0xf3,0xb0,0x04]
 273 // CHECK-ERROR: instruction requires: sve or sme
 274 // CHECK-UNKNOWN: 04b0f300 <unknown>
 275
 276 sqincw  x0, #25
 277 // CHECK-INST: sqincw  x0, #25
 278 // CHECK-ENCODING: [0x20,0xf3,0xb0,0x04]
 279 // CHECK-ERROR: instruction requires: sve or sme
 280 // CHECK-UNKNOWN: 04b0f320 <unknown>
 281
 282 sqincw  x0, #26
 283 // CHECK-INST: sqincw  x0, #26
 284 // CHECK-ENCODING: [0x40,0xf3,0xb0,0x04]
 285 // CHECK-ERROR: instruction requires: sve or sme
 286 // CHECK-UNKNOWN: 04b0f340 <unknown>
 287
 288 sqincw  x0, #27
 289 // CHECK-INST: sqincw  x0, #27
 290 // CHECK-ENCODING: [0x60,0xf3,0xb0,0x04]
 291 // CHECK-ERROR: instruction requires: sve or sme
 292 // CHECK-UNKNOWN: 04b0f360 <unknown>
 293
 294 sqincw  x0, #28
 295 // CHECK-INST: sqincw  x0, #28
 296 // CHECK-ENCODING: [0x80,0xf3,0xb0,0x04]
 297 // CHECK-ERROR: instruction requires: sve or sme
 298 // CHECK-UNKNOWN: 04b0f380 <unknown>
 299
 300
 301 // --------------------------------------------------------------------------//
 302 // Test compatibility with MOVPRFX instruction.
 303
 304 movprfx z0, z7
 305 // CHECK-INST: movprfx  z0, z7
 306 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 307 // CHECK-ERROR: instruction requires: sve or sme
 308 // CHECK-UNKNOWN: 0420bce0 <unknown>
 309
 310 sqincw  z0.s
 311 // CHECK-INST: sqincw   z0.s
 312 // CHECK-ENCODING: [0xe0,0xc3,0xa0,0x04]
 313 // CHECK-ERROR: instruction requires: sve or sme
 314 // CHECK-UNKNOWN: 04a0c3e0 <unknown>
 315
 316 movprfx z0, z7
 317 // CHECK-INST: movprfx  z0, z7
 318 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 319 // CHECK-ERROR: instruction requires: sve or sme
 320 // CHECK-UNKNOWN: 0420bce0 <unknown>
 321
 322 sqincw  z0.s, pow2, mul #16
 323 // CHECK-INST: sqincw   z0.s, pow2, mul #16
 324 // CHECK-ENCODING: [0x00,0xc0,0xaf,0x04]
 325 // CHECK-ERROR: instruction requires: sve or sme
 326 // CHECK-UNKNOWN: 04afc000 <unknown>
 327
 328 movprfx z0, z7
 329 // CHECK-INST: movprfx  z0, z7
 330 // CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
 331 // CHECK-ERROR: instruction requires: sve or sme
 332 // CHECK-UNKNOWN: 0420bce0 <unknown>
 333
 334 sqincw  z0.s, pow2
 335 // CHECK-INST: sqincw   z0.s, pow2
 336 // CHECK-ENCODING: [0x00,0xc0,0xa0,0x04]
 337 // CHECK-ERROR: instruction requires: sve or sme
 338 // CHECK-UNKNOWN: 04a0c000 <unknown>