llvm/test/MC/AArch64/SVE2p1/bfminnm-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1,+b16b16 2>&1 < %s | FileCheck %s
   2
   3 // --------------------------------------------------------------------------//
   4 // Invalid predicate register
   5
   6 bfminnm z23.h, p8/m, z23.h, z13.h
   7 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
   8 // CHECK-NEXT: bfminnm z23.h, p8/m, z23.h, z13.h
   9 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  10
  11 bfminnm z23.h, p1/z, z23.h, z13.h
  12 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  13 // CHECK-NEXT: bfminnm z23.h, p1/z, z23.h, z13.h
  14 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  15
  16 // --------------------------------------------------------------------------//
  17 // Invalid vector suffix
  18
  19 bfminnm z23.h, p1/z, z23.s, z13.s
  20 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  21 // CHECK-NEXT: bfminnm z23.h, p1/z, z23.s, z13.s
  22 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  23
  24 bfminnm z23.s, z23.h, z13.h
  25 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  26 // CHECK-NEXT: bfminnm z23.s, z23.h, z13.h
  27 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: