llvm/test/MC/AArch64/armv8.1a-rdma.s

   1 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a -show-encoding < %s 2> %t | FileCheck %s
   2 // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
   3 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8r -show-encoding < %s 2> %t | FileCheck %s
   4 // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s
   5   .text
   6
   7   //AdvSIMD RDMA vector
   8   sqrdmlah v0.4h, v1.4h, v2.4h
   9   sqrdmlsh v0.4h, v1.4h, v2.4h
  10   sqrdmlah v0.2s, v1.2s, v2.2s
  11   sqrdmlsh v0.2s, v1.2s, v2.2s
  12   sqrdmlah v0.4s, v1.4s, v2.4s
  13   sqrdmlsh v0.4s, v1.4s, v2.4s
  14   sqrdmlah v0.8h, v1.8h, v2.8h
  15   sqrdmlsh v0.8h, v1.8h, v2.8h
  16 // CHECK: sqrdmlah  v0.4h, v1.4h, v2.4h // encoding: [0x20,0x84,0x42,0x2e]
  17 // CHECK: sqrdmlsh  v0.4h, v1.4h, v2.4h // encoding: [0x20,0x8c,0x42,0x2e]
  18 // CHECK: sqrdmlah  v0.2s, v1.2s, v2.2s // encoding: [0x20,0x84,0x82,0x2e]
  19 // CHECK: sqrdmlsh  v0.2s, v1.2s, v2.2s // encoding: [0x20,0x8c,0x82,0x2e]
  20 // CHECK: sqrdmlah  v0.4s, v1.4s, v2.4s // encoding: [0x20,0x84,0x82,0x6e]
  21 // CHECK: sqrdmlsh  v0.4s, v1.4s, v2.4s // encoding: [0x20,0x8c,0x82,0x6e]
  22 // CHECK: sqrdmlah  v0.8h, v1.8h, v2.8h // encoding: [0x20,0x84,0x42,0x6e]
  23 // CHECK: sqrdmlsh  v0.8h, v1.8h, v2.8h // encoding: [0x20,0x8c,0x42,0x6e]
  24
  25   sqrdmlah v0.2h, v1.2h, v2.2h
  26 // CHECK-ERROR: [[@LINE-1]]:12: error: invalid operand for instruction
  27   sqrdmlsh v0.2h, v1.2h, v2.2h
  28 // CHECK-ERROR: [[@LINE-1]]:12: error: invalid operand for instruction
  29   sqrdmlah v0.8s, v1.8s, v2.8s
  30 // CHECK-ERROR: [[@LINE-1]]:12: error: invalid vector kind qualifier
  31 // CHECK-ERROR: [[@LINE-2]]:19: error: invalid vector kind qualifier
  32 // CHECK-ERROR: [[@LINE-3]]:26: error: invalid vector kind qualifier
  33   sqrdmlsh v0.8s, v1.8s, v2.8s
  34 // CHECK-ERROR: [[@LINE-1]]:12: error: invalid vector kind qualifier
  35 // CHECK-ERROR: [[@LINE-2]]:19: error: invalid vector kind qualifier
  36 // CHECK-ERROR: [[@LINE-3]]:26: error: invalid vector kind qualifier
  37   sqrdmlah v0.2s, v1.4h, v2.8h
  38 // CHECK-ERROR: [[@LINE-1]]:19: error: invalid operand for instruction
  39   sqrdmlsh v0.4s, v1.8h, v2.2s
  40 // CHECK-ERROR: [[@LINE-1]]:19: error: invalid operand for instruction
  41
  42   //AdvSIMD RDMA scalar
  43   sqrdmlah h0, h1, h2
  44   sqrdmlsh h0, h1, h2
  45   sqrdmlah s0, s1, s2
  46   sqrdmlsh s0, s1, s2
  47 // CHECK: sqrdmlah h0, h1, h2  // encoding: [0x20,0x84,0x42,0x7e]
  48 // CHECK: sqrdmlsh h0, h1, h2  // encoding: [0x20,0x8c,0x42,0x7e]
  49 // CHECK: sqrdmlah s0, s1, s2  // encoding: [0x20,0x84,0x82,0x7e]
  50 // CHECK: sqrdmlsh s0, s1, s2  // encoding: [0x20,0x8c,0x82,0x7e]
  51
  52   //AdvSIMD RDMA vector by-element
  53   sqrdmlah v0.4h, v1.4h, v2.h[3]
  54   sqrdmlsh v0.4h, v1.4h, v2.h[3]
  55   sqrdmlah v0.2s, v1.2s, v2.s[1]
  56   sqrdmlsh v0.2s, v1.2s, v2.s[1]
  57   sqrdmlah v0.8h, v1.8h, v2.h[3]
  58   sqrdmlsh v0.8h, v1.8h, v2.h[3]
  59   sqrdmlah v0.4s, v1.4s, v2.s[3]
  60   sqrdmlsh v0.4s, v1.4s, v2.s[3]
  61 // CHECK: sqrdmlah v0.4h, v1.4h, v2.h[3]  // encoding: [0x20,0xd0,0x72,0x2f]
  62 // CHECK: sqrdmlsh v0.4h, v1.4h, v2.h[3]  // encoding: [0x20,0xf0,0x72,0x2f]
  63 // CHECK: sqrdmlah v0.2s, v1.2s, v2.s[1]  // encoding: [0x20,0xd0,0xa2,0x2f]
  64 // CHECK: sqrdmlsh v0.2s, v1.2s, v2.s[1]  // encoding: [0x20,0xf0,0xa2,0x2f]
  65 // CHECK: sqrdmlah v0.8h, v1.8h, v2.h[3]  // encoding: [0x20,0xd0,0x72,0x6f]
  66 // CHECK: sqrdmlsh v0.8h, v1.8h, v2.h[3]  // encoding: [0x20,0xf0,0x72,0x6f]
  67 // CHECK: sqrdmlah v0.4s, v1.4s, v2.s[3]  // encoding: [0x20,0xd8,0xa2,0x6f]
  68 // CHECK: sqrdmlsh v0.4s, v1.4s, v2.s[3]  // encoding: [0x20,0xf8,0xa2,0x6f]
  69
  70   sqrdmlah v0.4s, v1.2s, v2.s[1]
  71   sqrdmlsh v0.2s, v1.2d, v2.s[1]
  72   sqrdmlah v0.8h, v1.8h, v2.s[3]
  73   sqrdmlsh v0.8h, v1.8h, v2.h[8]
  74 // CHECK-ERROR: error: invalid operand for instruction
  75 // CHECK-ERROR:   sqrdmlah v0.4s, v1.2s, v2.s[1]
  76 // CHECK-ERROR:                   ^
  77 // CHECK-ERROR: error: invalid operand for instruction
  78 // CHECK-ERROR:   sqrdmlsh v0.2s, v1.2d, v2.s[1]
  79 // CHECK-ERROR:                   ^
  80 // CHECK-ERROR: error: invalid operand for instruction
  81 // CHECK-ERROR:   sqrdmlah v0.8h, v1.8h, v2.s[3]
  82 // CHECK-ERROR:                          ^
  83 // CHECK-ERROR: error: vector lane must be an integer in range [0, 7].
  84 // CHECK-ERROR:   sqrdmlsh v0.8h, v1.8h, v2.h[8]
  85 // CHECK-ERROR:                              ^
  86
  87   //AdvSIMD RDMA scalar by-element
  88   sqrdmlah h0, h1, v2.h[3]
  89   sqrdmlsh h0, h1, v2.h[3]
  90   sqrdmlah s0, s1, v2.s[3]
  91   sqrdmlsh s0, s1, v2.s[3]
  92 // CHECK: sqrdmlah h0, h1, v2.h[3]  // encoding: [0x20,0xd0,0x72,0x7f]
  93 // CHECK: sqrdmlsh h0, h1, v2.h[3]  // encoding: [0x20,0xf0,0x72,0x7f]
  94 // CHECK: sqrdmlah s0, s1, v2.s[3]  // encoding: [0x20,0xd8,0xa2,0x7f]
  95 // CHECK: sqrdmlsh s0, s1, v2.s[3]  // encoding: [0x20,0xf8,0xa2,0x7f]
  96
  97   sqrdmlah b0, h1, v2.h[3]
  98   sqrdmlah s0, d1, v2.s[3]
  99   sqrdmlsh h0, h1, v2.s[3]
 100   sqrdmlsh s0, s1, v2.s[4]
 101 // CHECK-ERROR: error: invalid operand for instruction
 102 // CHECK-ERROR:   sqrdmlah b0, h1, v2.h[3]
 103 // CHECK-ERROR:            ^
 104 // CHECK-ERROR: error: invalid operand for instruction
 105 // CHECK-ERROR:   sqrdmlah s0, d1, v2.s[3]
 106 // CHECK-ERROR:                ^
 107 // CHECK-ERROR: error: invalid operand for instruction
 108 // CHECK-ERROR:   sqrdmlsh h0, h1, v2.s[3]
 109 // CHECK-ERROR:                    ^
 110 // CHECK-ERROR: error: vector lane must be an integer in range [0, 3].
 111 // CHECK-ERROR:   sqrdmlsh s0, s1, v2.s[4]
 112 // CHECK-ERROR:                        ^