llvm/test/MC/AArch64/armv9-mrrs.s

   1 // +the required for RCWSMASK_EL1, RCWMASK_EL1
   2 // +el2vmsa required for TTBR0_EL2 (VSCTLR_EL2), VTTBR_EL2
   3 // +vh required for TTBR1_EL2
   4
   5 // RUN: not llvm-mc -triple aarch64 -mattr=+d128,+the,+el2vmsa,+vh -show-encoding %s -o - 2> %t | FileCheck %s
   6 // RUN: FileCheck %s --input-file=%t --check-prefix=ERRORS
   7
   8 // RUN: not llvm-mc -triple aarch64 -mattr=+the,+el2vmsa,+vh -show-encoding %s -o - 2>&1 | FileCheck %s --check-prefix=ERROR-NO-D128
   9
  10           mrrs  x0, x1, TTBR0_EL1
  11 // CHECK: mrrs  x0, x1, TTBR0_EL1           // encoding: [0x00,0x20,0x78,0xd5]
  12 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  13           mrrs  x0, x1, TTBR1_EL1
  14 // CHECK: mrrs  x0, x1, TTBR1_EL1           // encoding: [0x20,0x20,0x78,0xd5]
  15 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  16           mrrs  x0, x1, PAR_EL1
  17 // CHECK: mrrs  x0, x1, PAR_EL1             // encoding: [0x00,0x74,0x78,0xd5]
  18 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  19           mrrs  x0, x1, RCWSMASK_EL1
  20 // CHECK: mrrs  x0, x1, RCWSMASK_EL1        // encoding: [0x60,0xd0,0x78,0xd5]
  21 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  22           mrrs  x0, x1, RCWMASK_EL1
  23 // CHECK: mrrs  x0, x1, RCWMASK_EL1         // encoding: [0xc0,0xd0,0x78,0xd5]
  24 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  25           mrrs  x0, x1, TTBR0_EL2
  26 // CHECK: mrrs  x0, x1, TTBR0_EL2           // encoding: [0x00,0x20,0x7c,0xd5]
  27 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  28           mrrs  x0, x1, TTBR1_EL2
  29 // CHECK: mrrs  x0, x1, TTBR1_EL2           // encoding: [0x20,0x20,0x7c,0xd5]
  30 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  31           mrrs  x0, x1, VTTBR_EL2
  32 // CHECK: mrrs  x0, x1, VTTBR_EL2           // encoding: [0x00,0x21,0x7c,0xd5]
  33 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  34
  35           mrrs   x0,  x1, VTTBR_EL2
  36 // CHECK: mrrs   x0,  x1, VTTBR_EL2           // encoding: [0x00,0x21,0x7c,0xd5]
  37 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  38           mrrs   x2,  x3, VTTBR_EL2
  39 // CHECK: mrrs   x2,  x3, VTTBR_EL2           // encoding: [0x02,0x21,0x7c,0xd5]
  40 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  41           mrrs   x4,  x5, VTTBR_EL2
  42 // CHECK: mrrs   x4,  x5, VTTBR_EL2           // encoding: [0x04,0x21,0x7c,0xd5]
  43 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  44           mrrs   x6,  x7, VTTBR_EL2
  45 // CHECK: mrrs   x6,  x7, VTTBR_EL2           // encoding: [0x06,0x21,0x7c,0xd5]
  46 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  47           mrrs   x8,  x9, VTTBR_EL2
  48 // CHECK: mrrs   x8,  x9, VTTBR_EL2           // encoding: [0x08,0x21,0x7c,0xd5]
  49 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  50           mrrs  x10, x11, VTTBR_EL2
  51 // CHECK: mrrs  x10, x11, VTTBR_EL2           // encoding: [0x0a,0x21,0x7c,0xd5]
  52 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  53           mrrs  x12, x13, VTTBR_EL2
  54 // CHECK: mrrs  x12, x13, VTTBR_EL2           // encoding: [0x0c,0x21,0x7c,0xd5]
  55 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  56           mrrs  x14, x15, VTTBR_EL2
  57 // CHECK: mrrs  x14, x15, VTTBR_EL2           // encoding: [0x0e,0x21,0x7c,0xd5]
  58 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  59           mrrs  x16, x17, VTTBR_EL2
  60 // CHECK: mrrs  x16, x17, VTTBR_EL2           // encoding: [0x10,0x21,0x7c,0xd5]
  61 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  62           mrrs  x18, x19, VTTBR_EL2
  63 // CHECK: mrrs  x18, x19, VTTBR_EL2           // encoding: [0x12,0x21,0x7c,0xd5]
  64 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  65           mrrs  x20, x21, VTTBR_EL2
  66 // CHECK: mrrs  x20, x21, VTTBR_EL2           // encoding: [0x14,0x21,0x7c,0xd5]
  67 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  68           mrrs  x22, x23, VTTBR_EL2
  69 // CHECK: mrrs  x22, x23, VTTBR_EL2           // encoding: [0x16,0x21,0x7c,0xd5]
  70 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  71           mrrs  x24, x25, VTTBR_EL2
  72 // CHECK: mrrs  x24, x25, VTTBR_EL2           // encoding: [0x18,0x21,0x7c,0xd5]
  73 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  74           mrrs  x26, x27, VTTBR_EL2
  75 // CHECK: mrrs  x26, x27, VTTBR_EL2           // encoding: [0x1a,0x21,0x7c,0xd5]
  76 // ERROR-NO-D128: [[@LINE-2]]:11: error: instruction requires: d128
  77
  78           mrrs x0, x2, TTBR0_EL1
  79 // ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair
  80
  81           mrrs x0, TTBR0_EL1
  82 // ERRORS: error: expected second odd register of a consecutive same-size even/odd register pair
  83
  84           mrrs x1, x2, TTBR0_EL1
  85 // ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
  86
  87           mrrs x31, x0, TTBR0_EL1
  88 // ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
  89
  90           mrrs xzr, x30, TTBR0_EL1
  91 // ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
  92
  93           mrrs xzr, TTBR0_EL1
  94 // ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
  95
  96           mrrs S3_0_c2_c0_1
  97 // ERRORS: error: expected first even register of a consecutive same-size even/odd register pair
  98
  99           mrrs S3_0_c2_c0_1, x0, x1
 100 // ERRORS: error: expected first even register of a consecutive same-size even/odd register pair