llvm/test/MC/AMDGPU/gfx10_asm_dpp16.s

   1 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s
   2 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s
   3 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s
   4 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s
   5
   6 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
   7 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00]
   8
   9 v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
  10 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00]
  11
  12 v_mov_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0
  13 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0x00]
  14
  15 v_mov_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0
  16 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0x00]
  17
  18 v_mov_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0
  19 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0x00]
  20
  21 v_mov_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0
  22 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0x00]
  23
  24 v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0
  25 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0x00]
  26
  27 v_mov_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0
  28 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0x00]
  29
  30 v_mov_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0
  31 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0x00]
  32
  33 v_mov_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0
  34 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0x00]
  35
  36 v_mov_b32_dpp v5, v1 row_share:0 row_mask:0x0 bank_mask:0x0
  37 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x50,0x01,0x00]
  38
  39 v_mov_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0
  40 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x5f,0x01,0x00]
  41
  42 v_mov_b32_dpp v5, v1 row_xmask:0 row_mask:0x0 bank_mask:0x0
  43 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x60,0x01,0x00]
  44
  45 v_mov_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0
  46 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x6f,0x01,0x00]
  47
  48 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x1 bank_mask:0x0
  49 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x10]
  50
  51 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x3 bank_mask:0x0
  52 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x30]
  53
  54 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0x0
  55 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0xf0]
  56
  57 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] bank_mask:0x0
  58 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0xf0]
  59
  60 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x1
  61 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x01]
  62
  63 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x3
  64 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x03]
  65
  66 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0xf
  67 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x0f]
  68
  69 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0
  70 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x0f]
  71
  72 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
  73 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x08,0x00]
  74
  75 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:1
  76 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x08,0x00]
  77
  78 v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
  79 // GFX10: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
  80
  81 v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
  82 // GFX10: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
  83
  84 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
  85 // GFX10: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
  86
  87 v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
  88 // GFX10: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0x00]
  89
  90 v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
  91 // GFX10: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0x00]
  92
  93 v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
  94 // GFX10: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0x00]
  95
  96 v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
  97 // GFX10: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0x00]
  98
  99 v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 100 // GFX10: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 101
 102 v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 103 // GFX10: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 104
 105 v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 106 // GFX10: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 107
 108 v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 109 // GFX10: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 110
 111 v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 112 // GFX10: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 113
 114 v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 115 // GFX10: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 116
 117 v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 118 // GFX10: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 119
 120 v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 121 // GFX10: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 122
 123 v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 124 // GFX10: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 125
 126 v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 127 // GFX10: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 128
 129 v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 130 // GFX10: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 131
 132 v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 133 // GFX10: [0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 134
 135 v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 136 // GFX10: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 137
 138 v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 139 // GFX10: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 140
 141 v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 142 // GFX10: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 143
 144 v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 145 // GFX10: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 146
 147 v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 148 // GFX10: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 149
 150 v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 151 // GFX10: [0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 152
 153 v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 154 // GFX10: [0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 155
 156 v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 157 // GFX10: [0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 158
 159 v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 160 // GFX10: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 161
 162 v_ffbh_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 163 // GFX10: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 164
 165 v_ffbl_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 166 // GFX10: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 167
 168 v_ffbh_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 169 // GFX10: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 170
 171 v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 172 // GFX10: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 173
 174 v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 175 // GFX10: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 176
 177 v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 178 // GFX10: [0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 179
 180 v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 181 // GFX10: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 182
 183 v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 184 // GFX10: [0xfa,0xa4,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 185
 186 v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 187 // GFX10: [0xfa,0xa6,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 188
 189 v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 190 // GFX10: [0xfa,0xa8,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 191
 192 v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 193 // GFX10: [0xfa,0xaa,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 194
 195 v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 196 // GFX10: [0xfa,0xac,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 197
 198 v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 199 // GFX10: [0xfa,0xae,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 200
 201 v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 202 // GFX10: [0xfa,0xb0,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 203
 204 v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 205 // GFX10: [0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 206
 207 v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 208 // GFX10: [0xfa,0xb4,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 209
 210 v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 211 // GFX10: [0xfa,0xb6,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 212
 213 v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 214 // GFX10: [0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 215
 216 v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 217 // GFX10: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 218
 219 v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 220 // GFX10: [0xfa,0xbc,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 221
 222 v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 223 // GFX10: [0xfa,0xbe,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 224
 225 v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 226 // GFX10: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 227
 228 v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 229 // GFX10: [0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 230
 231 v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 232 // GFX10: [0xfa,0xc4,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 233
 234 v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 235 // GFX10: [0xfa,0xc6,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 236
 237 v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 238 // GFX10: [0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 239
 240 v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 241 // GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00]
 242
 243 v_add_f32_dpp v5, -v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 244 // GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x10,0x00]
 245
 246 v_add_f32_dpp v5, |v1|, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 247 // GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x20,0x00]
 248
 249 v_add_f32_dpp v5, v1, -v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 250 // GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x40,0x00]
 251
 252 v_add_f32_dpp v5, v1, |v2| quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 253 // GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x80,0x00]
 254
 255 v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 256 // GFX10: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0x00]
 257
 258 v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 259 // GFX10: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0x00]
 260
 261 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 262 // GFX10: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0x00]
 263
 264 v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 265 // GFX10: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0x00]
 266
 267 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 268 // GFX10: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0x00]
 269
 270 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 271 // GFX10: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0x00]
 272
 273 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 274 // GFX10: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0x00]
 275
 276 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 277 // GFX10: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0x00]
 278
 279 v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 280 // GFX10: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0x00]
 281
 282 v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 283 // GFX10: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0x00]
 284
 285 v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 286 // GFX10: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0x00]
 287
 288 v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 289 // GFX10: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0x00]
 290
 291 v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 292 // GFX10: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0x00]
 293
 294 v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 295 // GFX10: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0x00]
 296
 297 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 298 // GFX10: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0x00]
 299
 300 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 301 // GFX10: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0x00]
 302
 303 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 304 // GFX10: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0x00]
 305
 306 v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 307 // GFX10: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0x00]
 308
 309 v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 310 // GFX10: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0x00]
 311
 312 v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 313 // GFX10: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0x00]
 314
 315 v_xnor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 316 // GFX10: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0x00]
 317
 318 v_mac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 319 // GFX10: [0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x00,0x00]
 320
 321 v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 322 // W32: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00]
 323 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 324
 325 v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 326 // W32: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x00,0x00]
 327 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 328
 329 v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 330 // W32: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x00,0x00]
 331 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 332
 333 v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 334 // W64: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00]
 335 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 336
 337 v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 338 // W64: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x00,0x00]
 339 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 340
 341 v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 342 // W64: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x00,0x00]
 343 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 344
 345 v_fmac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 346 // GFX10: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0x00]
 347
 348 v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 349 // GFX10: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00]
 350
 351 v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 352 // GFX10: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0x00]
 353
 354 v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 355 // GFX10: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0x00]
 356
 357 v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 358 // GFX10: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0x00]
 359
 360 v_fmac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 361 // GFX10: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0x00]
 362
 363 v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 364 // GFX10: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0x00]
 365
 366 v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 367 // GFX10: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0x00]
 368
 369 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 370 // GFX10: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0x00]
 371
 372 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:0
 373 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00]
 374
 375 v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 376 // GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 377
 378 v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 379 // GFX10: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 380
 381 v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 382 // GFX10: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 383
 384 v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 385 // GFX10: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 386
 387 v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 388 // GFX10: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 389
 390 v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 391 // GFX10: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 392
 393 v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 394 // GFX10: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 395
 396 v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 397 // GFX10: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 398
 399 v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 400 // GFX10: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 401
 402 v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 403 // GFX10: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 404
 405 v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 406 // GFX10: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 407
 408 v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 409 // GFX10: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 410
 411 v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 412 // GFX10: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 413
 414 v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 415 // GFX10: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 416
 417 v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 418 // GFX10: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 419
 420 v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 421 // GFX10: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 422
 423 v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 424 // GFX10: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 425
 426 v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 427 // GFX10: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 428
 429 v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 430 // GFX10: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 431
 432 v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 433 // GFX10: [0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 434
 435 v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 436 // GFX10: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 437
 438 v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 439 // GFX10: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 440
 441 v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 442 // GFX10: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 443
 444 v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 445 // GFX10: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 446
 447 v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 448 // GFX10: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 449
 450 v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 451 // GFX10: [0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 452
 453 v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 454 // GFX10: [0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 455
 456 v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 457 // GFX10: [0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 458
 459 v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 460 // GFX10: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 461
 462 v_ffbh_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 463 // GFX10: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 464
 465 v_ffbl_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 466 // GFX10: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 467
 468 v_ffbh_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 469 // GFX10: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 470
 471 v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 472 // GFX10: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 473
 474 v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 475 // GFX10: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 476
 477 v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 478 // GFX10: [0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 479
 480 v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 481 // GFX10: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 482
 483 v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 484 // GFX10: [0xfa,0xa4,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 485
 486 v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 487 // GFX10: [0xfa,0xa6,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 488
 489 v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 490 // GFX10: [0xfa,0xa8,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 491
 492 v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 493 // GFX10: [0xfa,0xaa,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 494
 495 v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 496 // GFX10: [0xfa,0xac,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 497
 498 v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 499 // GFX10: [0xfa,0xae,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 500
 501 v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 502 // GFX10: [0xfa,0xb0,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 503
 504 v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 505 // GFX10: [0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 506
 507 v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 508 // GFX10: [0xfa,0xb4,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 509
 510 v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 511 // GFX10: [0xfa,0xb6,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 512
 513 v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 514 // GFX10: [0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 515
 516 v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 517 // GFX10: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 518
 519 v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 520 // GFX10: [0xfa,0xbc,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 521
 522 v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 523 // GFX10: [0xfa,0xbe,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 524
 525 v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 526 // GFX10: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 527
 528 v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 529 // GFX10: [0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 530
 531 v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 532 // GFX10: [0xfa,0xc4,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 533
 534 v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 535 // GFX10: [0xfa,0xc6,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 536
 537 v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 538 // GFX10: [0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x04,0x00]
 539
 540 v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 541 // GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x04,0x00]
 542
 543 v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 544 // GFX10: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x04,0x00]
 545
 546 v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 547 // GFX10: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x04,0x00]
 548
 549 v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 550 // GFX10: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x04,0x00]
 551
 552 v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 553 // GFX10: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x04,0x00]
 554
 555 v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 556 // GFX10: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x04,0x00]
 557
 558 v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 559 // GFX10: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x04,0x00]
 560
 561 v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 562 // GFX10: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x04,0x00]
 563
 564 v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 565 // GFX10: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x04,0x00]
 566
 567 v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 568 // GFX10: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x04,0x00]
 569
 570 v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 571 // GFX10: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x04,0x00]
 572
 573 v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 574 // GFX10: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x04,0x00]
 575
 576 v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 577 // GFX10: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x04,0x00]
 578
 579 v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 580 // GFX10: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x04,0x00]
 581
 582 v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 583 // GFX10: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x04,0x00]
 584
 585 v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 586 // GFX10: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x04,0x00]
 587
 588 v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 589 // GFX10: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x04,0x00]
 590
 591 v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 592 // GFX10: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x04,0x00]
 593
 594 v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 595 // GFX10: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x04,0x00]
 596
 597 v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 598 // GFX10: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x04,0x00]
 599
 600 v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 601 // GFX10: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x04,0x00]
 602
 603 v_xnor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 604 // GFX10: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x04,0x00]
 605
 606 v_mac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 607 // GFX10: [0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x04,0x00]
 608
 609 v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 610 // W32: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x04,0x00]
 611 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 612
 613 v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 614 // W32: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x04,0x00]
 615 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 616
 617 v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 618 // W32: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x04,0x00]
 619 // W64-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 620
 621 v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 622 // W64: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x04,0x00]
 623 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 624
 625 v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 626 // W64: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x04,0x00]
 627 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 628
 629 v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 630 // W64: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x04,0x00]
 631 // W32-ERR: :[[@LINE-2]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
 632
 633 v_fmac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 634 // GFX10: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x04,0x00]
 635
 636 v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 637 // GFX10: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x04,0x00]
 638
 639 v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 640 // GFX10: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x04,0x00]
 641
 642 v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 643 // GFX10: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x04,0x00]
 644
 645 v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 646 // GFX10: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x04,0x00]
 647
 648 v_fmac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 649 // GFX10: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x04,0x00]
 650
 651 v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 652 // GFX10: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x04,0x00]
 653
 654 v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 655 // GFX10: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x04,0x00]
 656
 657 v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 658 // GFX10: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x04,0x00]
 659
 660 v_add_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 661 // GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0x00]
 662
 663 v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:0
 664 // GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x08,0x00]
 665
 666 v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:1
 667 // GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x08,0x00]
 668
 669 v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 670 // GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x04,0x00]
 671
 672 v_sub_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0
 673 // GFX10: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0x00]
 674
 675 v_sub_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0
 676 // GFX10: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0x00]
 677
 678 v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 679 // GFX10: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x04,0x00]
 680
 681 v_subrev_nc_u32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0
 682 // GFX10: [0xfa,0x04,0x0a,0x4e,0x01,0x6f,0x01,0x00]
 683
 684 v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x1 bank_mask:0x0
 685 // GFX10: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0x10]
 686
 687 v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 688 // GFX10: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00]
 689
 690 v_movreld_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 691 // GFX10: [0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00]
 692
 693 v_movrels_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
 694 // GFX10: [0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00]
 695
 696 v_movrelsd_2_b32_dpp v0, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 697 // GFX10: [0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00]
 698
 699 v_movrelsd_b32_dpp v0, v255 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
 700 // GFX10: [0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00]