1 // RUN
: llvm-mc
-arch
=amdgcn
-show-encoding
-mcpu
=gfx1150
%s | FileCheck
--check-prefix
=GFX1150
%s
2 // RUN
: llvm-mc
-arch
=amdgcn
-show-encoding
-mcpu
=gfx1151
%s | FileCheck
--check-prefix
=GFX1150
%s
5 // Subtargets allow src1 of VOP3 DPP instructions to
be SGPR
or inlinable
9 v_add3_u32_e64_dpp v5
, v1
, s2
, v3 quad_perm
:[3,2,1,0] row_mask
:0xf bank_mask
:0xf
10 // GFX1150
: encoding
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0c,0x04,0x01,0x1b,0x00,0xff]
12 v_add3_u32_e64_dpp v5
, v1
, 42, v3 quad_perm
:[3,2,1,0] row_mask
:0xf bank_mask
:0xf
13 // GFX1150
: encoding
: [0x05,0x00,0x55,0xd6,0xfa,0x54,0x0d,0x04,0x01,0x1b,0x00,0xff]
15 v_add3_u32_e64_dpp v5
, v1
, s2
, v0 dpp8
:[7,6,5,4,3,2,1,0]
16 // GFX1150
: encoding
: [0x05,0x00,0x55,0xd6,0xe9,0x04,0x00,0x04,0x01,0x77,0x39,0x05]
18 v_add3_u32_e64_dpp v5
, v1
, 42, v0 dpp8
:[7,6,5,4,3,2,1,0]
19 // GFX1150
: encoding
: [0x05,0x00,0x55,0xd6,0xe9,0x54,0x01,0x04,0x01,0x77,0x39,0x05]