1 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=gfx1100
-mattr
=+wavefrontsize32
,-wavefrontsize64
-show-encoding
%s | FileCheck
--check-prefixes
=GFX11
,W32
%s
2 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=gfx1100
-mattr
=-wavefrontsize32
,+wavefrontsize64
-show-encoding
%s | FileCheck
--check-prefixes
=GFX11
,W64
%s
3 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=gfx1100
-mattr
=+wavefrontsize32
,-wavefrontsize64
%s
2>&1 | FileCheck
--check-prefixes
=GFX11-ERR
,W32-ERR
--implicit-check-
not=error
: %s
4 // RUN
: not llvm-mc
-triple
=amdgcn
-mcpu
=gfx1100
-mattr
=-wavefrontsize32
,+wavefrontsize64
%s
2>&1 | FileCheck
--check-prefixes
=GFX11-ERR
,W64-ERR
--implicit-check-
not=error
: %s
6 v_add3_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
7 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
9 v_add3_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
10 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
12 v_add3_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
13 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
15 v_add3_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
16 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
18 v_add3_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
19 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
21 v_add3_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
22 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
24 v_add3_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
25 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
27 v_add3_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
28 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
30 v_add3_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
31 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
33 v_add3_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
34 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
36 v_add3_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
37 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
39 v_add3_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
40 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
42 v_add3_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
43 // GFX11
: [0x05,0x00,0x55,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
45 v_add3_u32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
46 // GFX11
: [0xff,0x00,0x55,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
48 v_add_co_u32_e64_dpp v5
, s6
, v1
, v2 quad_perm
:[3,2,1,0]
49 // W32
: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
50 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
52 v_add_co_u32_e64_dpp v5
, s6
, v1
, v2 quad_perm
:[0,1,2,3]
53 // W32
: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
54 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
56 v_add_co_u32_e64_dpp v5
, s6
, v1
, v2 row_mirror
57 // W32
: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
58 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
60 v_add_co_u32_e64_dpp v5
, s6
, v1
, v2 row_half_mirror
61 // W32
: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
62 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
64 v_add_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shl
:1
65 // W32
: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
66 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
68 v_add_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shl
:15
69 // W32
: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
70 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
72 v_add_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shr
:1
73 // W32
: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
74 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
76 v_add_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shr
:15
77 // W32
: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
78 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
80 v_add_co_u32_e64_dpp v5
, s6
, v1
, v2 row_ror
:1
81 // W32
: [0x05,0x06,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
82 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
84 v_add_co_u32_e64_dpp v5
, s105
, v1
, v2 row_ror
:15
85 // W32
: [0x05,0x69,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
86 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
88 v_add_co_u32_e64_dpp v5
, vcc_lo
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
89 // W32
: [0x05,0x6a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
90 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
92 v_add_co_u32_e64_dpp v5
, vcc_hi
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
93 // W32
: [0x05,0x6b,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
94 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
96 v_add_co_u32_e64_dpp v5
, ttmp15
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
97 // W32
: [0x05,0x7b,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
98 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
100 v_add_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 quad_perm
:[3,2,1,0]
101 // W64
: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
102 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
104 v_add_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 quad_perm
:[0,1,2,3]
105 // W64
: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
106 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
108 v_add_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_mirror
109 // W64
: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
110 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
112 v_add_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_half_mirror
113 // W64
: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
114 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
116 v_add_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shl
:1
117 // W64
: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
118 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
120 v_add_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shl
:15
121 // W64
: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
122 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
124 v_add_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shr
:1
125 // W64
: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
126 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
128 v_add_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shr
:15
129 // W64
: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
130 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
132 v_add_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_ror
:1
133 // W64
: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
134 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
136 v_add_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_ror
:15
137 // W64
: [0x05,0x0c,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
138 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
140 v_add_co_u32_e64_dpp v5
, s
[104:105], v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
141 // W64
: [0x05,0x68,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
142 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
144 v_add_co_u32_e64_dpp v5
, vcc
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
145 // W64
: [0x05,0x6a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
146 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
148 v_add_co_u32_e64_dpp v5
, ttmp
[14:15], v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
149 // W64
: [0x05,0x7a,0x00,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
150 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
152 v_add_co_u32_e64_dpp v255
, null
, v255
, v255 clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
153 // GFX11
: [0xff,0xfc,0x00,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
155 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
156 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
158 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
159 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
161 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
162 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
164 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
165 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
167 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
168 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
170 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
171 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
173 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
174 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
176 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
177 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
179 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
180 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
182 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
183 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
185 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
186 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
188 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
189 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
191 v_add_lshl_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
192 // GFX11
: [0x05,0x00,0x47,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
194 v_add_lshl_u32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
195 // GFX11
: [0xff,0x00,0x47,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
197 v_add_nc_i16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
198 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
200 v_add_nc_i16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
201 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
203 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_mirror
204 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
206 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_half_mirror
207 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
209 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_shl
:1
210 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
212 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_shl
:15
213 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
215 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_shr
:1
216 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
218 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_shr
:15
219 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
221 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_ror
:1
222 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
224 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_ror
:15
225 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
227 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
228 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
230 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
231 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
233 v_add_nc_i16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
234 // GFX11
: [0x05,0x00,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
236 v_add_nc_i16_e64_dpp v255
, v255
, v255 clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
237 // GFX11
: [0xff,0x80,0x0d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
239 v_add_nc_i32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
240 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
242 v_add_nc_i32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
243 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
245 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_mirror
246 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
248 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_half_mirror
249 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
251 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_shl
:1
252 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
254 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_shl
:15
255 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
257 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_shr
:1
258 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
260 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_shr
:15
261 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
263 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_ror
:1
264 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
266 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_ror
:15
267 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
269 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
270 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
272 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
273 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
275 v_add_nc_i32_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
276 // GFX11
: [0x05,0x00,0x26,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
278 v_add_nc_i32_e64_dpp v255
, v255
, v255 clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
279 // GFX11
: [0xff,0x80,0x26,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
281 v_add_nc_u16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
282 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
284 v_add_nc_u16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
285 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
287 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_mirror
288 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
290 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_half_mirror
291 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
293 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_shl
:1
294 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
296 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_shl
:15
297 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
299 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_shr
:1
300 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
302 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_shr
:15
303 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
305 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_ror
:1
306 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
308 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_ror
:15
309 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
311 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
312 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
314 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
315 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
317 v_add_nc_u16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
318 // GFX11
: [0x05,0x00,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
320 v_add_nc_u16_e64_dpp v255
, v255
, v255 clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
321 // GFX11
: [0xff,0x80,0x03,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
323 v_alignbit_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
324 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
326 v_alignbit_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
327 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
329 v_alignbit_b32_e64_dpp v5
, v1
, v2
, v3 row_mirror
330 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
332 v_alignbit_b32_e64_dpp v5
, v1
, v2
, v3 row_half_mirror
333 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
335 v_alignbit_b32_e64_dpp v5
, v1
, v2
, v255 row_shl
:1
336 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
338 v_alignbit_b32_e64_dpp v5
, v1
, v2
, s105 row_shl
:15
339 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
341 v_alignbit_b32_e64_dpp v5
, v1
, v2
, vcc_hi row_shr
:1
342 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
344 v_alignbit_b32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:15
345 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
347 v_alignbit_b32_e64_dpp v5
, v1
, v2
, ttmp15 row_ror
:1
348 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
350 v_alignbit_b32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:15
351 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
353 v_alignbit_b32_e64_dpp v5
, v1
, v2
, exec_lo row_share
:0 row_mask
:0xf bank_mask
:0xf
354 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
356 v_alignbit_b32_e64_dpp v5
, v1
, v2
, null row_share
:15 row_mask
:0x0 bank_mask
:0x1
357 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
359 v_alignbit_b32_e64_dpp v5
, v1
, v2
, -1 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
360 // GFX11
: [0x05,0x00,0x16,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
362 v_alignbit_b32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
363 // GFX11
: [0xff,0x00,0x16,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
365 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
366 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
368 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
369 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
371 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, v3 row_mirror
372 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
374 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, v3 row_half_mirror
375 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
377 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, v255 row_shl
:1
378 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
380 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, s105 row_shl
:15
381 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
383 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, vcc_hi row_shr
:1
384 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
386 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:15
387 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
389 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, ttmp15 row_ror
:1
390 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
392 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:15
393 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
395 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, exec_lo row_share
:0 row_mask
:0xf bank_mask
:0xf
396 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
398 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, null row_share
:15 row_mask
:0x0 bank_mask
:0x1
399 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
401 v_alignbyte_b32_e64_dpp v5
, v1
, v2
, -1 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
402 // GFX11
: [0x05,0x00,0x17,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
404 v_alignbyte_b32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
405 // GFX11
: [0xff,0x00,0x17,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
407 v_and_b16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
408 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
410 v_and_b16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
411 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
413 v_and_b16_e64_dpp v5
, v1
, v2 row_mirror
414 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
416 v_and_b16_e64_dpp v5
, v1
, v2 row_half_mirror
417 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
419 v_and_b16_e64_dpp v5
, v1
, v2 row_shl
:1
420 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
422 v_and_b16_e64_dpp v5
, v1
, v2 row_shl
:15
423 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
425 v_and_b16_e64_dpp v5
, v1
, v2 row_shr
:1
426 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
428 v_and_b16_e64_dpp v5
, v1
, v2 row_shr
:15
429 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
431 v_and_b16_e64_dpp v5
, v1
, v2 row_ror
:1
432 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
434 v_and_b16_e64_dpp v5
, v1
, v2 row_ror
:15
435 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
437 v_and_b16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
438 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
440 v_and_b16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
441 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
443 v_and_b16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
444 // GFX11
: [0x05,0x00,0x62,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
446 v_and_b16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
447 // GFX11
: [0xff,0x00,0x62,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
449 v_and_or_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
450 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
452 v_and_or_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
453 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
455 v_and_or_b32_e64_dpp v5
, v1
, v2
, v3 row_mirror
456 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
458 v_and_or_b32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
459 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
461 v_and_or_b32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
462 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
464 v_and_or_b32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
465 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
467 v_and_or_b32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
468 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
470 v_and_or_b32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
471 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
473 v_and_or_b32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
474 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
476 v_and_or_b32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
477 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
479 v_and_or_b32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
480 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
482 v_and_or_b32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
483 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
485 v_and_or_b32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
486 // GFX11
: [0x05,0x00,0x57,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
488 v_and_or_b32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
489 // GFX11
: [0xff,0x00,0x57,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
491 v_ashrrev_i16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
492 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
494 v_ashrrev_i16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
495 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
497 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_mirror
498 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
500 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_half_mirror
501 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
503 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_shl
:1
504 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
506 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_shl
:15
507 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
509 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_shr
:1
510 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
512 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_shr
:15
513 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
515 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_ror
:1
516 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
518 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_ror
:15
519 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
521 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
522 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
524 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
525 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
527 v_ashrrev_i16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
528 // GFX11
: [0x05,0x00,0x3a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
530 v_ashrrev_i16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
531 // GFX11
: [0xff,0x00,0x3a,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
533 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
534 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
536 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
537 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
539 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_mirror
540 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
542 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_half_mirror
543 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
545 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_shl
:1
546 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
548 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_shl
:15
549 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
551 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_shr
:1
552 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
554 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_shr
:15
555 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
557 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_ror
:1
558 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
560 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_ror
:15
561 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
563 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
564 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
566 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
567 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
569 v_bcnt_u32_b32_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
570 // GFX11
: [0x05,0x00,0x1e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
572 v_bcnt_u32_b32_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
573 // GFX11
: [0xff,0x00,0x1e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
575 v_bfe_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
576 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
578 v_bfe_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
579 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
581 v_bfe_i32_e64_dpp v5
, v1
, v2
, v3 row_mirror
582 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
584 v_bfe_i32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
585 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
587 v_bfe_i32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
588 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
590 v_bfe_i32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
591 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
593 v_bfe_i32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
594 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
596 v_bfe_i32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
597 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
599 v_bfe_i32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
600 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
602 v_bfe_i32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
603 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
605 v_bfe_i32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
606 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
608 v_bfe_i32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
609 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
611 v_bfe_i32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
612 // GFX11
: [0x05,0x00,0x11,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
614 v_bfe_i32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
615 // GFX11
: [0xff,0x00,0x11,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
617 v_bfe_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
618 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
620 v_bfe_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
621 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
623 v_bfe_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
624 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
626 v_bfe_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
627 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
629 v_bfe_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
630 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
632 v_bfe_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
633 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
635 v_bfe_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
636 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
638 v_bfe_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
639 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
641 v_bfe_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
642 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
644 v_bfe_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
645 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
647 v_bfe_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
648 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
650 v_bfe_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
651 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
653 v_bfe_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
654 // GFX11
: [0x05,0x00,0x10,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
656 v_bfe_u32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
657 // GFX11
: [0xff,0x00,0x10,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
659 v_bfi_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
660 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
662 v_bfi_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
663 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
665 v_bfi_b32_e64_dpp v5
, v1
, v2
, v3 row_mirror
666 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
668 v_bfi_b32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
669 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
671 v_bfi_b32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
672 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
674 v_bfi_b32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
675 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
677 v_bfi_b32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
678 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
680 v_bfi_b32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
681 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
683 v_bfi_b32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
684 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
686 v_bfi_b32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
687 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
689 v_bfi_b32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
690 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
692 v_bfi_b32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
693 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
695 v_bfi_b32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
696 // GFX11
: [0x05,0x00,0x12,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
698 v_bfi_b32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
699 // GFX11
: [0xff,0x00,0x12,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
701 v_bfm_b32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
702 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
704 v_bfm_b32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
705 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
707 v_bfm_b32_e64_dpp v5
, v1
, v2 row_mirror
708 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
710 v_bfm_b32_e64_dpp v5
, v1
, v2 row_half_mirror
711 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
713 v_bfm_b32_e64_dpp v5
, v1
, v2 row_shl
:1
714 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
716 v_bfm_b32_e64_dpp v5
, v1
, v2 row_shl
:15
717 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
719 v_bfm_b32_e64_dpp v5
, v1
, v2 row_shr
:1
720 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
722 v_bfm_b32_e64_dpp v5
, v1
, v2 row_shr
:15
723 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
725 v_bfm_b32_e64_dpp v5
, v1
, v2 row_ror
:1
726 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
728 v_bfm_b32_e64_dpp v5
, v1
, v2 row_ror
:15
729 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
731 v_bfm_b32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
732 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
734 v_bfm_b32_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
735 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
737 v_bfm_b32_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
738 // GFX11
: [0x05,0x00,0x1d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
740 v_bfm_b32_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
741 // GFX11
: [0xff,0x00,0x1d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
743 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s3 quad_perm
:[3,2,1,0]
744 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x1b,0x00,0xff]
745 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
747 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s3 quad_perm
:[0,1,2,3]
748 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0xe4,0x00,0xff]
749 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
751 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s3 row_mirror
752 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x40,0x01,0xff]
753 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
755 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s3 row_half_mirror
756 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x41,0x01,0xff]
757 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
759 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s3 row_shl
:1
760 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x01,0x01,0xff]
761 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
763 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s3 row_shl
:15
764 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x0f,0x01,0xff]
765 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
767 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s3 row_shr
:1
768 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x11,0x01,0xff]
769 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
771 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s3 row_shr
:15
772 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x1f,0x01,0xff]
773 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
775 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s3 row_ror
:1
776 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x0e,0x00,0x01,0x21,0x01,0xff]
777 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
779 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s105 row_ror
:15
780 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x2f,0x01,0xff]
781 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
783 v_cndmask_b16_e64_dpp v5
, v1
, v2
, vcc_hi row_share
:0 row_mask
:0xf bank_mask
:0xf
784 // W32
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x50,0x01,0xff]
785 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
787 v_cndmask_b16_e64_dpp v5
, |v1|
, -v2
, vcc_lo row_share
:15 row_mask
:0x0 bank_mask
:0x1
788 // W32
: [0x05,0x01,0x5d,0xd6,0xfa,0x04,0xaa,0x41,0x01,0x5f,0x01,0x01]
789 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
791 v_cndmask_b16_e64_dpp v5
, -v1
, |v2|
, ttmp15 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
792 // W32
: [0x05,0x02,0x5d,0xd6,0xfa,0x04,0xee,0x21,0x01,0x60,0x09,0x13]
793 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
795 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[6:7] quad_perm
:[3,2,1,0]
796 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1b,0x00,0xff]
797 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
799 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[6:7] quad_perm
:[0,1,2,3]
800 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0xe4,0x00,0xff]
801 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
803 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[6:7] row_mirror
804 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x40,0x01,0xff]
805 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
807 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[6:7] row_half_mirror
808 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x41,0x01,0xff]
809 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
811 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[6:7] row_shl
:1
812 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x01,0x01,0xff]
813 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
815 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[6:7] row_shl
:15
816 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x0f,0x01,0xff]
817 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
819 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[6:7] row_shr
:1
820 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x11,0x01,0xff]
821 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
823 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[6:7] row_shr
:15
824 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x1f,0x01,0xff]
825 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
827 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[6:7] row_ror
:1
828 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x21,0x01,0xff]
829 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
831 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[6:7] row_ror
:15
832 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0x1a,0x00,0x01,0x2f,0x01,0xff]
833 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
835 v_cndmask_b16_e64_dpp v5
, v1
, v2
, s
[104:105] row_share
:0 row_mask
:0xf bank_mask
:0xf
836 // W64
: [0x05,0x00,0x5d,0xd6,0xfa,0x04,0xa2,0x01,0x01,0x50,0x01,0xff]
837 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
839 v_cndmask_b16_e64_dpp v5
, |v1|
, -v2
, vcc row_share
:15 row_mask
:0x0 bank_mask
:0x1
840 // W64
: [0x05,0x01,0x5d,0xd6,0xfa,0x04,0xaa,0x41,0x01,0x5f,0x01,0x01]
841 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
843 v_cndmask_b16_e64_dpp v5
, -v1
, |v2|
, ttmp
[14:15] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
844 // W64
: [0x05,0x02,0x5d,0xd6,0xfa,0x04,0xea,0x21,0x01,0x60,0x09,0x13]
845 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
847 v_cndmask_b16_e64_dpp v255
, -|v255|
, -|v255|
, null row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
848 // GFX11
: [0xff,0x03,0x5d,0xd6,0xfa,0xfe,0xf3,0x61,0xff,0x6f,0x05,0x30]
850 v_cubeid_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
851 // GFX11
: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
853 v_cubeid_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
854 // GFX11
: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
856 v_cubeid_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
857 // GFX11
: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
859 v_cubeid_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
860 // GFX11
: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
862 v_cubeid_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
863 // GFX11
: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
865 v_cubeid_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
866 // GFX11
: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
868 v_cubeid_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
869 // GFX11
: [0x05,0x00,0x0c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
871 v_cubeid_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
872 // GFX11
: [0x05,0x01,0x0c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
874 v_cubeid_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
875 // GFX11
: [0x05,0x02,0x0c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
877 v_cubeid_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
878 // GFX11
: [0x05,0x04,0x0c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
880 v_cubeid_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
881 // GFX11
: [0x05,0x03,0x0c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
883 v_cubeid_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
884 // GFX11
: [0x05,0x05,0x0c,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
886 v_cubeid_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
887 // GFX11
: [0x05,0x06,0x0c,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
889 v_cubeid_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
890 // GFX11
: [0xff,0x87,0x0c,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
892 v_cubema_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
893 // GFX11
: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
895 v_cubema_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
896 // GFX11
: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
898 v_cubema_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
899 // GFX11
: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
901 v_cubema_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
902 // GFX11
: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
904 v_cubema_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
905 // GFX11
: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
907 v_cubema_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
908 // GFX11
: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
910 v_cubema_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
911 // GFX11
: [0x05,0x00,0x0f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
913 v_cubema_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
914 // GFX11
: [0x05,0x01,0x0f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
916 v_cubema_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
917 // GFX11
: [0x05,0x02,0x0f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
919 v_cubema_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
920 // GFX11
: [0x05,0x04,0x0f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
922 v_cubema_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
923 // GFX11
: [0x05,0x03,0x0f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
925 v_cubema_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
926 // GFX11
: [0x05,0x05,0x0f,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
928 v_cubema_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
929 // GFX11
: [0x05,0x06,0x0f,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
931 v_cubema_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
932 // GFX11
: [0xff,0x87,0x0f,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
934 v_cubesc_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
935 // GFX11
: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
937 v_cubesc_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
938 // GFX11
: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
940 v_cubesc_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
941 // GFX11
: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
943 v_cubesc_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
944 // GFX11
: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
946 v_cubesc_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
947 // GFX11
: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
949 v_cubesc_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
950 // GFX11
: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
952 v_cubesc_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
953 // GFX11
: [0x05,0x00,0x0d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
955 v_cubesc_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
956 // GFX11
: [0x05,0x01,0x0d,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
958 v_cubesc_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
959 // GFX11
: [0x05,0x02,0x0d,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
961 v_cubesc_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
962 // GFX11
: [0x05,0x04,0x0d,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
964 v_cubesc_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
965 // GFX11
: [0x05,0x03,0x0d,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
967 v_cubesc_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
968 // GFX11
: [0x05,0x05,0x0d,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
970 v_cubesc_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
971 // GFX11
: [0x05,0x06,0x0d,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
973 v_cubesc_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
974 // GFX11
: [0xff,0x87,0x0d,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
976 v_cubetc_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
977 // GFX11
: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
979 v_cubetc_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
980 // GFX11
: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
982 v_cubetc_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
983 // GFX11
: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
985 v_cubetc_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
986 // GFX11
: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
988 v_cubetc_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
989 // GFX11
: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
991 v_cubetc_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
992 // GFX11
: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
994 v_cubetc_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
995 // GFX11
: [0x05,0x00,0x0e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
997 v_cubetc_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
998 // GFX11
: [0x05,0x01,0x0e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
1000 v_cubetc_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
1001 // GFX11
: [0x05,0x02,0x0e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
1003 v_cubetc_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
1004 // GFX11
: [0x05,0x04,0x0e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
1006 v_cubetc_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
1007 // GFX11
: [0x05,0x03,0x0e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
1009 v_cubetc_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1010 // GFX11
: [0x05,0x05,0x0e,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
1012 v_cubetc_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1013 // GFX11
: [0x05,0x06,0x0e,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
1015 v_cubetc_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1016 // GFX11
: [0xff,0x87,0x0e,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
1018 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1019 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1021 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1022 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1024 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 row_mirror
1025 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1027 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 row_half_mirror
1028 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1030 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 row_shl
:1
1031 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1033 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 row_shl
:15
1034 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1036 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 row_shr
:1
1037 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1039 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 row_shr
:15
1040 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1042 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 row_ror
:1
1043 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1045 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 row_ror
:15
1046 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1048 v_cvt_pk_i16_f32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1049 // GFX11
: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1051 v_cvt_pk_i16_f32_e64_dpp v5
, |v1|
, -v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1052 // GFX11
: [0x05,0x01,0x06,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
1054 v_cvt_pk_i16_f32_e64_dpp v5
, -v1
, |v2| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1055 // GFX11
: [0x05,0x02,0x06,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
1057 v_cvt_pk_i16_f32_e64_dpp v255
, -|v255|
, -|v255| row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1058 // GFX11
: [0xff,0x03,0x06,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
1060 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1061 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1063 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1064 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1066 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_mirror
1067 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1069 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_half_mirror
1070 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1072 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_shl
:1
1073 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1075 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_shl
:15
1076 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1078 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_shr
:1
1079 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1081 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_shr
:15
1082 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1084 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_ror
:1
1085 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1087 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_ror
:15
1088 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1090 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1091 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1093 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1094 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
1096 v_cvt_pk_i16_i32_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1097 // GFX11
: [0x05,0x00,0x24,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
1099 v_cvt_pk_i16_i32_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1100 // GFX11
: [0xff,0x00,0x24,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
1102 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1103 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1105 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1106 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1108 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_mirror
1109 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1111 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_half_mirror
1112 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1114 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_shl
:1
1115 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1117 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_shl
:15
1118 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1120 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_shr
:1
1121 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1123 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_shr
:15
1124 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1126 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_ror
:1
1127 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1129 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_ror
:15
1130 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1132 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1133 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1135 v_cvt_pk_norm_i16_f16_e64_dpp v5
, |v1|
, -v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1136 // GFX11
: [0x05,0x01,0x12,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
1138 v_cvt_pk_norm_i16_f16_e64_dpp v5
, -v1
, |v2| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1139 // GFX11
: [0x05,0x02,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
1141 v_cvt_pk_norm_i16_f16_e64_dpp v255
, -|v255|
, -|v255| row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1142 // GFX11
: [0xff,0x03,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
1144 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1145 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1147 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1148 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1150 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_mirror
1151 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1153 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_half_mirror
1154 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1156 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_shl
:1
1157 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1159 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_shl
:15
1160 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1162 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_shr
:1
1163 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1165 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_shr
:15
1166 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1168 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_ror
:1
1169 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1171 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_ror
:15
1172 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1174 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1175 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1177 v_cvt_pk_norm_u16_f16_e64_dpp v5
, |v1|
, -v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1178 // GFX11
: [0x05,0x01,0x13,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
1180 v_cvt_pk_norm_u16_f16_e64_dpp v5
, -v1
, |v2| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1181 // GFX11
: [0x05,0x02,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
1183 v_cvt_pk_norm_u16_f16_e64_dpp v255
, -|v255|
, -|v255| row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1184 // GFX11
: [0xff,0x03,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
1186 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1187 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1189 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1190 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1192 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 row_mirror
1193 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1195 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 row_half_mirror
1196 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1198 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 row_shl
:1
1199 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1201 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 row_shl
:15
1202 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1204 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 row_shr
:1
1205 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1207 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 row_shr
:15
1208 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1210 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 row_ror
:1
1211 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1213 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 row_ror
:15
1214 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1216 v_cvt_pk_u16_f32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1217 // GFX11
: [0x05,0x00,0x07,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1219 v_cvt_pk_u16_f32_e64_dpp v5
, |v1|
, -v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1220 // GFX11
: [0x05,0x01,0x07,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
1222 v_cvt_pk_u16_f32_e64_dpp v5
, -v1
, |v2| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1223 // GFX11
: [0x05,0x02,0x07,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
1225 v_cvt_pk_u16_f32_e64_dpp v255
, -|v255|
, -|v255| row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1226 // GFX11
: [0xff,0x03,0x07,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
1228 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1229 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1231 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1232 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1234 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_mirror
1235 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1237 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_half_mirror
1238 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1240 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_shl
:1
1241 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1243 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_shl
:15
1244 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1246 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_shr
:1
1247 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1249 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_shr
:15
1250 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1252 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_ror
:1
1253 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1255 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_ror
:15
1256 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1258 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1259 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1261 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1262 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
1264 v_cvt_pk_u16_u32_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1265 // GFX11
: [0x05,0x00,0x23,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
1267 v_cvt_pk_u16_u32_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1268 // GFX11
: [0xff,0x00,0x23,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
1270 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1271 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1273 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1274 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1276 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
1277 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1279 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
1280 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
1282 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
1283 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
1285 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
1286 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
1288 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
1289 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
1291 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
1292 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
1294 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
1295 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
1297 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
1298 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
1300 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
1301 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
1303 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1304 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
1306 v_cvt_pk_u8_f32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1307 // GFX11
: [0x05,0x00,0x26,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
1309 v_cvt_pk_u8_f32_e64_dpp v255
, -|v255|
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1310 // GFX11
: [0xff,0x01,0x26,0xd6,0xfa,0xfe,0xf7,0x23,0xff,0x6f,0x05,0x30]
1312 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1313 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1315 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1316 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1318 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_mirror
1319 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1321 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_half_mirror
1322 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1324 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_shl
:1
1325 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1327 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_shl
:15
1328 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1330 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_shr
:1
1331 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1333 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_shr
:15
1334 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1336 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_ror
:1
1337 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1339 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_ror
:15
1340 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1342 v_cvt_pk_norm_i16_f16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1343 // GFX11
: [0x05,0x00,0x12,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1345 v_cvt_pk_norm_i16_f16_e64_dpp v5
, |v1|
, -v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1346 // GFX11
: [0x05,0x01,0x12,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
1348 v_cvt_pk_norm_i16_f16_e64_dpp v5
, -v1
, |v2| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1349 // GFX11
: [0x05,0x02,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
1351 v_cvt_pk_norm_i16_f16_e64_dpp v255
, -|v255|
, -|v255| row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1352 // GFX11
: [0xff,0x03,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
1354 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1355 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1357 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1358 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1360 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 row_mirror
1361 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1363 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 row_half_mirror
1364 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1366 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 row_shl
:1
1367 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1369 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 row_shl
:15
1370 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1372 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 row_shr
:1
1373 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1375 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 row_shr
:15
1376 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1378 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 row_ror
:1
1379 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1381 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 row_ror
:15
1382 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1384 v_cvt_pk_norm_i16_f32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1385 // GFX11
: [0x05,0x00,0x21,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1387 v_cvt_pk_norm_i16_f32_e64_dpp v5
, |v1|
, -v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1388 // GFX11
: [0x05,0x01,0x21,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
1390 v_cvt_pk_norm_i16_f32_e64_dpp v5
, -v1
, |v2| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1391 // GFX11
: [0x05,0x02,0x21,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
1393 v_cvt_pk_norm_i16_f32_e64_dpp v255
, -|v255|
, -|v255| row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1394 // GFX11
: [0xff,0x03,0x21,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
1396 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1397 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1399 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1400 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1402 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_mirror
1403 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1405 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_half_mirror
1406 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1408 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_shl
:1
1409 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1411 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_shl
:15
1412 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1414 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_shr
:1
1415 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1417 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_shr
:15
1418 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1420 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_ror
:1
1421 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1423 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_ror
:15
1424 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1426 v_cvt_pk_norm_u16_f16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1427 // GFX11
: [0x05,0x00,0x13,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1429 v_cvt_pk_norm_u16_f16_e64_dpp v5
, |v1|
, -v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1430 // GFX11
: [0x05,0x01,0x13,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
1432 v_cvt_pk_norm_u16_f16_e64_dpp v5
, -v1
, |v2| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1433 // GFX11
: [0x05,0x02,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
1435 v_cvt_pk_norm_u16_f16_e64_dpp v255
, -|v255|
, -|v255| row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1436 // GFX11
: [0xff,0x03,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
1438 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1439 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1441 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1442 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1444 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 row_mirror
1445 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1447 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 row_half_mirror
1448 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1450 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 row_shl
:1
1451 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1453 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 row_shl
:15
1454 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1456 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 row_shr
:1
1457 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1459 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 row_shr
:15
1460 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1462 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 row_ror
:1
1463 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1465 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 row_ror
:15
1466 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1468 v_cvt_pk_norm_u16_f32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1469 // GFX11
: [0x05,0x00,0x22,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1471 v_cvt_pk_norm_u16_f32_e64_dpp v5
, |v1|
, -v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1472 // GFX11
: [0x05,0x01,0x22,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
1474 v_cvt_pk_norm_u16_f32_e64_dpp v5
, -v1
, |v2| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1475 // GFX11
: [0x05,0x02,0x22,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
1477 v_cvt_pk_norm_u16_f32_e64_dpp v255
, -|v255|
, -|v255| row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1478 // GFX11
: [0xff,0x03,0x22,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
1480 v_div_fixup_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1481 // GFX11
: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1483 v_div_fixup_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1484 // GFX11
: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1486 v_div_fixup_f16_e64_dpp v5
, v1
, v2
, v3 row_mirror
1487 // GFX11
: [0x05,0x00,0x54,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1489 v_div_fixup_f16_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
1490 // GFX11
: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
1492 v_div_fixup_f16_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
1493 // GFX11
: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
1495 v_div_fixup_f16_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
1496 // GFX11
: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
1498 v_div_fixup_f16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
1499 // GFX11
: [0x05,0x00,0x54,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
1501 v_div_fixup_f16_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
1502 // GFX11
: [0x05,0x01,0x54,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
1504 v_div_fixup_f16_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
1505 // GFX11
: [0x05,0x02,0x54,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
1507 v_div_fixup_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
1508 // GFX11
: [0x05,0x04,0x54,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
1510 v_div_fixup_f16_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
1511 // GFX11
: [0x05,0x03,0x54,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
1513 v_div_fixup_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1| row_share
:15 row_mask
:0x0 bank_mask
:0x1
1514 // GFX11
: [0x05,0x05,0x54,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
1516 v_div_fixup_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1517 // GFX11
: [0x05,0x06,0x54,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13]
1519 v_div_fixup_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1520 // GFX11
: [0xff,0x87,0x54,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30]
1522 v_fma_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1523 // GFX11
: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1525 v_fma_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1526 // GFX11
: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1528 v_fma_f16_e64_dpp v5
, v1
, v2
, v3 row_mirror
1529 // GFX11
: [0x05,0x00,0x48,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1531 v_fma_f16_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
1532 // GFX11
: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
1534 v_fma_f16_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
1535 // GFX11
: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
1537 v_fma_f16_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
1538 // GFX11
: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
1540 v_fma_f16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
1541 // GFX11
: [0x05,0x00,0x48,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
1543 v_fma_f16_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
1544 // GFX11
: [0x05,0x01,0x48,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
1546 v_fma_f16_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
1547 // GFX11
: [0x05,0x02,0x48,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
1549 v_fma_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
1550 // GFX11
: [0x05,0x04,0x48,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
1552 v_fma_f16_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
1553 // GFX11
: [0x05,0x03,0x48,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
1555 v_fma_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1| row_share
:15 row_mask
:0x0 bank_mask
:0x1
1556 // GFX11
: [0x05,0x05,0x48,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
1558 v_fma_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1559 // GFX11
: [0x05,0x06,0x48,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13]
1561 v_fma_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1562 // GFX11
: [0xff,0x87,0x48,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30]
1564 v_fma_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1565 // GFX11
: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1567 v_fma_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1568 // GFX11
: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1570 v_fma_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
1571 // GFX11
: [0x05,0x00,0x13,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1573 v_fma_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
1574 // GFX11
: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
1576 v_fma_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
1577 // GFX11
: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
1579 v_fma_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
1580 // GFX11
: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
1582 v_fma_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
1583 // GFX11
: [0x05,0x00,0x13,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
1585 v_fma_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
1586 // GFX11
: [0x05,0x01,0x13,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
1588 v_fma_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
1589 // GFX11
: [0x05,0x02,0x13,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
1591 v_fma_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
1592 // GFX11
: [0x05,0x04,0x13,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
1594 v_fma_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
1595 // GFX11
: [0x05,0x03,0x13,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
1597 v_fma_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1598 // GFX11
: [0x05,0x05,0x13,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
1600 v_fma_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1601 // GFX11
: [0x05,0x06,0x13,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
1603 v_fma_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1604 // GFX11
: [0xff,0x87,0x13,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
1606 v_ldexp_f32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1607 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1609 v_ldexp_f32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1610 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1612 v_ldexp_f32_e64_dpp v5
, v1
, v2 row_mirror
1613 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1615 v_ldexp_f32_e64_dpp v5
, v1
, v2 row_half_mirror
1616 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1618 v_ldexp_f32_e64_dpp v5
, v1
, v2 row_shl
:1
1619 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1621 v_ldexp_f32_e64_dpp v5
, v1
, v2 row_shl
:15
1622 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1624 v_ldexp_f32_e64_dpp v5
, v1
, v2 row_shr
:1
1625 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1627 v_ldexp_f32_e64_dpp v5
, v1
, v2 row_shr
:15
1628 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1630 v_ldexp_f32_e64_dpp v5
, v1
, v2 row_ror
:1
1631 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1633 v_ldexp_f32_e64_dpp v5
, v1
, v2 row_ror
:15
1634 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1636 v_ldexp_f32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1637 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1639 v_ldexp_f32_e64_dpp v5
, v1
, v2
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1640 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x08,0x01,0x5f,0x01,0x01]
1642 v_ldexp_f32_e64_dpp v5
, v1
, v2
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1643 // GFX11
: [0x05,0x00,0x1c,0xd7,0xfa,0x04,0x02,0x10,0x01,0x60,0x09,0x13]
1645 v_ldexp_f32_e64_dpp v255
, -|v255|
, v255 clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1646 // GFX11
: [0xff,0x81,0x1c,0xd7,0xfa,0xfe,0x03,0x38,0xff,0x6f,0x05,0x30]
1648 v_lerp_u8_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1649 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1651 v_lerp_u8_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1652 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1654 v_lerp_u8_e64_dpp v5
, v1
, v2
, v3 row_mirror
1655 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1657 v_lerp_u8_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
1658 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
1660 v_lerp_u8_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
1661 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
1663 v_lerp_u8_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
1664 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
1666 v_lerp_u8_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
1667 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
1669 v_lerp_u8_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
1670 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
1672 v_lerp_u8_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
1673 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
1675 v_lerp_u8_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
1676 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
1678 v_lerp_u8_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
1679 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
1681 v_lerp_u8_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1682 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
1684 v_lerp_u8_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1685 // GFX11
: [0x05,0x00,0x15,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
1687 v_lerp_u8_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1688 // GFX11
: [0xff,0x00,0x15,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
1690 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1691 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1693 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1694 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1696 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
1697 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1699 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
1700 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
1702 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
1703 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
1705 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
1706 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
1708 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
1709 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
1711 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
1712 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
1714 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
1715 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
1717 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
1718 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
1720 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
1721 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
1723 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1724 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
1726 v_lshl_add_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1727 // GFX11
: [0x05,0x00,0x46,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
1729 v_lshl_add_u32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1730 // GFX11
: [0xff,0x00,0x46,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
1732 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1733 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1735 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1736 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1738 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, v3 row_mirror
1739 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1741 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
1742 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
1744 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
1745 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
1747 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
1748 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
1750 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
1751 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
1753 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
1754 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
1756 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
1757 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
1759 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
1760 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
1762 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
1763 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
1765 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1766 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
1768 v_lshl_or_b32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1769 // GFX11
: [0x05,0x00,0x56,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
1771 v_lshl_or_b32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1772 // GFX11
: [0xff,0x00,0x56,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
1774 v_lshlrev_b16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1775 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1777 v_lshlrev_b16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1778 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1780 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_mirror
1781 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1783 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_half_mirror
1784 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1786 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_shl
:1
1787 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1789 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_shl
:15
1790 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1792 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_shr
:1
1793 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1795 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_shr
:15
1796 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1798 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_ror
:1
1799 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1801 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_ror
:15
1802 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1804 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1805 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1807 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1808 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
1810 v_lshlrev_b16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1811 // GFX11
: [0x05,0x00,0x38,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
1813 v_lshlrev_b16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1814 // GFX11
: [0xff,0x00,0x38,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
1816 v_lshrrev_b16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
1817 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
1819 v_lshrrev_b16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
1820 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
1822 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_mirror
1823 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
1825 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_half_mirror
1826 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
1828 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_shl
:1
1829 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
1831 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_shl
:15
1832 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
1834 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_shr
:1
1835 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
1837 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_shr
:15
1838 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
1840 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_ror
:1
1841 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
1843 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_ror
:15
1844 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
1846 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
1847 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
1849 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1850 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
1852 v_lshrrev_b16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1853 // GFX11
: [0x05,0x00,0x39,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
1855 v_lshrrev_b16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1856 // GFX11
: [0xff,0x00,0x39,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
1858 v_mad_i16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1859 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1861 v_mad_i16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1862 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1864 v_mad_i16_e64_dpp v5
, v1
, v2
, v3 row_mirror
1865 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1867 v_mad_i16_e64_dpp v5
, v1
, v2
, v3 row_half_mirror
1868 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
1870 v_mad_i16_e64_dpp v5
, v1
, v2
, v255 row_shl
:1
1871 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
1873 v_mad_i16_e64_dpp v5
, v1
, v2
, s105 row_shl
:15
1874 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
1876 v_mad_i16_e64_dpp v5
, v1
, v2
, vcc_hi row_shr
:1
1877 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
1879 v_mad_i16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:15
1880 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
1882 v_mad_i16_e64_dpp v5
, v1
, v2
, ttmp15 row_ror
:1
1883 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
1885 v_mad_i16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:15
1886 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
1888 v_mad_i16_e64_dpp v5
, v1
, v2
, exec_lo row_share
:0 row_mask
:0xf bank_mask
:0xf
1889 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
1891 v_mad_i16_e64_dpp v5
, v1
, v2
, null row_share
:15 row_mask
:0x0 bank_mask
:0x1
1892 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
1894 v_mad_i16_e64_dpp v5
, v1
, v2
, -1 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1895 // GFX11
: [0x05,0x00,0x53,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
1897 v_mad_i16_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1898 // GFX11
: [0xff,0x80,0x53,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
1900 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1901 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1903 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1904 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1906 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, v3 row_mirror
1907 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1909 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
1910 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
1912 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
1913 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
1915 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
1916 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
1918 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
1919 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
1921 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
1922 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
1924 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
1925 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
1927 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
1928 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
1930 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
1931 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
1933 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1934 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
1936 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1937 // GFX11
: [0x05,0x00,0x5a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
1939 v_mad_i32_i16_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1940 // GFX11
: [0xff,0x80,0x5a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
1942 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1943 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1945 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1946 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1948 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, v3 row_mirror
1949 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1951 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
1952 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
1954 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
1955 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
1957 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
1958 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
1960 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
1961 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
1963 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
1964 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
1966 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
1967 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
1969 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
1970 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
1972 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
1973 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
1975 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
1976 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
1978 v_mad_i32_i24_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
1979 // GFX11
: [0x05,0x00,0x0a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
1981 v_mad_i32_i24_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
1982 // GFX11
: [0xff,0x80,0x0a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
1984 v_mad_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
1985 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
1987 v_mad_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
1988 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
1990 v_mad_u16_e64_dpp v5
, v1
, v2
, v3 row_mirror
1991 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
1993 v_mad_u16_e64_dpp v5
, v1
, v2
, v3 row_half_mirror
1994 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
1996 v_mad_u16_e64_dpp v5
, v1
, v2
, v255 row_shl
:1
1997 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
1999 v_mad_u16_e64_dpp v5
, v1
, v2
, s105 row_shl
:15
2000 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
2002 v_mad_u16_e64_dpp v5
, v1
, v2
, vcc_hi row_shr
:1
2003 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
2005 v_mad_u16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:15
2006 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
2008 v_mad_u16_e64_dpp v5
, v1
, v2
, ttmp15 row_ror
:1
2009 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
2011 v_mad_u16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:15
2012 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
2014 v_mad_u16_e64_dpp v5
, v1
, v2
, exec_lo row_share
:0 row_mask
:0xf bank_mask
:0xf
2015 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
2017 v_mad_u16_e64_dpp v5
, v1
, v2
, null row_share
:15 row_mask
:0x0 bank_mask
:0x1
2018 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
2020 v_mad_u16_e64_dpp v5
, v1
, v2
, -1 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2021 // GFX11
: [0x05,0x00,0x41,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
2023 v_mad_u16_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2024 // GFX11
: [0xff,0x80,0x41,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2026 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2027 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2029 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2030 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2032 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, v3 row_mirror
2033 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2035 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2036 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2038 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2039 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2041 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2042 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2044 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2045 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2047 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
2048 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
2050 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
2051 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
2053 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
2054 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
2056 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2057 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
2059 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2060 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
2062 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2063 // GFX11
: [0x05,0x00,0x59,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
2065 v_mad_u32_u16_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2066 // GFX11
: [0xff,0x80,0x59,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2068 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2069 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2071 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2072 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2074 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, v3 row_mirror
2075 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2077 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2078 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2080 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2081 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2083 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2084 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2086 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2087 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2089 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
2090 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
2092 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
2093 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
2095 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
2096 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
2098 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2099 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
2101 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2102 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
2104 v_mad_u32_u24_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2105 // GFX11
: [0x05,0x00,0x0b,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
2107 v_mad_u32_u24_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2108 // GFX11
: [0xff,0x80,0x0b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2110 v_max3_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2111 // GFX11
: [0x05,0x00,0x4c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2113 v_max3_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2114 // GFX11
: [0x05,0x00,0x4c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2116 v_max3_f16_e64_dpp v5
, v1
, v2
, v3 row_mirror
2117 // GFX11
: [0x05,0x00,0x4c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2119 v_max3_f16_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2120 // GFX11
: [0x05,0x00,0x4c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2122 v_max3_f16_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2123 // GFX11
: [0x05,0x00,0x4c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2125 v_max3_f16_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2126 // GFX11
: [0x05,0x00,0x4c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2128 v_max3_f16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2129 // GFX11
: [0x05,0x00,0x4c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2131 v_max3_f16_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
2132 // GFX11
: [0x05,0x01,0x4c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
2134 v_max3_f16_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
2135 // GFX11
: [0x05,0x02,0x4c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
2137 v_max3_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
2138 // GFX11
: [0x05,0x04,0x4c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
2140 v_max3_f16_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2141 // GFX11
: [0x05,0x03,0x4c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
2143 v_max3_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1| row_share
:15 row_mask
:0x0 bank_mask
:0x1
2144 // GFX11
: [0x05,0x05,0x4c,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
2146 v_max3_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2147 // GFX11
: [0x05,0x06,0x4c,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13]
2149 v_max3_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2150 // GFX11
: [0xff,0x87,0x4c,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30]
2152 v_max3_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2153 // GFX11
: [0x05,0x00,0x1c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2155 v_max3_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2156 // GFX11
: [0x05,0x00,0x1c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2158 v_max3_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
2159 // GFX11
: [0x05,0x00,0x1c,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2161 v_max3_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2162 // GFX11
: [0x05,0x00,0x1c,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2164 v_max3_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2165 // GFX11
: [0x05,0x00,0x1c,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2167 v_max3_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2168 // GFX11
: [0x05,0x00,0x1c,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2170 v_max3_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2171 // GFX11
: [0x05,0x00,0x1c,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2173 v_max3_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
2174 // GFX11
: [0x05,0x01,0x1c,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
2176 v_max3_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
2177 // GFX11
: [0x05,0x02,0x1c,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
2179 v_max3_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
2180 // GFX11
: [0x05,0x04,0x1c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
2182 v_max3_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2183 // GFX11
: [0x05,0x03,0x1c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
2185 v_max3_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2186 // GFX11
: [0x05,0x05,0x1c,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
2188 v_max3_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2189 // GFX11
: [0x05,0x06,0x1c,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
2191 v_max3_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2192 // GFX11
: [0xff,0x87,0x1c,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
2194 v_max3_i16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2195 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2197 v_max3_i16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2198 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2200 v_max3_i16_e64_dpp v5
, v1
, v2
, v3 row_mirror
2201 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2203 v_max3_i16_e64_dpp v5
, v1
, v2
, v3 row_half_mirror
2204 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
2206 v_max3_i16_e64_dpp v5
, v1
, v2
, v255 row_shl
:1
2207 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
2209 v_max3_i16_e64_dpp v5
, v1
, v2
, s105 row_shl
:15
2210 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
2212 v_max3_i16_e64_dpp v5
, v1
, v2
, vcc_hi row_shr
:1
2213 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
2215 v_max3_i16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:15
2216 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
2218 v_max3_i16_e64_dpp v5
, v1
, v2
, ttmp15 row_ror
:1
2219 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
2221 v_max3_i16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:15
2222 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
2224 v_max3_i16_e64_dpp v5
, v1
, v2
, exec_lo row_share
:0 row_mask
:0xf bank_mask
:0xf
2225 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
2227 v_max3_i16_e64_dpp v5
, v1
, v2
, null row_share
:15 row_mask
:0x0 bank_mask
:0x1
2228 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
2230 v_max3_i16_e64_dpp v5
, v1
, v2
, -1 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2231 // GFX11
: [0x05,0x00,0x4d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
2233 v_max3_i16_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2234 // GFX11
: [0xff,0x00,0x4d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2236 v_max3_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2237 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2239 v_max3_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2240 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2242 v_max3_i32_e64_dpp v5
, v1
, v2
, v3 row_mirror
2243 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2245 v_max3_i32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2246 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2248 v_max3_i32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2249 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2251 v_max3_i32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2252 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2254 v_max3_i32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2255 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2257 v_max3_i32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
2258 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
2260 v_max3_i32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
2261 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
2263 v_max3_i32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
2264 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
2266 v_max3_i32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2267 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
2269 v_max3_i32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2270 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
2272 v_max3_i32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2273 // GFX11
: [0x05,0x00,0x1d,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
2275 v_max3_i32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2276 // GFX11
: [0xff,0x00,0x1d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2278 v_max3_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2279 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2281 v_max3_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2282 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2284 v_max3_u16_e64_dpp v5
, v1
, v2
, v3 row_mirror
2285 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2287 v_max3_u16_e64_dpp v5
, v1
, v2
, v3 row_half_mirror
2288 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
2290 v_max3_u16_e64_dpp v5
, v1
, v2
, v255 row_shl
:1
2291 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
2293 v_max3_u16_e64_dpp v5
, v1
, v2
, s105 row_shl
:15
2294 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
2296 v_max3_u16_e64_dpp v5
, v1
, v2
, vcc_hi row_shr
:1
2297 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
2299 v_max3_u16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:15
2300 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
2302 v_max3_u16_e64_dpp v5
, v1
, v2
, ttmp15 row_ror
:1
2303 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
2305 v_max3_u16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:15
2306 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
2308 v_max3_u16_e64_dpp v5
, v1
, v2
, exec_lo row_share
:0 row_mask
:0xf bank_mask
:0xf
2309 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
2311 v_max3_u16_e64_dpp v5
, v1
, v2
, null row_share
:15 row_mask
:0x0 bank_mask
:0x1
2312 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
2314 v_max3_u16_e64_dpp v5
, v1
, v2
, -1 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2315 // GFX11
: [0x05,0x00,0x4e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
2317 v_max3_u16_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2318 // GFX11
: [0xff,0x00,0x4e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2320 v_max3_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2321 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2323 v_max3_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2324 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2326 v_max3_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
2327 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2329 v_max3_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2330 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2332 v_max3_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2333 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2335 v_max3_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2336 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2338 v_max3_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2339 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2341 v_max3_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
2342 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
2344 v_max3_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
2345 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
2347 v_max3_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
2348 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
2350 v_max3_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2351 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
2353 v_max3_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2354 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
2356 v_max3_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2357 // GFX11
: [0x05,0x00,0x1e,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
2359 v_max3_u32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2360 // GFX11
: [0xff,0x00,0x1e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2362 v_max_i16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
2363 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
2365 v_max_i16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
2366 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
2368 v_max_i16_e64_dpp v5
, v1
, v2 row_mirror
2369 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
2371 v_max_i16_e64_dpp v5
, v1
, v2 row_half_mirror
2372 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
2374 v_max_i16_e64_dpp v5
, v1
, v2 row_shl
:1
2375 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
2377 v_max_i16_e64_dpp v5
, v1
, v2 row_shl
:15
2378 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
2380 v_max_i16_e64_dpp v5
, v1
, v2 row_shr
:1
2381 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
2383 v_max_i16_e64_dpp v5
, v1
, v2 row_shr
:15
2384 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
2386 v_max_i16_e64_dpp v5
, v1
, v2 row_ror
:1
2387 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
2389 v_max_i16_e64_dpp v5
, v1
, v2 row_ror
:15
2390 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
2392 v_max_i16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
2393 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
2395 v_max_i16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2396 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
2398 v_max_i16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2399 // GFX11
: [0x05,0x00,0x0a,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
2401 v_max_i16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2402 // GFX11
: [0xff,0x00,0x0a,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
2404 v_max_u16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
2405 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
2407 v_max_u16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
2408 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
2410 v_max_u16_e64_dpp v5
, v1
, v2 row_mirror
2411 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
2413 v_max_u16_e64_dpp v5
, v1
, v2 row_half_mirror
2414 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
2416 v_max_u16_e64_dpp v5
, v1
, v2 row_shl
:1
2417 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
2419 v_max_u16_e64_dpp v5
, v1
, v2 row_shl
:15
2420 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
2422 v_max_u16_e64_dpp v5
, v1
, v2 row_shr
:1
2423 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
2425 v_max_u16_e64_dpp v5
, v1
, v2 row_shr
:15
2426 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
2428 v_max_u16_e64_dpp v5
, v1
, v2 row_ror
:1
2429 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
2431 v_max_u16_e64_dpp v5
, v1
, v2 row_ror
:15
2432 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
2434 v_max_u16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
2435 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
2437 v_max_u16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2438 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
2440 v_max_u16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2441 // GFX11
: [0x05,0x00,0x09,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
2443 v_max_u16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2444 // GFX11
: [0xff,0x00,0x09,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
2446 v_maxmin_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2447 // GFX11
: [0x05,0x00,0x60,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2449 v_maxmin_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2450 // GFX11
: [0x05,0x00,0x60,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2452 v_maxmin_f16_e64_dpp v5
, v1
, v2
, v3 row_mirror
2453 // GFX11
: [0x05,0x00,0x60,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2455 v_maxmin_f16_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2456 // GFX11
: [0x05,0x00,0x60,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2458 v_maxmin_f16_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2459 // GFX11
: [0x05,0x00,0x60,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2461 v_maxmin_f16_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2462 // GFX11
: [0x05,0x00,0x60,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2464 v_maxmin_f16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2465 // GFX11
: [0x05,0x00,0x60,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2467 v_maxmin_f16_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
2468 // GFX11
: [0x05,0x01,0x60,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
2470 v_maxmin_f16_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
2471 // GFX11
: [0x05,0x02,0x60,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
2473 v_maxmin_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
2474 // GFX11
: [0x05,0x04,0x60,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
2476 v_maxmin_f16_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2477 // GFX11
: [0x05,0x03,0x60,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
2479 v_maxmin_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2480 // GFX11
: [0x05,0x05,0x60,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
2482 v_maxmin_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2483 // GFX11
: [0x05,0x06,0x60,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
2485 v_maxmin_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2486 // GFX11
: [0xff,0x87,0x60,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
2488 v_maxmin_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2489 // GFX11
: [0x05,0x00,0x5e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2491 v_maxmin_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2492 // GFX11
: [0x05,0x00,0x5e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2494 v_maxmin_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
2495 // GFX11
: [0x05,0x00,0x5e,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2497 v_maxmin_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2498 // GFX11
: [0x05,0x00,0x5e,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2500 v_maxmin_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2501 // GFX11
: [0x05,0x00,0x5e,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2503 v_maxmin_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2504 // GFX11
: [0x05,0x00,0x5e,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2506 v_maxmin_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2507 // GFX11
: [0x05,0x00,0x5e,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2509 v_maxmin_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
2510 // GFX11
: [0x05,0x01,0x5e,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
2512 v_maxmin_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
2513 // GFX11
: [0x05,0x02,0x5e,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
2515 v_maxmin_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
2516 // GFX11
: [0x05,0x04,0x5e,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
2518 v_maxmin_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2519 // GFX11
: [0x05,0x03,0x5e,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
2521 v_maxmin_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2522 // GFX11
: [0x05,0x05,0x5e,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
2524 v_maxmin_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2525 // GFX11
: [0x05,0x06,0x5e,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
2527 v_maxmin_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2528 // GFX11
: [0xff,0x87,0x5e,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
2530 v_maxmin_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2531 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2533 v_maxmin_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2534 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2536 v_maxmin_i32_e64_dpp v5
, v1
, v2
, v3 row_mirror
2537 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2539 v_maxmin_i32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2540 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2542 v_maxmin_i32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2543 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2545 v_maxmin_i32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2546 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2548 v_maxmin_i32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2549 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2551 v_maxmin_i32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
2552 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
2554 v_maxmin_i32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
2555 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
2557 v_maxmin_i32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
2558 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
2560 v_maxmin_i32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2561 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
2563 v_maxmin_i32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2564 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
2566 v_maxmin_i32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2567 // GFX11
: [0x05,0x00,0x64,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
2569 v_maxmin_i32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2570 // GFX11
: [0xff,0x00,0x64,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2572 v_maxmin_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2573 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2575 v_maxmin_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2576 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2578 v_maxmin_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
2579 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2581 v_maxmin_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2582 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2584 v_maxmin_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2585 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2587 v_maxmin_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2588 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2590 v_maxmin_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2591 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2593 v_maxmin_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
2594 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
2596 v_maxmin_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
2597 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
2599 v_maxmin_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
2600 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
2602 v_maxmin_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2603 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
2605 v_maxmin_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2606 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
2608 v_maxmin_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2609 // GFX11
: [0x05,0x00,0x62,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
2611 v_maxmin_u32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2612 // GFX11
: [0xff,0x00,0x62,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2614 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
2615 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
2617 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
2618 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
2620 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_mirror
2621 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
2623 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_half_mirror
2624 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
2626 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_shl
:1
2627 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
2629 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_shl
:15
2630 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
2632 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_shr
:1
2633 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
2635 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_shr
:15
2636 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
2638 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_ror
:1
2639 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
2641 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_ror
:15
2642 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
2644 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
2645 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
2647 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2648 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
2650 v_mbcnt_hi_u32_b32_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2651 // GFX11
: [0x05,0x00,0x20,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
2653 v_mbcnt_hi_u32_b32_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2654 // GFX11
: [0xff,0x00,0x20,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
2656 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
2657 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
2659 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
2660 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
2662 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_mirror
2663 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
2665 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_half_mirror
2666 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
2668 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_shl
:1
2669 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
2671 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_shl
:15
2672 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
2674 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_shr
:1
2675 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
2677 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_shr
:15
2678 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
2680 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_ror
:1
2681 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
2683 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_ror
:15
2684 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
2686 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
2687 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
2689 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2690 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
2692 v_mbcnt_lo_u32_b32_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2693 // GFX11
: [0x05,0x00,0x1f,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
2695 v_mbcnt_lo_u32_b32_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2696 // GFX11
: [0xff,0x00,0x1f,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
2698 v_med3_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2699 // GFX11
: [0x05,0x00,0x4f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2701 v_med3_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2702 // GFX11
: [0x05,0x00,0x4f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2704 v_med3_f16_e64_dpp v5
, v1
, v2
, v3 row_mirror
2705 // GFX11
: [0x05,0x00,0x4f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2707 v_med3_f16_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2708 // GFX11
: [0x05,0x00,0x4f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2710 v_med3_f16_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2711 // GFX11
: [0x05,0x00,0x4f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2713 v_med3_f16_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2714 // GFX11
: [0x05,0x00,0x4f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2716 v_med3_f16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2717 // GFX11
: [0x05,0x00,0x4f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2719 v_med3_f16_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
2720 // GFX11
: [0x05,0x01,0x4f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
2722 v_med3_f16_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
2723 // GFX11
: [0x05,0x02,0x4f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
2725 v_med3_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
2726 // GFX11
: [0x05,0x04,0x4f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
2728 v_med3_f16_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2729 // GFX11
: [0x05,0x03,0x4f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
2731 v_med3_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1| row_share
:15 row_mask
:0x0 bank_mask
:0x1
2732 // GFX11
: [0x05,0x05,0x4f,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
2734 v_med3_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2735 // GFX11
: [0x05,0x06,0x4f,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13]
2737 v_med3_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2738 // GFX11
: [0xff,0x87,0x4f,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30]
2740 v_med3_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2741 // GFX11
: [0x05,0x00,0x1f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2743 v_med3_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2744 // GFX11
: [0x05,0x00,0x1f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2746 v_med3_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
2747 // GFX11
: [0x05,0x00,0x1f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2749 v_med3_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2750 // GFX11
: [0x05,0x00,0x1f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2752 v_med3_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2753 // GFX11
: [0x05,0x00,0x1f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2755 v_med3_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2756 // GFX11
: [0x05,0x00,0x1f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2758 v_med3_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2759 // GFX11
: [0x05,0x00,0x1f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2761 v_med3_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
2762 // GFX11
: [0x05,0x01,0x1f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
2764 v_med3_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
2765 // GFX11
: [0x05,0x02,0x1f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
2767 v_med3_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
2768 // GFX11
: [0x05,0x04,0x1f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
2770 v_med3_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2771 // GFX11
: [0x05,0x03,0x1f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
2773 v_med3_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2774 // GFX11
: [0x05,0x05,0x1f,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
2776 v_med3_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2777 // GFX11
: [0x05,0x06,0x1f,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
2779 v_med3_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2780 // GFX11
: [0xff,0x87,0x1f,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
2782 v_med3_i16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2783 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2785 v_med3_i16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2786 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2788 v_med3_i16_e64_dpp v5
, v1
, v2
, v3 row_mirror
2789 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2791 v_med3_i16_e64_dpp v5
, v1
, v2
, v3 row_half_mirror
2792 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
2794 v_med3_i16_e64_dpp v5
, v1
, v2
, v255 row_shl
:1
2795 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
2797 v_med3_i16_e64_dpp v5
, v1
, v2
, s105 row_shl
:15
2798 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
2800 v_med3_i16_e64_dpp v5
, v1
, v2
, vcc_hi row_shr
:1
2801 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
2803 v_med3_i16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:15
2804 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
2806 v_med3_i16_e64_dpp v5
, v1
, v2
, ttmp15 row_ror
:1
2807 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
2809 v_med3_i16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:15
2810 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
2812 v_med3_i16_e64_dpp v5
, v1
, v2
, exec_lo row_share
:0 row_mask
:0xf bank_mask
:0xf
2813 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
2815 v_med3_i16_e64_dpp v5
, v1
, v2
, null row_share
:15 row_mask
:0x0 bank_mask
:0x1
2816 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
2818 v_med3_i16_e64_dpp v5
, v1
, v2
, -1 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2819 // GFX11
: [0x05,0x00,0x50,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
2821 v_med3_i16_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2822 // GFX11
: [0xff,0x00,0x50,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2824 v_med3_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2825 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2827 v_med3_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2828 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2830 v_med3_i32_e64_dpp v5
, v1
, v2
, v3 row_mirror
2831 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2833 v_med3_i32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2834 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2836 v_med3_i32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2837 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2839 v_med3_i32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2840 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2842 v_med3_i32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2843 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2845 v_med3_i32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
2846 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
2848 v_med3_i32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
2849 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
2851 v_med3_i32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
2852 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
2854 v_med3_i32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2855 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
2857 v_med3_i32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2858 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
2860 v_med3_i32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2861 // GFX11
: [0x05,0x00,0x20,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
2863 v_med3_i32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2864 // GFX11
: [0xff,0x00,0x20,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2866 v_med3_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2867 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2869 v_med3_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2870 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2872 v_med3_u16_e64_dpp v5
, v1
, v2
, v3 row_mirror
2873 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2875 v_med3_u16_e64_dpp v5
, v1
, v2
, v3 row_half_mirror
2876 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
2878 v_med3_u16_e64_dpp v5
, v1
, v2
, v255 row_shl
:1
2879 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
2881 v_med3_u16_e64_dpp v5
, v1
, v2
, s105 row_shl
:15
2882 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
2884 v_med3_u16_e64_dpp v5
, v1
, v2
, vcc_hi row_shr
:1
2885 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
2887 v_med3_u16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:15
2888 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
2890 v_med3_u16_e64_dpp v5
, v1
, v2
, ttmp15 row_ror
:1
2891 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
2893 v_med3_u16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:15
2894 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
2896 v_med3_u16_e64_dpp v5
, v1
, v2
, exec_lo row_share
:0 row_mask
:0xf bank_mask
:0xf
2897 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
2899 v_med3_u16_e64_dpp v5
, v1
, v2
, null row_share
:15 row_mask
:0x0 bank_mask
:0x1
2900 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
2902 v_med3_u16_e64_dpp v5
, v1
, v2
, -1 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2903 // GFX11
: [0x05,0x00,0x51,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
2905 v_med3_u16_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2906 // GFX11
: [0xff,0x00,0x51,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2908 v_med3_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2909 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2911 v_med3_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2912 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2914 v_med3_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
2915 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2917 v_med3_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2918 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2920 v_med3_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2921 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2923 v_med3_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2924 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2926 v_med3_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2927 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2929 v_med3_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
2930 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
2932 v_med3_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
2933 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
2935 v_med3_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
2936 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
2938 v_med3_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2939 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
2941 v_med3_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
2942 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
2944 v_med3_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2945 // GFX11
: [0x05,0x00,0x21,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
2947 v_med3_u32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2948 // GFX11
: [0xff,0x00,0x21,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
2950 v_min3_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2951 // GFX11
: [0x05,0x00,0x49,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2953 v_min3_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2954 // GFX11
: [0x05,0x00,0x49,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2956 v_min3_f16_e64_dpp v5
, v1
, v2
, v3 row_mirror
2957 // GFX11
: [0x05,0x00,0x49,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
2959 v_min3_f16_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
2960 // GFX11
: [0x05,0x00,0x49,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
2962 v_min3_f16_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
2963 // GFX11
: [0x05,0x00,0x49,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
2965 v_min3_f16_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
2966 // GFX11
: [0x05,0x00,0x49,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
2968 v_min3_f16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
2969 // GFX11
: [0x05,0x00,0x49,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
2971 v_min3_f16_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
2972 // GFX11
: [0x05,0x01,0x49,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
2974 v_min3_f16_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
2975 // GFX11
: [0x05,0x02,0x49,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
2977 v_min3_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
2978 // GFX11
: [0x05,0x04,0x49,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
2980 v_min3_f16_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
2981 // GFX11
: [0x05,0x03,0x49,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
2983 v_min3_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1| row_share
:15 row_mask
:0x0 bank_mask
:0x1
2984 // GFX11
: [0x05,0x05,0x49,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
2986 v_min3_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
2987 // GFX11
: [0x05,0x06,0x49,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x09,0x13]
2989 v_min3_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
2990 // GFX11
: [0xff,0x87,0x49,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x05,0x30]
2992 v_min3_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
2993 // GFX11
: [0x05,0x00,0x19,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
2995 v_min3_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
2996 // GFX11
: [0x05,0x00,0x19,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
2998 v_min3_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
2999 // GFX11
: [0x05,0x00,0x19,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3001 v_min3_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3002 // GFX11
: [0x05,0x00,0x19,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3004 v_min3_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3005 // GFX11
: [0x05,0x00,0x19,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3007 v_min3_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3008 // GFX11
: [0x05,0x00,0x19,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3010 v_min3_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3011 // GFX11
: [0x05,0x00,0x19,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3013 v_min3_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
3014 // GFX11
: [0x05,0x01,0x19,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
3016 v_min3_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
3017 // GFX11
: [0x05,0x02,0x19,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
3019 v_min3_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
3020 // GFX11
: [0x05,0x04,0x19,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
3022 v_min3_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3023 // GFX11
: [0x05,0x03,0x19,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
3025 v_min3_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3026 // GFX11
: [0x05,0x05,0x19,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
3028 v_min3_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3029 // GFX11
: [0x05,0x06,0x19,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
3031 v_min3_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3032 // GFX11
: [0xff,0x87,0x19,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
3034 v_min3_i16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3035 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3037 v_min3_i16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3038 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3040 v_min3_i16_e64_dpp v5
, v1
, v2
, v3 row_mirror
3041 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3043 v_min3_i16_e64_dpp v5
, v1
, v2
, v3 row_half_mirror
3044 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
3046 v_min3_i16_e64_dpp v5
, v1
, v2
, v255 row_shl
:1
3047 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
3049 v_min3_i16_e64_dpp v5
, v1
, v2
, s105 row_shl
:15
3050 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
3052 v_min3_i16_e64_dpp v5
, v1
, v2
, vcc_hi row_shr
:1
3053 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
3055 v_min3_i16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:15
3056 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
3058 v_min3_i16_e64_dpp v5
, v1
, v2
, ttmp15 row_ror
:1
3059 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
3061 v_min3_i16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:15
3062 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
3064 v_min3_i16_e64_dpp v5
, v1
, v2
, exec_lo row_share
:0 row_mask
:0xf bank_mask
:0xf
3065 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
3067 v_min3_i16_e64_dpp v5
, v1
, v2
, null row_share
:15 row_mask
:0x0 bank_mask
:0x1
3068 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
3070 v_min3_i16_e64_dpp v5
, v1
, v2
, -1 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3071 // GFX11
: [0x05,0x00,0x4a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
3073 v_min3_i16_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3074 // GFX11
: [0xff,0x00,0x4a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3076 v_min3_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3077 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3079 v_min3_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3080 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3082 v_min3_i32_e64_dpp v5
, v1
, v2
, v3 row_mirror
3083 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3085 v_min3_i32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3086 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3088 v_min3_i32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3089 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3091 v_min3_i32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3092 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3094 v_min3_i32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3095 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3097 v_min3_i32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3098 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3100 v_min3_i32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3101 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3103 v_min3_i32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3104 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3106 v_min3_i32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3107 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3109 v_min3_i32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3110 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3112 v_min3_i32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3113 // GFX11
: [0x05,0x00,0x1a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3115 v_min3_i32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3116 // GFX11
: [0xff,0x00,0x1a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3118 v_min3_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3119 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3121 v_min3_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3122 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3124 v_min3_u16_e64_dpp v5
, v1
, v2
, v3 row_mirror
3125 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3127 v_min3_u16_e64_dpp v5
, v1
, v2
, v3 row_half_mirror
3128 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x41,0x01,0xff]
3130 v_min3_u16_e64_dpp v5
, v1
, v2
, v255 row_shl
:1
3131 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x01,0x01,0xff]
3133 v_min3_u16_e64_dpp v5
, v1
, v2
, s105 row_shl
:15
3134 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x0f,0x01,0xff]
3136 v_min3_u16_e64_dpp v5
, v1
, v2
, vcc_hi row_shr
:1
3137 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x11,0x01,0xff]
3139 v_min3_u16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:15
3140 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x1f,0x01,0xff]
3142 v_min3_u16_e64_dpp v5
, v1
, v2
, ttmp15 row_ror
:1
3143 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x21,0x01,0xff]
3145 v_min3_u16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:15
3146 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
3148 v_min3_u16_e64_dpp v5
, v1
, v2
, exec_lo row_share
:0 row_mask
:0xf bank_mask
:0xf
3149 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
3151 v_min3_u16_e64_dpp v5
, v1
, v2
, null row_share
:15 row_mask
:0x0 bank_mask
:0x1
3152 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
3154 v_min3_u16_e64_dpp v5
, v1
, v2
, -1 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3155 // GFX11
: [0x05,0x00,0x4b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x09,0x13]
3157 v_min3_u16_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3158 // GFX11
: [0xff,0x00,0x4b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3160 v_min3_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3161 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3163 v_min3_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3164 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3166 v_min3_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
3167 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3169 v_min3_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3170 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3172 v_min3_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3173 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3175 v_min3_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3176 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3178 v_min3_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3179 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3181 v_min3_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3182 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3184 v_min3_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3185 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3187 v_min3_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3188 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3190 v_min3_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3191 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3193 v_min3_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3194 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3196 v_min3_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3197 // GFX11
: [0x05,0x00,0x1b,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3199 v_min3_u32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3200 // GFX11
: [0xff,0x00,0x1b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3202 v_min_i16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
3203 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
3205 v_min_i16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
3206 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
3208 v_min_i16_e64_dpp v5
, v1
, v2 row_mirror
3209 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
3211 v_min_i16_e64_dpp v5
, v1
, v2 row_half_mirror
3212 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
3214 v_min_i16_e64_dpp v5
, v1
, v2 row_shl
:1
3215 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
3217 v_min_i16_e64_dpp v5
, v1
, v2 row_shl
:15
3218 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
3220 v_min_i16_e64_dpp v5
, v1
, v2 row_shr
:1
3221 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
3223 v_min_i16_e64_dpp v5
, v1
, v2 row_shr
:15
3224 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
3226 v_min_i16_e64_dpp v5
, v1
, v2 row_ror
:1
3227 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
3229 v_min_i16_e64_dpp v5
, v1
, v2 row_ror
:15
3230 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
3232 v_min_i16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
3233 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
3235 v_min_i16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3236 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
3238 v_min_i16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3239 // GFX11
: [0x05,0x00,0x0c,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
3241 v_min_i16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3242 // GFX11
: [0xff,0x00,0x0c,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
3244 v_min_u16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
3245 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
3247 v_min_u16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
3248 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
3250 v_min_u16_e64_dpp v5
, v1
, v2 row_mirror
3251 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
3253 v_min_u16_e64_dpp v5
, v1
, v2 row_half_mirror
3254 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
3256 v_min_u16_e64_dpp v5
, v1
, v2 row_shl
:1
3257 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
3259 v_min_u16_e64_dpp v5
, v1
, v2 row_shl
:15
3260 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
3262 v_min_u16_e64_dpp v5
, v1
, v2 row_shr
:1
3263 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
3265 v_min_u16_e64_dpp v5
, v1
, v2 row_shr
:15
3266 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
3268 v_min_u16_e64_dpp v5
, v1
, v2 row_ror
:1
3269 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
3271 v_min_u16_e64_dpp v5
, v1
, v2 row_ror
:15
3272 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
3274 v_min_u16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
3275 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
3277 v_min_u16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3278 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
3280 v_min_u16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3281 // GFX11
: [0x05,0x00,0x0b,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
3283 v_min_u16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3284 // GFX11
: [0xff,0x00,0x0b,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
3286 v_minmax_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3287 // GFX11
: [0x05,0x00,0x61,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3289 v_minmax_f16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3290 // GFX11
: [0x05,0x00,0x61,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3292 v_minmax_f16_e64_dpp v5
, v1
, v2
, v3 row_mirror
3293 // GFX11
: [0x05,0x00,0x61,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3295 v_minmax_f16_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3296 // GFX11
: [0x05,0x00,0x61,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3298 v_minmax_f16_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3299 // GFX11
: [0x05,0x00,0x61,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3301 v_minmax_f16_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3302 // GFX11
: [0x05,0x00,0x61,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3304 v_minmax_f16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3305 // GFX11
: [0x05,0x00,0x61,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3307 v_minmax_f16_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
3308 // GFX11
: [0x05,0x01,0x61,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
3310 v_minmax_f16_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
3311 // GFX11
: [0x05,0x02,0x61,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
3313 v_minmax_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
3314 // GFX11
: [0x05,0x04,0x61,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
3316 v_minmax_f16_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3317 // GFX11
: [0x05,0x03,0x61,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
3319 v_minmax_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3320 // GFX11
: [0x05,0x05,0x61,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
3322 v_minmax_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3323 // GFX11
: [0x05,0x06,0x61,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
3325 v_minmax_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3326 // GFX11
: [0xff,0x87,0x61,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
3328 v_minmax_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3329 // GFX11
: [0x05,0x00,0x5f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3331 v_minmax_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3332 // GFX11
: [0x05,0x00,0x5f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3334 v_minmax_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
3335 // GFX11
: [0x05,0x00,0x5f,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3337 v_minmax_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3338 // GFX11
: [0x05,0x00,0x5f,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3340 v_minmax_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3341 // GFX11
: [0x05,0x00,0x5f,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3343 v_minmax_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3344 // GFX11
: [0x05,0x00,0x5f,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3346 v_minmax_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3347 // GFX11
: [0x05,0x00,0x5f,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3349 v_minmax_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
3350 // GFX11
: [0x05,0x01,0x5f,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
3352 v_minmax_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
3353 // GFX11
: [0x05,0x02,0x5f,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
3355 v_minmax_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
3356 // GFX11
: [0x05,0x04,0x5f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
3358 v_minmax_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3359 // GFX11
: [0x05,0x03,0x5f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
3361 v_minmax_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3362 // GFX11
: [0x05,0x05,0x5f,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
3364 v_minmax_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3365 // GFX11
: [0x05,0x06,0x5f,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
3367 v_minmax_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3368 // GFX11
: [0xff,0x87,0x5f,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
3370 v_minmax_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3371 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3373 v_minmax_i32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3374 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3376 v_minmax_i32_e64_dpp v5
, v1
, v2
, v3 row_mirror
3377 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3379 v_minmax_i32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3380 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3382 v_minmax_i32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3383 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3385 v_minmax_i32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3386 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3388 v_minmax_i32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3389 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3391 v_minmax_i32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3392 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3394 v_minmax_i32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3395 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3397 v_minmax_i32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3398 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3400 v_minmax_i32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3401 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3403 v_minmax_i32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3404 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3406 v_minmax_i32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3407 // GFX11
: [0x05,0x00,0x65,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3409 v_minmax_i32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3410 // GFX11
: [0xff,0x00,0x65,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3412 v_minmax_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3413 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3415 v_minmax_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3416 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3418 v_minmax_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
3419 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3421 v_minmax_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3422 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3424 v_minmax_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3425 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3427 v_minmax_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3428 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3430 v_minmax_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3431 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3433 v_minmax_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3434 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3436 v_minmax_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3437 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3439 v_minmax_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3440 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3442 v_minmax_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3443 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3445 v_minmax_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3446 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3448 v_minmax_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3449 // GFX11
: [0x05,0x00,0x63,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3451 v_minmax_u32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3452 // GFX11
: [0xff,0x00,0x63,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3454 v_msad_u8_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3455 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3457 v_msad_u8_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3458 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3460 v_msad_u8_e64_dpp v5
, v1
, v2
, v3 row_mirror
3461 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3463 v_msad_u8_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3464 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3466 v_msad_u8_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3467 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3469 v_msad_u8_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3470 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3472 v_msad_u8_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3473 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3475 v_msad_u8_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3476 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3478 v_msad_u8_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3479 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3481 v_msad_u8_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3482 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3484 v_msad_u8_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3485 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3487 v_msad_u8_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3488 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3490 v_msad_u8_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3491 // GFX11
: [0x05,0x00,0x39,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3493 v_msad_u8_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3494 // GFX11
: [0xff,0x80,0x39,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3496 v_mul_lo_u16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
3497 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
3499 v_mul_lo_u16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
3500 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
3502 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_mirror
3503 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
3505 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_half_mirror
3506 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
3508 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_shl
:1
3509 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
3511 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_shl
:15
3512 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
3514 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_shr
:1
3515 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
3517 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_shr
:15
3518 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
3520 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_ror
:1
3521 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
3523 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_ror
:15
3524 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
3526 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
3527 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
3529 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3530 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
3532 v_mul_lo_u16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3533 // GFX11
: [0x05,0x00,0x05,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
3535 v_mul_lo_u16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3536 // GFX11
: [0xff,0x00,0x05,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
3538 v_mullit_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3539 // GFX11
: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3541 v_mullit_f32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3542 // GFX11
: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3544 v_mullit_f32_e64_dpp v5
, v1
, v2
, v3 row_mirror
3545 // GFX11
: [0x05,0x00,0x18,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3547 v_mullit_f32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3548 // GFX11
: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3550 v_mullit_f32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3551 // GFX11
: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3553 v_mullit_f32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3554 // GFX11
: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3556 v_mullit_f32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3557 // GFX11
: [0x05,0x00,0x18,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3559 v_mullit_f32_e64_dpp v5
, |v1|
, v2
, -ttmp15 row_shr
:15
3560 // GFX11
: [0x05,0x01,0x18,0xd6,0xfa,0x04,0xee,0x81,0x01,0x1f,0x01,0xff]
3562 v_mullit_f32_e64_dpp v5
, v1
, -|v2|
, exec_hi row_ror
:1
3563 // GFX11
: [0x05,0x02,0x18,0xd6,0xfa,0x04,0xfe,0x41,0x01,0x21,0x01,0xff]
3565 v_mullit_f32_e64_dpp v5
, -v1
, v2
, |exec_lo| row_ror
:15
3566 // GFX11
: [0x05,0x04,0x18,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
3568 v_mullit_f32_e64_dpp v5
, -|v1|
, -|v2|
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3569 // GFX11
: [0x05,0x03,0x18,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
3571 v_mullit_f32_e64_dpp v5
, -|v1|
, v2
, -|
-1|
mul:2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3572 // GFX11
: [0x05,0x05,0x18,0xd6,0xfa,0x04,0x06,0xab,0x01,0x5f,0x01,0x01]
3574 v_mullit_f32_e64_dpp v5
, v1
, -|v2|
, -|
0.5|
mul:4 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3575 // GFX11
: [0x05,0x06,0x18,0xd6,0xfa,0x04,0xc2,0xd3,0x01,0x60,0x09,0x13]
3577 v_mullit_f32_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| clamp
div:2 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3578 // GFX11
: [0xff,0x87,0x18,0xd6,0xfa,0xfe,0xf7,0xfb,0xff,0x6f,0x05,0x30]
3580 v_or3_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3581 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3583 v_or3_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3584 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3586 v_or3_b32_e64_dpp v5
, v1
, v2
, v3 row_mirror
3587 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3589 v_or3_b32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3590 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3592 v_or3_b32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3593 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3595 v_or3_b32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3596 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3598 v_or3_b32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3599 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3601 v_or3_b32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3602 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3604 v_or3_b32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3605 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3607 v_or3_b32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3608 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3610 v_or3_b32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3611 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3613 v_or3_b32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3614 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3616 v_or3_b32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3617 // GFX11
: [0x05,0x00,0x58,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3619 v_or3_b32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3620 // GFX11
: [0xff,0x00,0x58,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3622 v_or_b16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
3623 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
3625 v_or_b16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
3626 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
3628 v_or_b16_e64_dpp v5
, v1
, v2 row_mirror
3629 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
3631 v_or_b16_e64_dpp v5
, v1
, v2 row_half_mirror
3632 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
3634 v_or_b16_e64_dpp v5
, v1
, v2 row_shl
:1
3635 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
3637 v_or_b16_e64_dpp v5
, v1
, v2 row_shl
:15
3638 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
3640 v_or_b16_e64_dpp v5
, v1
, v2 row_shr
:1
3641 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
3643 v_or_b16_e64_dpp v5
, v1
, v2 row_shr
:15
3644 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
3646 v_or_b16_e64_dpp v5
, v1
, v2 row_ror
:1
3647 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
3649 v_or_b16_e64_dpp v5
, v1
, v2 row_ror
:15
3650 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
3652 v_or_b16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
3653 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
3655 v_or_b16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3656 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
3658 v_or_b16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3659 // GFX11
: [0x05,0x00,0x63,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
3661 v_or_b16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3662 // GFX11
: [0xff,0x00,0x63,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
3664 v_pack_b32_f16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
3665 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
3667 v_pack_b32_f16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
3668 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
3670 v_pack_b32_f16_e64_dpp v5
, v1
, v2 row_mirror
3671 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
3673 v_pack_b32_f16_e64_dpp v5
, v1
, v2 row_half_mirror
3674 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
3676 v_pack_b32_f16_e64_dpp v5
, v1
, v2 row_shl
:1
3677 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
3679 v_pack_b32_f16_e64_dpp v5
, v1
, v2 row_shl
:15
3680 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
3682 v_pack_b32_f16_e64_dpp v5
, v1
, v2 row_shr
:1
3683 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
3685 v_pack_b32_f16_e64_dpp v5
, v1
, v2 row_shr
:15
3686 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
3688 v_pack_b32_f16_e64_dpp v5
, v1
, v2 row_ror
:1
3689 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
3691 v_pack_b32_f16_e64_dpp v5
, v1
, v2 row_ror
:15
3692 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
3694 v_pack_b32_f16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
3695 // GFX11
: [0x05,0x00,0x11,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
3697 v_pack_b32_f16_e64_dpp v5
, |v1|
, -v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3698 // GFX11
: [0x05,0x01,0x11,0xd7,0xfa,0x04,0x02,0x40,0x01,0x5f,0x01,0x01]
3700 v_pack_b32_f16_e64_dpp v5
, -v1
, |v2| row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3701 // GFX11
: [0x05,0x02,0x11,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x09,0x13]
3703 v_pack_b32_f16_e64_dpp v255
, -|v255|
, -|v255| row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3704 // GFX11
: [0xff,0x03,0x11,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x05,0x30]
3706 v_perm_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3707 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3709 v_perm_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3710 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3712 v_perm_b32_e64_dpp v5
, v1
, v2
, v3 row_mirror
3713 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3715 v_perm_b32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3716 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3718 v_perm_b32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3719 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3721 v_perm_b32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3722 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3724 v_perm_b32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3725 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3727 v_perm_b32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3728 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3730 v_perm_b32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3731 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3733 v_perm_b32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3734 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3736 v_perm_b32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3737 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3739 v_perm_b32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3740 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3742 v_perm_b32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3743 // GFX11
: [0x05,0x00,0x44,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3745 v_perm_b32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3746 // GFX11
: [0xff,0x00,0x44,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3748 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3749 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3751 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3752 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3754 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, v3 row_mirror
3755 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3757 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3758 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3760 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3761 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3763 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3764 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3766 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3767 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3769 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3770 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3772 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3773 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3775 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3776 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3778 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3779 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3781 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3782 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3784 v_sad_hi_u8_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3785 // GFX11
: [0x05,0x00,0x23,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3787 v_sad_hi_u8_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3788 // GFX11
: [0xff,0x80,0x23,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3790 v_sad_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3791 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3793 v_sad_u16_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3794 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3796 v_sad_u16_e64_dpp v5
, v1
, v2
, v3 row_mirror
3797 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3799 v_sad_u16_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3800 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3802 v_sad_u16_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3803 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3805 v_sad_u16_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3806 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3808 v_sad_u16_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3809 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3811 v_sad_u16_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3812 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3814 v_sad_u16_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3815 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3817 v_sad_u16_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3818 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3820 v_sad_u16_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3821 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3823 v_sad_u16_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3824 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3826 v_sad_u16_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3827 // GFX11
: [0x05,0x00,0x24,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3829 v_sad_u16_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3830 // GFX11
: [0xff,0x80,0x24,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3832 v_sad_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3833 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3835 v_sad_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3836 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3838 v_sad_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
3839 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3841 v_sad_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3842 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3844 v_sad_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3845 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3847 v_sad_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3848 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3850 v_sad_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3851 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3853 v_sad_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3854 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3856 v_sad_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3857 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3859 v_sad_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3860 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3862 v_sad_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3863 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3865 v_sad_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3866 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3868 v_sad_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3869 // GFX11
: [0x05,0x00,0x25,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3871 v_sad_u32_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3872 // GFX11
: [0xff,0x80,0x25,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3874 v_sad_u8_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
3875 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
3877 v_sad_u8_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
3878 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
3880 v_sad_u8_e64_dpp v5
, v1
, v2
, v3 row_mirror
3881 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
3883 v_sad_u8_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
3884 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
3886 v_sad_u8_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
3887 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
3889 v_sad_u8_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
3890 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
3892 v_sad_u8_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
3893 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
3895 v_sad_u8_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
3896 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
3898 v_sad_u8_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
3899 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
3901 v_sad_u8_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
3902 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
3904 v_sad_u8_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
3905 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
3907 v_sad_u8_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3908 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
3910 v_sad_u8_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3911 // GFX11
: [0x05,0x00,0x22,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
3913 v_sad_u8_e64_dpp v255
, v255
, v255
, src_scc clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
3914 // GFX11
: [0xff,0x80,0x22,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
3916 v_sub_co_u32_e64_dpp v5
, s6
, v1
, v2 quad_perm
:[3,2,1,0]
3917 // W32
: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
3918 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3920 v_sub_co_u32_e64_dpp v5
, s6
, v1
, v2 quad_perm
:[0,1,2,3]
3921 // W32
: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
3922 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3924 v_sub_co_u32_e64_dpp v5
, s6
, v1
, v2 row_mirror
3925 // W32
: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
3926 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3928 v_sub_co_u32_e64_dpp v5
, s6
, v1
, v2 row_half_mirror
3929 // W32
: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
3930 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3932 v_sub_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shl
:1
3933 // W32
: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
3934 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3936 v_sub_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shl
:15
3937 // W32
: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
3938 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3940 v_sub_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shr
:1
3941 // W32
: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
3942 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3944 v_sub_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shr
:15
3945 // W32
: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
3946 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3948 v_sub_co_u32_e64_dpp v5
, s6
, v1
, v2 row_ror
:1
3949 // W32
: [0x05,0x06,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
3950 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3952 v_sub_co_u32_e64_dpp v5
, s105
, v1
, v2 row_ror
:15
3953 // W32
: [0x05,0x69,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
3954 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3956 v_sub_co_u32_e64_dpp v5
, vcc_lo
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
3957 // W32
: [0x05,0x6a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
3958 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3960 v_sub_co_u32_e64_dpp v5
, vcc_hi
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
3961 // W32
: [0x05,0x6b,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
3962 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3964 v_sub_co_u32_e64_dpp v5
, ttmp15
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
3965 // W32
: [0x05,0x7b,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
3966 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3968 v_sub_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 quad_perm
:[3,2,1,0]
3969 // W64
: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
3970 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3972 v_sub_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 quad_perm
:[0,1,2,3]
3973 // W64
: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
3974 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3976 v_sub_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_mirror
3977 // W64
: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
3978 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3980 v_sub_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_half_mirror
3981 // W64
: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
3982 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3984 v_sub_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shl
:1
3985 // W64
: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
3986 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3988 v_sub_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shl
:15
3989 // W64
: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
3990 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3992 v_sub_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shr
:1
3993 // W64
: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
3994 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
3996 v_sub_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shr
:15
3997 // W64
: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
3998 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4000 v_sub_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_ror
:1
4001 // W64
: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
4002 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4004 v_sub_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_ror
:15
4005 // W64
: [0x05,0x0c,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
4006 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4008 v_sub_co_u32_e64_dpp v5
, s
[104:105], v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
4009 // W64
: [0x05,0x68,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4010 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4012 v_sub_co_u32_e64_dpp v5
, vcc
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
4013 // W64
: [0x05,0x6a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4014 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4016 v_sub_co_u32_e64_dpp v5
, ttmp
[14:15], v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
4017 // W64
: [0x05,0x7a,0x01,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
4018 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4020 v_sub_co_u32_e64_dpp v255
, null
, v255
, v255 clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
4021 // GFX11
: [0xff,0xfc,0x01,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
4023 v_sub_nc_i16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
4024 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
4026 v_sub_nc_i16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
4027 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
4029 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_mirror
4030 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
4032 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_half_mirror
4033 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
4035 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_shl
:1
4036 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
4038 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_shl
:15
4039 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
4041 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_shr
:1
4042 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
4044 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_shr
:15
4045 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
4047 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_ror
:1
4048 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
4050 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_ror
:15
4051 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
4053 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
4054 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4056 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
4057 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4059 v_sub_nc_i16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
4060 // GFX11
: [0x05,0x00,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
4062 v_sub_nc_i16_e64_dpp v255
, v255
, v255 clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
4063 // GFX11
: [0xff,0x80,0x0e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
4065 v_sub_nc_i32_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
4066 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
4068 v_sub_nc_i32_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
4069 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
4071 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_mirror
4072 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
4074 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_half_mirror
4075 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
4077 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_shl
:1
4078 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
4080 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_shl
:15
4081 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
4083 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_shr
:1
4084 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
4086 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_shr
:15
4087 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
4089 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_ror
:1
4090 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
4092 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_ror
:15
4093 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
4095 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
4096 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4098 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
4099 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4101 v_sub_nc_i32_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
4102 // GFX11
: [0x05,0x00,0x25,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
4104 v_sub_nc_i32_e64_dpp v255
, v255
, v255 clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
4105 // GFX11
: [0xff,0x80,0x25,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
4107 v_sub_nc_u16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
4108 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
4110 v_sub_nc_u16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
4111 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
4113 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_mirror
4114 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
4116 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_half_mirror
4117 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
4119 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_shl
:1
4120 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
4122 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_shl
:15
4123 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
4125 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_shr
:1
4126 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
4128 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_shr
:15
4129 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
4131 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_ror
:1
4132 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
4134 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_ror
:15
4135 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
4137 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
4138 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4140 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
4141 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4143 v_sub_nc_u16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
4144 // GFX11
: [0x05,0x00,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
4146 v_sub_nc_u16_e64_dpp v255
, v255
, v255 clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
4147 // GFX11
: [0xff,0x80,0x04,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
4149 v_subrev_co_u32_e64_dpp v5
, s6
, v1
, v2 quad_perm
:[3,2,1,0]
4150 // W32
: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
4151 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4153 v_subrev_co_u32_e64_dpp v5
, s6
, v1
, v2 quad_perm
:[0,1,2,3]
4154 // W32
: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
4155 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4157 v_subrev_co_u32_e64_dpp v5
, s6
, v1
, v2 row_mirror
4158 // W32
: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
4159 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4161 v_subrev_co_u32_e64_dpp v5
, s6
, v1
, v2 row_half_mirror
4162 // W32
: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
4163 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4165 v_subrev_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shl
:1
4166 // W32
: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
4167 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4169 v_subrev_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shl
:15
4170 // W32
: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
4171 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4173 v_subrev_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shr
:1
4174 // W32
: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
4175 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4177 v_subrev_co_u32_e64_dpp v5
, s6
, v1
, v2 row_shr
:15
4178 // W32
: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
4179 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4181 v_subrev_co_u32_e64_dpp v5
, s6
, v1
, v2 row_ror
:1
4182 // W32
: [0x05,0x06,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
4183 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4185 v_subrev_co_u32_e64_dpp v5
, s105
, v1
, v2 row_ror
:15
4186 // W32
: [0x05,0x69,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
4187 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4189 v_subrev_co_u32_e64_dpp v5
, vcc_lo
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
4190 // W32
: [0x05,0x6a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4191 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4193 v_subrev_co_u32_e64_dpp v5
, vcc_hi
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
4194 // W32
: [0x05,0x6b,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4195 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4197 v_subrev_co_u32_e64_dpp v5
, ttmp15
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
4198 // W32
: [0x05,0x7b,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
4199 // W64-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4201 v_subrev_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 quad_perm
:[3,2,1,0]
4202 // W64
: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
4203 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4205 v_subrev_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 quad_perm
:[0,1,2,3]
4206 // W64
: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
4207 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4209 v_subrev_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_mirror
4210 // W64
: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
4211 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4213 v_subrev_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_half_mirror
4214 // W64
: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
4215 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4217 v_subrev_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shl
:1
4218 // W64
: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
4219 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4221 v_subrev_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shl
:15
4222 // W64
: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
4223 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4225 v_subrev_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shr
:1
4226 // W64
: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
4227 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4229 v_subrev_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_shr
:15
4230 // W64
: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
4231 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4233 v_subrev_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_ror
:1
4234 // W64
: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
4235 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4237 v_subrev_co_u32_e64_dpp v5
, s
[12:13], v1
, v2 row_ror
:15
4238 // W64
: [0x05,0x0c,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
4239 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4241 v_subrev_co_u32_e64_dpp v5
, s
[104:105], v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
4242 // W64
: [0x05,0x68,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4243 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4245 v_subrev_co_u32_e64_dpp v5
, vcc
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
4246 // W64
: [0x05,0x6a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4247 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4249 v_subrev_co_u32_e64_dpp v5
, ttmp
[14:15], v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
4250 // W64
: [0x05,0x7a,0x02,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
4251 // W32-ERR
: :[[@LINE-
2]]:{{[0-9]+}}: error
: invalid operand for instruction
4253 v_subrev_co_u32_e64_dpp v255
, null
, v255
, v255 clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
4254 // GFX11
: [0xff,0xfc,0x02,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
4256 v_xad_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
4257 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
4259 v_xad_u32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
4260 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
4262 v_xad_u32_e64_dpp v5
, v1
, v2
, v3 row_mirror
4263 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
4265 v_xad_u32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
4266 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
4268 v_xad_u32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
4269 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
4271 v_xad_u32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
4272 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
4274 v_xad_u32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
4275 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
4277 v_xad_u32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
4278 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
4280 v_xad_u32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
4281 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
4283 v_xad_u32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
4284 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
4286 v_xad_u32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
4287 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
4289 v_xad_u32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
4290 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
4292 v_xad_u32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
4293 // GFX11
: [0x05,0x00,0x45,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
4295 v_xad_u32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
4296 // GFX11
: [0xff,0x00,0x45,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
4298 v_xor3_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[3,2,1,0]
4299 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x1b,0x00,0xff]
4301 v_xor3_b32_e64_dpp v5
, v1
, v2
, v3 quad_perm
:[0,1,2,3]
4302 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x00,0xff]
4304 v_xor3_b32_e64_dpp v5
, v1
, v2
, v3 row_mirror
4305 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x0e,0x04,0x01,0x40,0x01,0xff]
4307 v_xor3_b32_e64_dpp v5
, v1
, v2
, v255 row_half_mirror
4308 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfe,0x07,0x01,0x41,0x01,0xff]
4310 v_xor3_b32_e64_dpp v5
, v1
, v2
, s105 row_shl
:1
4311 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xa6,0x01,0x01,0x01,0x01,0xff]
4313 v_xor3_b32_e64_dpp v5
, v1
, v2
, vcc_hi row_shl
:15
4314 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xae,0x01,0x01,0x0f,0x01,0xff]
4316 v_xor3_b32_e64_dpp v5
, v1
, v2
, vcc_lo row_shr
:1
4317 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xaa,0x01,0x01,0x11,0x01,0xff]
4319 v_xor3_b32_e64_dpp v5
, v1
, v2
, ttmp15 row_shr
:15
4320 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xee,0x01,0x01,0x1f,0x01,0xff]
4322 v_xor3_b32_e64_dpp v5
, v1
, v2
, exec_hi row_ror
:1
4323 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x21,0x01,0xff]
4325 v_xor3_b32_e64_dpp v5
, v1
, v2
, exec_lo row_ror
:15
4326 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x2f,0x01,0xff]
4328 v_xor3_b32_e64_dpp v5
, v1
, v2
, null row_share
:0 row_mask
:0xf bank_mask
:0xf
4329 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x50,0x01,0xff]
4331 v_xor3_b32_e64_dpp v5
, v1
, v2
, -1 row_share
:15 row_mask
:0x0 bank_mask
:0x1
4332 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0x06,0x03,0x01,0x5f,0x01,0x01]
4334 v_xor3_b32_e64_dpp v5
, v1
, v2
, 0.5 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
4335 // GFX11
: [0x05,0x00,0x40,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x09,0x13]
4337 v_xor3_b32_e64_dpp v255
, v255
, v255
, src_scc row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
4338 // GFX11
: [0xff,0x00,0x40,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x05,0x30]
4340 v_xor_b16_e64_dpp v5
, v1
, v2 quad_perm
:[3,2,1,0]
4341 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff]
4343 v_xor_b16_e64_dpp v5
, v1
, v2 quad_perm
:[0,1,2,3]
4344 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0xe4,0x00,0xff]
4346 v_xor_b16_e64_dpp v5
, v1
, v2 row_mirror
4347 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x40,0x01,0xff]
4349 v_xor_b16_e64_dpp v5
, v1
, v2 row_half_mirror
4350 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x41,0x01,0xff]
4352 v_xor_b16_e64_dpp v5
, v1
, v2 row_shl
:1
4353 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x01,0x01,0xff]
4355 v_xor_b16_e64_dpp v5
, v1
, v2 row_shl
:15
4356 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x0f,0x01,0xff]
4358 v_xor_b16_e64_dpp v5
, v1
, v2 row_shr
:1
4359 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x11,0x01,0xff]
4361 v_xor_b16_e64_dpp v5
, v1
, v2 row_shr
:15
4362 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1f,0x01,0xff]
4364 v_xor_b16_e64_dpp v5
, v1
, v2 row_ror
:1
4365 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x21,0x01,0xff]
4367 v_xor_b16_e64_dpp v5
, v1
, v2 row_ror
:15
4368 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x2f,0x01,0xff]
4370 v_xor_b16_e64_dpp v5
, v1
, v2 row_share
:0 row_mask
:0xf bank_mask
:0xf
4371 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4373 v_xor_b16_e64_dpp v5
, v1
, v2 row_share
:15 row_mask
:0x0 bank_mask
:0x1
4374 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4376 v_xor_b16_e64_dpp v5
, v1
, v2 row_xmask
:0 row_mask
:0x1 bank_mask
:0x3 bound_ctrl
:1 fi
:0
4377 // GFX11
: [0x05,0x00,0x64,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x09,0x13]
4379 v_xor_b16_e64_dpp v255
, v255
, v255 row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:0 fi
:1
4380 // GFX11
: [0xff,0x00,0x64,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x05,0x30]
4382 v_add_nc_i16_e64_dpp v5
, v1
, v2 op_sel
:[1,1,1] row_share
:0 row_mask
:0xf bank_mask
:0xf
4383 // GFX11
: [0x05,0x58,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4385 v_add_nc_i16_e64_dpp v5
, v1
, v2 op_sel
:[1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4386 // GFX11
: [0x05,0x08,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4388 v_add_nc_i16_e64_dpp v5
, v1
, v2 op_sel
:[0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4389 // GFX11
: [0x05,0x10,0x0d,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
4391 v_add_nc_i16_e64_dpp v255
, v255
, v255 op_sel
:[0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4392 // GFX11
: [0xff,0xc0,0x0d,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
4394 v_add_nc_u16_e64_dpp v5
, v1
, v2 op_sel
:[1,1,1] row_share
:0 row_mask
:0xf bank_mask
:0xf
4395 // GFX11
: [0x05,0x58,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4397 v_add_nc_u16_e64_dpp v5
, v1
, v2 op_sel
:[1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4398 // GFX11
: [0x05,0x08,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4400 v_add_nc_u16_e64_dpp v5
, v1
, v2 op_sel
:[0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4401 // GFX11
: [0x05,0x10,0x03,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
4403 v_add_nc_u16_e64_dpp v255
, v255
, v255 op_sel
:[0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4404 // GFX11
: [0xff,0xc0,0x03,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
4406 v_cvt_pk_norm_i16_f16_e64_dpp v5
, -v1
, |v2| op_sel
:[1,0,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4407 // GFX11
: [0x05,0x0a,0x12,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
4409 v_cvt_pk_norm_i16_f16_e64_dpp v255
, -|v255|
, -|v255| op_sel
:[0,1,0] row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4410 // GFX11
: [0xff,0x13,0x12,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
4412 v_cvt_pk_norm_u16_f16_e64_dpp v5
, -v1
, |v2| op_sel
:[1,0,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4413 // GFX11
: [0x05,0x0a,0x13,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
4415 v_cvt_pk_norm_u16_f16_e64_dpp v255
, -|v255|
, -|v255| op_sel
:[0,1,0] row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4416 // GFX11
: [0xff,0x13,0x13,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
4418 v_div_fixup_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4419 // GFX11
: [0x05,0x7c,0x54,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
4421 v_div_fixup_f16_e64_dpp v5
, -|v1|
, -|v2|
, null op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4422 // GFX11
: [0x05,0x0b,0x54,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
4424 v_div_fixup_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1| op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4425 // GFX11
: [0x05,0x15,0x54,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
4427 v_div_fixup_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5| op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4428 // GFX11
: [0x05,0x26,0x54,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
4430 v_div_fixup_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| op_sel
:[0,0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4431 // GFX11
: [0xff,0xc7,0x54,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
4433 v_fma_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4434 // GFX11
: [0x05,0x7c,0x48,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
4436 v_fma_f16_e64_dpp v5
, -|v1|
, -|v2|
, null op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4437 // GFX11
: [0x05,0x0b,0x48,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
4439 v_fma_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1| op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4440 // GFX11
: [0x05,0x15,0x48,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
4442 v_fma_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5| op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4443 // GFX11
: [0x05,0x26,0x48,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
4445 v_fma_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| op_sel
:[0,0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4446 // GFX11
: [0xff,0xc7,0x48,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
4448 v_mad_i16_e64_dpp v5
, v1
, v2
, exec_hi op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4449 // GFX11
: [0x05,0x78,0x53,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
4451 v_mad_i16_e64_dpp v5
, v1
, v2
, exec_lo op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4452 // GFX11
: [0x05,0x08,0x53,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
4454 v_mad_i16_e64_dpp v5
, v1
, v2
, null op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4455 // GFX11
: [0x05,0x10,0x53,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
4457 v_mad_i16_e64_dpp v5
, v1
, v2
, -1 op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4458 // GFX11
: [0x05,0x20,0x53,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
4460 v_mad_i16_e64_dpp v255
, v255
, v255
, src_scc op_sel
:[0,0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4461 // GFX11
: [0xff,0xc0,0x53,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
4463 v_mad_i32_i16_e64_dpp v5
, v1
, v2
, 0.5 op_sel
:[1,0,0,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4464 // GFX11
: [0x05,0x08,0x5a,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
4466 v_mad_i32_i16_e64_dpp v255
, v255
, v255
, src_scc op_sel
:[0,1,0,0] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4467 // GFX11
: [0xff,0x90,0x5a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
4469 v_mad_u16_e64_dpp v5
, v1
, v2
, exec_hi op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4470 // GFX11
: [0x05,0x78,0x41,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
4472 v_mad_u16_e64_dpp v5
, v1
, v2
, exec_lo op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4473 // GFX11
: [0x05,0x08,0x41,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
4475 v_mad_u16_e64_dpp v5
, v1
, v2
, null op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4476 // GFX11
: [0x05,0x10,0x41,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
4478 v_mad_u16_e64_dpp v5
, v1
, v2
, -1 op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4479 // GFX11
: [0x05,0x20,0x41,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
4481 v_mad_u16_e64_dpp v255
, v255
, v255
, src_scc op_sel
:[0,0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4482 // GFX11
: [0xff,0xc0,0x41,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
4484 v_mad_u32_u16_e64_dpp v5
, v1
, v2
, 0.5 op_sel
:[1,0,0,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4485 // GFX11
: [0x05,0x08,0x59,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x60,0x01,0x13]
4487 v_mad_u32_u16_e64_dpp v255
, v255
, v255
, src_scc op_sel
:[0,1,0,0] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4488 // GFX11
: [0xff,0x90,0x59,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
4490 v_max3_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4491 // GFX11
: [0x05,0x7c,0x4c,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
4493 v_max3_f16_e64_dpp v5
, -|v1|
, -|v2|
, null op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4494 // GFX11
: [0x05,0x0b,0x4c,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
4496 v_max3_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1| op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4497 // GFX11
: [0x05,0x15,0x4c,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
4499 v_max3_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5| op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4500 // GFX11
: [0x05,0x26,0x4c,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
4502 v_max3_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| op_sel
:[0,0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4503 // GFX11
: [0xff,0xc7,0x4c,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
4505 v_max3_i16_e64_dpp v5
, v1
, v2
, exec_hi op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4506 // GFX11
: [0x05,0x78,0x4d,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
4508 v_max3_i16_e64_dpp v5
, v1
, v2
, exec_lo op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4509 // GFX11
: [0x05,0x08,0x4d,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
4511 v_max3_i16_e64_dpp v5
, v1
, v2
, null op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4512 // GFX11
: [0x05,0x10,0x4d,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
4514 v_max3_i16_e64_dpp v5
, v1
, v2
, -1 op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4515 // GFX11
: [0x05,0x20,0x4d,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
4517 v_max3_i16_e64_dpp v255
, v255
, v255
, src_scc op_sel
:[0,0,0,1] row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4518 // GFX11
: [0xff,0x40,0x4d,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
4520 v_max3_u16_e64_dpp v5
, v1
, v2
, exec_hi op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4521 // GFX11
: [0x05,0x78,0x4e,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
4523 v_max3_u16_e64_dpp v5
, v1
, v2
, exec_lo op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4524 // GFX11
: [0x05,0x08,0x4e,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
4526 v_max3_u16_e64_dpp v5
, v1
, v2
, null op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4527 // GFX11
: [0x05,0x10,0x4e,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
4529 v_max3_u16_e64_dpp v5
, v1
, v2
, -1 op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4530 // GFX11
: [0x05,0x20,0x4e,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
4532 v_max3_u16_e64_dpp v255
, v255
, v255
, src_scc op_sel
:[0,0,0,1] row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4533 // GFX11
: [0xff,0x40,0x4e,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
4535 v_med3_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4536 // GFX11
: [0x05,0x7c,0x4f,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
4538 v_med3_f16_e64_dpp v5
, -|v1|
, -|v2|
, null op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4539 // GFX11
: [0x05,0x0b,0x4f,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
4541 v_med3_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1| op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4542 // GFX11
: [0x05,0x15,0x4f,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
4544 v_med3_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5| op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4545 // GFX11
: [0x05,0x26,0x4f,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
4547 v_med3_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| op_sel
:[0,0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4548 // GFX11
: [0xff,0xc7,0x4f,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
4550 v_med3_i16_e64_dpp v5
, v1
, v2
, exec_hi op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4551 // GFX11
: [0x05,0x78,0x50,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
4553 v_med3_i16_e64_dpp v5
, v1
, v2
, exec_lo op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4554 // GFX11
: [0x05,0x08,0x50,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
4556 v_med3_i16_e64_dpp v5
, v1
, v2
, null op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4557 // GFX11
: [0x05,0x10,0x50,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
4559 v_med3_i16_e64_dpp v5
, v1
, v2
, -1 op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4560 // GFX11
: [0x05,0x20,0x50,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
4562 v_med3_i16_e64_dpp v255
, v255
, v255
, src_scc op_sel
:[0,0,0,1] row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4563 // GFX11
: [0xff,0x40,0x50,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
4565 v_med3_u16_e64_dpp v5
, v1
, v2
, exec_hi op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4566 // GFX11
: [0x05,0x78,0x51,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
4568 v_med3_u16_e64_dpp v5
, v1
, v2
, exec_lo op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4569 // GFX11
: [0x05,0x08,0x51,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
4571 v_med3_u16_e64_dpp v5
, v1
, v2
, null op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4572 // GFX11
: [0x05,0x10,0x51,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
4574 v_med3_u16_e64_dpp v5
, v1
, v2
, -1 op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4575 // GFX11
: [0x05,0x20,0x51,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
4577 v_med3_u16_e64_dpp v255
, v255
, v255
, src_scc op_sel
:[0,0,0,1] row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4578 // GFX11
: [0xff,0x40,0x51,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
4580 v_min3_f16_e64_dpp v5
, -v1
, v2
, |exec_lo| op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4581 // GFX11
: [0x05,0x7c,0x49,0xd6,0xfa,0x04,0xfa,0x21,0x01,0x2f,0x01,0xff]
4583 v_min3_f16_e64_dpp v5
, -|v1|
, -|v2|
, null op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4584 // GFX11
: [0x05,0x0b,0x49,0xd6,0xfa,0x04,0xf2,0x61,0x01,0x50,0x01,0xff]
4586 v_min3_f16_e64_dpp v5
, -|v1|
, v2
, -|
-1| op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4587 // GFX11
: [0x05,0x15,0x49,0xd6,0xfa,0x04,0x06,0xa3,0x01,0x5f,0x01,0x01]
4589 v_min3_f16_e64_dpp v5
, v1
, -|v2|
, -|
0.5| op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4590 // GFX11
: [0x05,0x26,0x49,0xd6,0xfa,0x04,0xc2,0xc3,0x01,0x60,0x01,0x13]
4592 v_min3_f16_e64_dpp v255
, -|v255|
, -|v255|
, -|src_scc| op_sel
:[0,0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4593 // GFX11
: [0xff,0xc7,0x49,0xd6,0xfa,0xfe,0xf7,0xe3,0xff,0x6f,0x0d,0x30]
4595 v_min3_i16_e64_dpp v5
, v1
, v2
, exec_hi op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4596 // GFX11
: [0x05,0x78,0x4a,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
4598 v_min3_i16_e64_dpp v5
, v1
, v2
, exec_lo op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4599 // GFX11
: [0x05,0x08,0x4a,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
4601 v_min3_i16_e64_dpp v5
, v1
, v2
, null op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4602 // GFX11
: [0x05,0x10,0x4a,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
4604 v_min3_i16_e64_dpp v5
, v1
, v2
, -1 op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4605 // GFX11
: [0x05,0x20,0x4a,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
4607 v_min3_i16_e64_dpp v255
, v255
, v255
, src_scc op_sel
:[0,0,0,1] row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4608 // GFX11
: [0xff,0x40,0x4a,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
4610 v_min3_u16_e64_dpp v5
, v1
, v2
, exec_hi op_sel
:[1,1,1,1] row_ror
:15 row_mask
:0xf bank_mask
:0xf
4611 // GFX11
: [0x05,0x78,0x4b,0xd6,0xfa,0x04,0xfe,0x01,0x01,0x2f,0x01,0xff]
4613 v_min3_u16_e64_dpp v5
, v1
, v2
, exec_lo op_sel
:[1,0,0,0] row_share
:0 row_mask
:0xf bank_mask
:0xf
4614 // GFX11
: [0x05,0x08,0x4b,0xd6,0xfa,0x04,0xfa,0x01,0x01,0x50,0x01,0xff]
4616 v_min3_u16_e64_dpp v5
, v1
, v2
, null op_sel
:[0,1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4617 // GFX11
: [0x05,0x10,0x4b,0xd6,0xfa,0x04,0xf2,0x01,0x01,0x5f,0x01,0x01]
4619 v_min3_u16_e64_dpp v5
, v1
, v2
, -1 op_sel
:[0,0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4620 // GFX11
: [0x05,0x20,0x4b,0xd6,0xfa,0x04,0x06,0x03,0x01,0x60,0x01,0x13]
4622 v_min3_u16_e64_dpp v255
, v255
, v255
, src_scc op_sel
:[0,0,0,1] row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4623 // GFX11
: [0xff,0x40,0x4b,0xd6,0xfa,0xfe,0xf7,0x03,0xff,0x6f,0x0d,0x30]
4625 v_pack_b32_f16_e64_dpp v5
, -v1
, |v2| op_sel
:[1,0,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4626 // GFX11
: [0x05,0x0a,0x11,0xd7,0xfa,0x04,0x02,0x20,0x01,0x60,0x01,0x13]
4628 v_pack_b32_f16_e64_dpp v255
, -|v255|
, -|v255| op_sel
:[0,1,0] row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4629 // GFX11
: [0xff,0x13,0x11,0xd7,0xfa,0xfe,0x03,0x60,0xff,0x6f,0x0d,0x30]
4631 v_sub_nc_i16_e64_dpp v5
, v1
, v2 op_sel
:[1,1,1] row_share
:0 row_mask
:0xf bank_mask
:0xf
4632 // GFX11
: [0x05,0x58,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4634 v_sub_nc_i16_e64_dpp v5
, v1
, v2 op_sel
:[1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4635 // GFX11
: [0x05,0x08,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4637 v_sub_nc_i16_e64_dpp v5
, v1
, v2 op_sel
:[0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4638 // GFX11
: [0x05,0x10,0x0e,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
4640 v_sub_nc_i16_e64_dpp v255
, v255
, v255 op_sel
:[0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4641 // GFX11
: [0xff,0xc0,0x0e,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
4643 v_sub_nc_u16_e64_dpp v5
, v1
, v2 op_sel
:[1,1,1] row_share
:0 row_mask
:0xf bank_mask
:0xf
4644 // GFX11
: [0x05,0x58,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x50,0x01,0xff]
4646 v_sub_nc_u16_e64_dpp v5
, v1
, v2 op_sel
:[1,0,0] row_share
:15 row_mask
:0x0 bank_mask
:0x1
4647 // GFX11
: [0x05,0x08,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x5f,0x01,0x01]
4649 v_sub_nc_u16_e64_dpp v5
, v1
, v2 op_sel
:[0,1,0] row_xmask
:0 row_mask
:0x1 bank_mask
:0x3
4650 // GFX11
: [0x05,0x10,0x04,0xd7,0xfa,0x04,0x02,0x00,0x01,0x60,0x01,0x13]
4652 v_sub_nc_u16_e64_dpp v255
, v255
, v255 op_sel
:[0,0,1] clamp row_xmask
:15 row_mask
:0x3 bank_mask
:0x0 bound_ctrl
:1 fi
:1
4653 // GFX11
: [0xff,0xc0,0x04,0xd7,0xfa,0xfe,0x03,0x00,0xff,0x6f,0x0d,0x30]
4655 v_dot2_f16_f16_e64_dpp v0
, v1
, v2
, v3 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 fi
:1
4656 // GFX11
: encoding
: [0x00,0x00,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
4658 v_dot2_f16_f16_e64_dpp v0
, v1
, v2
, v3 op_sel
:[1,1,0,0] quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 fi
:1
4659 // GFX11-ERR
: :[[@LINE-
1]]:{{[0-9]+}}: error
: invalid op_sel operand
4661 v_dot2_f16_f16_e64_dpp v0
, s1
, v2
, v3 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 fi
:1
4662 // GFX11-ERR
: :[[@LINE-
1]]:{{[0-9]+}}: error
: invalid operand for instruction
4664 v_dot2_f16_f16_e64_dpp v0
, v1
, s2
, v3 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 fi
:1
4665 // GFX11-ERR
: :[[@LINE-
1]]:{{[0-9]+}}: error
: invalid operand for instruction
4667 v_dot2_f16_f16_e64_dpp v0
, v1
, v2
, v3 op_sel
:[0,0,1,1] quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 fi
:1
4668 // GFX11
: encoding
: [0x00,0x60,0x66,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
4670 v_dot2_f16_f16_e64_dpp v0
, |v1|
, -v2
, -|s3| op_sel
:[0,0,1,1] quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 fi
:1
4671 // GFX11
: encoding
: [0x00,0x65,0x66,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00]
4673 v_dot2_f16_f16_e64_dpp v5
, v1
, v2
, 0.5 quad_perm
:[3,2,1,0] row_mask
:0xf bank_mask
:0xf
4674 // GFX11
: encoding
: [0x05,0x00,0x66,0xd6,0xfa,0x04,0xc2,0x03,0x01,0x1b,0x00,0xff]
4676 v_dot2_bf16_bf16_e64_dpp v0
, v1
, v2
, v3 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 fi
:1
4677 // GFX11
: encoding
: [0x00,0x00,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
4679 v_dot2_bf16_bf16_e64_dpp v0
, v1
, v2
, v3 op_sel
:[1,1,0,0] quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 fi
:1
4680 // GFX11-ERR
: :[[@LINE-
1]]:{{[0-9]+}}: error
: invalid op_sel operand
4682 v_dot2_bf16_bf16_e64_dpp v0
, s1
, v2
, v3 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
4683 // GFX11-ERR
: :[[@LINE-
1]]:{{[0-9]+}}: error
: invalid operand for instruction
4685 v_dot2_bf16_bf16_e64_dpp v0
, v1
, s2
, v3 quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0
4686 // GFX11-ERR
: :[[@LINE-
1]]:{{[0-9]+}}: error
: invalid operand for instruction
4688 v_dot2_bf16_bf16_e64_dpp v0
, v1
, v2
, v3 op_sel
:[0,0,1,1] quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 fi
:1
4689 // GFX11
: encoding
: [0x00,0x60,0x67,0xd6,0xfa,0x04,0x0e,0x04,0x01,0xe4,0x04,0x00]
4691 v_dot2_bf16_bf16_e64_dpp v0
, |v1|
, -v2
, -|s3| op_sel
:[0,0,1,1] quad_perm
:[0,1,2,3] row_mask
:0x0 bank_mask
:0x0 fi
:1
4692 // GFX11
: encoding
: [0x00,0x65,0x67,0xd6,0xfa,0x04,0x0e,0xc0,0x01,0xe4,0x04,0x00]
4694 v_dot2_bf16_bf16_e64_dpp v5
, v1
, v2
, 0 quad_perm
:[3,2,1,0] row_mask
:0xf bank_mask
:0xf
4695 // GFX11
: encoding
: [0x05,0x00,0x67,0xd6,0xfa,0x04,0x02,0x02,0x01,0x1b,0x00,0xff]