llvm/test/MC/AMDGPU/gfx11_unsupported_e32.s

   1 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
   2 // RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --implicit-check-not=error: %s
   3
   4 v_add_co_u32_e32 v2, vcc, s0, v2
   5 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
   6
   7 v_ashrrev_i16_e32 v1, v2, v3
   8 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
   9
  10 v_lshlrev_b16_e32 v1, v2, v3
  11 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  12
  13 v_lshrrev_b16_e32 v1, v2, v3
  14 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  15
  16 v_max_i16_e32 v1, v2, v3
  17 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  18
  19 v_max_u16_e32 v1, v2, v3
  20 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  21
  22 v_min_i16_e32 v1, v2, v3
  23 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  24
  25 v_min_u16_e32 v1, v2, v3
  26 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  27
  28 v_mul_lo_u16_e32 v1, v2, v3
  29 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  30
  31 v_sub_co_u32_e32 v2, vcc, s0, v2
  32 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported
  33
  34 v_subrev_co_u32_e32 v2, vcc, s0, v2
  35 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: e32 variant of this instruction is not supported