1 # RUN: llvm-mc -triple=aarch64 -mattr=+v8a,+fp-armv8 -disassemble < %s | FileCheck %s
2 # RUN: llvm-mc -triple=arm64 -mattr=+v8a,+fp-armv8 -disassemble < %s | FileCheck %s
3 # RUN: llvm-mc -triple=arm64 -mattr=+v8a,+fp-armv8,+fullfp16 -disassemble < %s | FileCheck %s --check-prefix=CHECK --check-prefix=FP16
4 # RUN: llvm-mc -triple=arm64 -mattr=+v8.2a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V82
5 # RUN: llvm-mc -triple=arm64 -mattr=+v8.3a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V83
7 #------------------------------------------------------------------------------
9 #------------------------------------------------------------------------------
10 # CHECK: add w4, w5, #0
11 # CHECK: add w2, w3, #4095
12 # CHECK: add w30, w29, #1, lsl #12
13 # CHECK: add w13, w5, #4095, lsl #12
14 # CHECK: add x5, x7, #1638
21 # CHECK: add w20, wsp, #801
22 # CHECK: add wsp, wsp, #1104
23 # CHECK: add wsp, w30, #4084
28 # CHECK: add x0, x24, #291
29 # CHECK: add x3, x24, #4095, lsl #12
30 # CHECK: add x8, sp, #1074
31 # CHECK: add sp, x29, #3816
37 # CHECK: sub w0, wsp, #4077
38 # CHECK: sub w4, w20, #546, lsl #12
39 # CHECK: sub sp, sp, #288
40 # CHECK: sub wsp, w19, #16
47 # CHECK: adds w13, w23, #291, lsl #12
48 # CHECK: cmn w2, #4095
49 # CHECK: adds w20, wsp, #0
50 # CHECK: cmn x3, #1, lsl #12
56 # CHECK: cmp sp, #20, lsl #12
57 # CHECK: cmp x30, #4095
58 # CHECK: subs x4, sp, #3822
63 # These should really be CMN
64 # CHECK: cmn w3, #291, lsl #12
65 # CHECK: cmn wsp, #1365
66 # CHECK: cmn sp, #1092, lsl #12
80 #------------------------------------------------------------------------------
81 # Add-subtract (shifted register)
82 #------------------------------------------------------------------------------
84 # CHECK: add w3, w5, w7
85 # CHECK: add wzr, w3, w5
86 # CHECK: add w20, wzr, w4
87 # CHECK: add w4, w6, wzr
88 # CHECK: add w11, w13, w15
89 # CHECK: add w9, w3, wzr, lsl #10
90 # CHECK: add w17, w29, w20, lsl #31
91 # CHECK: add w21, w22, w23, lsr #0
92 # CHECK: add w24, w25, w26, lsr #18
93 # CHECK: add w27, w28, w29, lsr #31
94 # CHECK: add w2, w3, w4, asr #0
95 # CHECK: add w5, w6, w7, asr #21
96 # CHECK: add w8, w9, w10, asr #31
111 # CHECK: add x3, x5, x7
112 # CHECK: add xzr, x3, x5
113 # CHECK: add x20, xzr, x4
114 # CHECK: add x4, x6, xzr
115 # CHECK: add x11, x13, x15
116 # CHECK: add x9, x3, xzr, lsl #10
117 # CHECK: add x17, x29, x20, lsl #63
118 # CHECK: add x21, x22, x23, lsr #0
119 # CHECK: add x24, x25, x26, lsr #18
120 # CHECK: add x27, x28, x29, lsr #63
121 # CHECK: add x2, x3, x4, asr #0
122 # CHECK: add x5, x6, x7, asr #21
123 # CHECK: add x8, x9, x10, asr #63
138 # CHECK: adds w3, w5, w7
140 # CHECK: adds w20, wzr, w4
141 # CHECK: adds w4, w6, wzr
142 # CHECK: adds w11, w13, w15
143 # CHECK: adds w9, w3, wzr, lsl #10
144 # CHECK: adds w17, w29, w20, lsl #31
145 # CHECK: adds w21, w22, w23, lsr #0
146 # CHECK: adds w24, w25, w26, lsr #18
147 # CHECK: adds w27, w28, w29, lsr #31
148 # CHECK: adds w2, w3, w4, asr #0
149 # CHECK: adds w5, w6, w7, asr #21
150 # CHECK: adds w8, w9, w10, asr #31
165 # CHECK: adds x3, x5, x7
167 # CHECK: adds x20, xzr, x4
168 # CHECK: adds x4, x6, xzr
169 # CHECK: adds x11, x13, x15
170 # CHECK: adds x9, x3, xzr, lsl #10
171 # CHECK: adds x17, x29, x20, lsl #63
172 # CHECK: adds x21, x22, x23, lsr #0
173 # CHECK: adds x24, x25, x26, lsr #18
174 # CHECK: adds x27, x28, x29, lsr #63
175 # CHECK: adds x2, x3, x4, asr #0
176 # CHECK: adds x5, x6, x7, asr #21
177 # CHECK: adds x8, x9, x10, asr #63
192 # CHECK: sub w3, w5, w7
193 # CHECK: sub wzr, w3, w5
194 # CHECK: {{sub w20, wzr, w4|neg w20, w4}}
195 # CHECK: sub w4, w6, wzr
196 # CHECK: sub w11, w13, w15
197 # CHECK: sub w9, w3, wzr, lsl #10
198 # CHECK: sub w17, w29, w20, lsl #31
199 # CHECK: sub w21, w22, w23, lsr #0
200 # CHECK: sub w24, w25, w26, lsr #18
201 # CHECK: sub w27, w28, w29, lsr #31
202 # CHECK: sub w2, w3, w4, asr #0
203 # CHECK: sub w5, w6, w7, asr #21
204 # CHECK: sub w8, w9, w10, asr #31
219 # CHECK: sub x3, x5, x7
220 # CHECK: sub xzr, x3, x5
221 # CHECK: {{sub x20, xzr, x4|neg x20, x4}}
222 # CHECK: sub x4, x6, xzr
223 # CHECK: sub x11, x13, x15
224 # CHECK: sub x9, x3, xzr, lsl #10
225 # CHECK: sub x17, x29, x20, lsl #63
226 # CHECK: sub x21, x22, x23, lsr #0
227 # CHECK: sub x24, x25, x26, lsr #18
228 # CHECK: sub x27, x28, x29, lsr #63
229 # CHECK: sub x2, x3, x4, asr #0
230 # CHECK: sub x5, x6, x7, asr #21
231 # CHECK: sub x8, x9, x10, asr #63
246 # CHECK: subs w3, w5, w7
248 # CHECK: {{subs w20, wzr, w4|negs w20, w4}}
249 # CHECK: subs w4, w6, wzr
250 # CHECK: subs w11, w13, w15
251 # CHECK: subs w9, w3, wzr, lsl #10
252 # CHECK: subs w17, w29, w20, lsl #31
253 # CHECK: subs w21, w22, w23, lsr #0
254 # CHECK: subs w24, w25, w26, lsr #18
255 # CHECK: subs w27, w28, w29, lsr #31
256 # CHECK: subs w2, w3, w4, asr #0
257 # CHECK: subs w5, w6, w7, asr #21
258 # CHECK: subs w8, w9, w10, asr #31
273 # CHECK: subs x3, x5, x7
275 # CHECK: {{subs x20, xzr, x4|negs x20, x4}}
276 # CHECK: subs x4, x6, xzr
277 # CHECK: subs x11, x13, x15
278 # CHECK: subs x9, x3, xzr, lsl #10
279 # CHECK: subs x17, x29, x20, lsl #63
280 # CHECK: subs x21, x22, x23, lsr #0
281 # CHECK: subs x24, x25, x26, lsr #18
282 # CHECK: subs x27, x28, x29, lsr #63
283 # CHECK: subs x2, x3, x4, asr #0
284 # CHECK: subs x5, x6, x7, asr #21
285 # CHECK: subs x8, x9, x10, asr #63
304 # CHECK: cmn w8, w9, lsl #15
305 # CHECK: cmn w10, w11, lsl #31
306 # CHECK: cmn w12, w13, lsr #0
307 # CHECK: cmn w14, w15, lsr #21
308 # CHECK: cmn w16, w17, lsr #31
309 # CHECK: cmn w18, w19, asr #0
310 # CHECK: cmn w20, w21, asr #22
311 # CHECK: cmn w22, w23, asr #31
329 # CHECK: cmn x8, x9, lsl #15
330 # CHECK: cmn x10, x11, lsl #63
331 # CHECK: cmn x12, x13, lsr #0
332 # CHECK: cmn x14, x15, lsr #41
333 # CHECK: cmn x16, x17, lsr #63
334 # CHECK: cmn x18, x19, asr #0
335 # CHECK: cmn x20, x21, asr #55
336 # CHECK: cmn x22, x23, asr #63
354 # CHECK: cmp w8, w9, lsl #15
355 # CHECK: cmp w10, w11, lsl #31
356 # CHECK: cmp w12, w13, lsr #0
357 # CHECK: cmp w14, w15, lsr #21
358 # CHECK: cmp w16, w17, lsr #31
359 # CHECK: cmp w18, w19, asr #0
360 # CHECK: cmp w20, w21, asr #22
361 # CHECK: cmp w22, w23, asr #31
379 # CHECK: cmp x8, x9, lsl #15
380 # CHECK: cmp x10, x11, lsl #63
381 # CHECK: cmp x12, x13, lsr #0
382 # CHECK: cmp x14, x15, lsr #41
383 # CHECK: cmp x16, x17, lsr #63
384 # CHECK: cmp x18, x19, asr #0
385 # CHECK: cmp x20, x21, asr #55
386 # CHECK: cmp x22, x23, asr #63
400 # CHECK: {{sub w29, wzr|neg w29}}, w30
401 # CHECK: {{sub w30, wzr|neg w30}}, wzr
402 # CHECK: {{sub wzr, wzr|neg wzr}}, w0
403 # CHECK: {{sub w28, wzr|neg w28}}, w27
404 # CHECK: {{sub w26, wzr|neg w26}}, w25, lsl #29
405 # CHECK: {{sub w24, wzr|neg w24}}, w23, lsl #31
406 # CHECK: {{sub w22, wzr|neg w22}}, w21, lsr #0
407 # CHECK: {{sub w20, wzr|neg w20}}, w19, lsr #1
408 # CHECK: {{sub w18, wzr|neg w18}}, w17, lsr #31
409 # CHECK: {{sub w16, wzr|neg w16}}, w15, asr #0
410 # CHECK: {{sub w14, wzr|neg w14}}, w13, asr #12
411 # CHECK: {{sub w12, wzr|neg w12}}, w11, asr #31
425 # CHECK: {{sub x29, xzr|neg x29}}, x30
426 # CHECK: {{sub x30, xzr|neg x30}}, xzr
427 # CHECK: {{sub xzr, xzr|neg xzr}}, x0
428 # CHECK: {{sub x28, xzr|neg x28}}, x27
429 # CHECK: {{sub x26, xzr|neg x26}}, x25, lsl #29
430 # CHECK: {{sub x24, xzr|neg x24}}, x23, lsl #31
431 # CHECK: {{sub x22, xzr|neg x22}}, x21, lsr #0
432 # CHECK: {{sub x20, xzr|neg x20}}, x19, lsr #1
433 # CHECK: {{sub x18, xzr|neg x18}}, x17, lsr #31
434 # CHECK: {{sub x16, xzr|neg x16}}, x15, asr #0
435 # CHECK: {{sub x14, xzr|neg x14}}, x13, asr #12
436 # CHECK: {{sub x12, xzr|neg x12}}, x11, asr #31
450 # CHECK: {{subs w29, wzr|negs w29}}, w30
451 # CHECK: {{subs w30, wzr|negs w30}}, wzr
453 # CHECK: {{subs w28, wzr|negs w28}}, w27
454 # CHECK: {{subs w26, wzr|negs w26}}, w25, lsl #29
455 # CHECK: {{subs w24, wzr|negs w24}}, w23, lsl #31
456 # CHECK: {{subs w22, wzr|negs w22}}, w21, lsr #0
457 # CHECK: {{subs w20, wzr|negs w20}}, w19, lsr #1
458 # CHECK: {{subs w18, wzr|negs w18}}, w17, lsr #31
459 # CHECK: {{subs w16, wzr|negs w16}}, w15, asr #0
460 # CHECK: {{subs w14, wzr|negs w14}}, w13, asr #12
461 # CHECK: {{subs w12, wzr|negs w12}}, w11, asr #31
475 # CHECK: {{subs x29, xzr|negs x29}}, x30
476 # CHECK: {{subs x30, xzr|negs x30}}, xzr
478 # CHECK: {{subs x28, xzr|negs x28}}, x27
479 # CHECK: {{subs x26, xzr|negs x26}}, x25, lsl #29
480 # CHECK: {{subs x24, xzr|negs x24}}, x23, lsl #31
481 # CHECK: {{subs x22, xzr|negs x22}}, x21, lsr #0
482 # CHECK: {{subs x20, xzr|negs x20}}, x19, lsr #1
483 # CHECK: {{subs x18, xzr|negs x18}}, x17, lsr #31
484 # CHECK: {{subs x16, xzr|negs x16}}, x15, asr #0
485 # CHECK: {{subs x14, xzr|negs x14}}, x13, asr #12
486 # CHECK: {{subs x12, xzr|negs x12}}, x11, asr #31
500 #------------------------------------------------------------------------------
501 # Add-subtract (shifted register)
502 #------------------------------------------------------------------------------
504 # CHECK: adc w29, w27, w25
505 # CHECK: adc wzr, w3, w4
506 # CHECK: adc w9, wzr, w10
507 # CHECK: adc w20, w0, wzr
513 # CHECK: adc x29, x27, x25
514 # CHECK: adc xzr, x3, x4
515 # CHECK: adc x9, xzr, x10
516 # CHECK: adc x20, x0, xzr
522 # CHECK: adcs w29, w27, w25
523 # CHECK: adcs wzr, w3, w4
524 # CHECK: adcs w9, wzr, w10
525 # CHECK: adcs w20, w0, wzr
531 # CHECK: adcs x29, x27, x25
532 # CHECK: adcs xzr, x3, x4
533 # CHECK: adcs x9, xzr, x10
534 # CHECK: adcs x20, x0, xzr
540 # CHECK: sbc w29, w27, w25
541 # CHECK: sbc wzr, w3, w4
543 # CHECK: sbc w20, w0, wzr
549 # CHECK: sbc x29, x27, x25
550 # CHECK: sbc xzr, x3, x4
552 # CHECK: sbc x20, x0, xzr
558 # CHECK: sbcs w29, w27, w25
559 # CHECK: sbcs wzr, w3, w4
560 # CHECK: ngcs w9, w10
561 # CHECK: sbcs w20, w0, wzr
567 # CHECK: sbcs x29, x27, x25
568 # CHECK: sbcs xzr, x3, x4
569 # CHECK: ngcs x9, x10
570 # CHECK: sbcs x20, x0, xzr
578 # CHECK: ngc w23, wzr
583 # CHECK: ngc x29, x30
590 # CHECK: ngcs w3, w12
591 # CHECK: ngcs wzr, w9
592 # CHECK: ngcs w23, wzr
597 # CHECK: ngcs x29, x30
598 # CHECK: ngcs xzr, x0
599 # CHECK: ngcs x0, xzr
604 #------------------------------------------------------------------------------
605 # Compare and branch (immediate)
606 #------------------------------------------------------------------------------
608 # CHECK: sbfx x1, x2, #3, #2
609 # CHECK: asr x3, x4, #63
610 # CHECK: asr wzr, wzr, #31
611 # CHECK: sbfx w12, w9, #0, #1
617 # CHECK: ubfiz x4, x5, #52, #11
618 # CHECK: ubfx xzr, x4, #0, #1
619 # CHECK: ubfiz x4, xzr, #1, #6
620 # CHECK: lsr x5, x6, #12
626 # CHECK: bfi x4, x5, #52, #11
627 # CHECK: bfxil xzr, x4, #0, #1
628 # CHECK: bfi x4, xzr, #1, #6
629 # CHECK-V82: bfc x4, #1, #6
630 # CHECK: bfxil x5, x6, #12, #52
637 # CHECK: sxtb xzr, w3
638 # CHECK: sxth w9, w10
640 # CHECK: sxtw x3, w30
648 # CHECK: uxth w9, w10
649 # CHECK: ubfx x3, x30, #0, #32
654 # CHECK: asr w3, w2, #0
655 # CHECK: asr w9, w10, #31
656 # CHECK: asr x20, x21, #63
657 # CHECK: asr w1, wzr, #3
663 # CHECK: lsr w3, w2, #0
664 # CHECK: lsr w9, w10, #31
665 # CHECK: lsr x20, x21, #63
666 # CHECK: lsr wzr, wzr, #3
672 # CHECK: lsr w3, w2, #0
673 # CHECK: lsl w9, w10, #31
674 # CHECK: lsl x20, x21, #63
675 # CHECK: lsl w1, wzr, #3
681 # CHECK: sbfx w9, w10, #0, #1
682 # CHECK: sbfiz x2, x3, #63, #1
683 # CHECK: asr x19, x20, #0
684 # CHECK: sbfiz x9, x10, #5, #59
685 # CHECK: asr w9, w10, #0
686 # CHECK: sbfiz w11, w12, #31, #1
687 # CHECK: sbfiz w13, w14, #29, #3
688 # CHECK: sbfiz xzr, xzr, #10, #11
698 # CHECK: sbfx w9, w10, #0, #1
699 # CHECK: asr x2, x3, #63
700 # CHECK: asr x19, x20, #0
701 # CHECK: asr x9, x10, #5
702 # CHECK: asr w9, w10, #0
703 # CHECK: asr w11, w12, #31
704 # CHECK: asr w13, w14, #29
705 # CHECK: sbfx xzr, xzr, #10, #11
715 # CHECK: bfxil w9, w10, #0, #1
716 # CHECK: bfi x2, x3, #63, #1
717 # CHECK: bfxil x19, x20, #0, #64
718 # CHECK: bfi x9, x10, #5, #59
719 # CHECK: bfxil w9, w10, #0, #32
720 # CHECK: bfi w11, w12, #31, #1
721 # CHECK: bfi w13, w14, #29, #3
722 # CHECK-V82: bfc xzr, #10, #11
723 # CHECK: bfi xzr, xzr, #10, #11
733 # CHECK: bfxil w9, w10, #0, #1
734 # CHECK: bfxil x2, x3, #63, #1
735 # CHECK: bfxil x19, x20, #0, #64
736 # CHECK: bfxil x9, x10, #5, #59
737 # CHECK: bfxil w9, w10, #0, #32
738 # CHECK: bfxil w11, w12, #31, #1
739 # CHECK: bfxil w13, w14, #29, #3
740 # CHECK: bfxil xzr, xzr, #10, #11
750 # CHECK: ubfx w9, w10, #0, #1
751 # CHECK: lsl x2, x3, #63
752 # CHECK: lsr x19, x20, #0
753 # CHECK: lsl x9, x10, #5
754 # CHECK: lsr w9, w10, #0
755 # CHECK: lsl w11, w12, #31
756 # CHECK: lsl w13, w14, #29
757 # CHECK: ubfiz xzr, xzr, #10, #11
767 # CHECK: ubfx w9, w10, #0, #1
768 # CHECK: lsr x2, x3, #63
769 # CHECK: lsr x19, x20, #0
770 # CHECK: lsr x9, x10, #5
771 # CHECK: lsr w9, w10, #0
772 # CHECK: lsr w11, w12, #31
773 # CHECK: lsr w13, w14, #29
774 # CHECK: ubfx xzr, xzr, #10, #11
785 #------------------------------------------------------------------------------
786 # Compare and branch (immediate)
787 #------------------------------------------------------------------------------
791 # CHECK: cbnz x2, #-4
792 # CHECK: cbnz x26, #1048572
799 # CHECK: cbnz xzr, #0
803 #------------------------------------------------------------------------------
804 # Conditional branch (immediate)
805 #------------------------------------------------------------------------------
808 # CHECK: b.ge #1048572
814 #------------------------------------------------------------------------------
815 # Conditional compare (immediate)
816 #------------------------------------------------------------------------------
818 # CHECK: ccmp w1, #31, #0, eq
819 # CHECK: ccmp w3, #0, #15, hs
820 # CHECK: ccmp wzr, #15, #13, hs
825 # CHECK: ccmp x9, #31, #0, le
826 # CHECK: ccmp x3, #0, #15, gt
827 # CHECK: ccmp xzr, #5, #7, ne
832 # CHECK: ccmn w1, #31, #0, eq
833 # CHECK: ccmn w3, #0, #15, hs
834 # CHECK: ccmn wzr, #15, #13, hs
839 # CHECK: ccmn x9, #31, #0, le
840 # CHECK: ccmn x3, #0, #15, gt
841 # CHECK: ccmn xzr, #5, #7, ne
846 #------------------------------------------------------------------------------
847 # Conditional compare (register)
848 #------------------------------------------------------------------------------
850 # CHECK: ccmp w1, wzr, #0, eq
851 # CHECK: ccmp w3, w0, #15, hs
852 # CHECK: ccmp wzr, w15, #13, hs
857 # CHECK: ccmp x9, xzr, #0, le
858 # CHECK: ccmp x3, x0, #15, gt
859 # CHECK: ccmp xzr, x5, #7, ne
864 # CHECK: ccmn w1, wzr, #0, eq
865 # CHECK: ccmn w3, w0, #15, hs
866 # CHECK: ccmn wzr, w15, #13, hs
871 # CHECK: ccmn x9, xzr, #0, le
872 # CHECK: ccmn x3, x0, #15, gt
873 # CHECK: ccmn xzr, x5, #7, ne
878 #------------------------------------------------------------------------------
879 # Conditional branch (immediate)
880 #------------------------------------------------------------------------------
881 # CHECK: csel w1, w0, w19, ne
882 # CHECK: csel wzr, w5, w9, eq
883 # CHECK: csel w9, wzr, w30, gt
884 # CHECK: csel w1, w28, wzr, mi
885 # CHECK: csel x19, x23, x29, lt
886 # CHECK: csel xzr, x3, x4, ge
887 # CHECK: csel x5, xzr, x6, hs
888 # CHECK: csel x7, x8, xzr, lo
898 # CHECK: csinc w1, w0, w19, ne
899 # CHECK: csinc wzr, w5, w9, eq
900 # CHECK: csinc w9, wzr, w30, gt
901 # CHECK: csinc w1, w28, wzr, mi
902 # CHECK: csinc x19, x23, x29, lt
903 # CHECK: csinc xzr, x3, x4, ge
904 # CHECK: csinc x5, xzr, x6, hs
905 # CHECK: csinc x7, x8, xzr, lo
915 # CHECK: csinv w1, w0, w19, ne
916 # CHECK: csinv wzr, w5, w9, eq
917 # CHECK: csinv w9, wzr, w30, gt
918 # CHECK: csinv w1, w28, wzr, mi
919 # CHECK: csinv x19, x23, x29, lt
920 # CHECK: csinv xzr, x3, x4, ge
921 # CHECK: csinv x5, xzr, x6, hs
922 # CHECK: csinv x7, x8, xzr, lo
932 # CHECK: csneg w1, w0, w19, ne
933 # CHECK: csneg wzr, w5, w9, eq
934 # CHECK: csneg w9, wzr, w30, gt
935 # CHECK: csneg w1, w28, wzr, mi
936 # CHECK: csneg x19, x23, x29, lt
937 # CHECK: csneg xzr, x3, x4, ge
938 # CHECK: csneg x5, xzr, x6, hs
939 # CHECK: csneg x7, x8, xzr, lo
951 # CHECK: csetm w20, ne
952 # CHECK: csetm x30, ge
953 # "cset w2, nv" and "csetm x3, al" are invalid aliases for these two
954 # CHECK: csinc w2, wzr, wzr, al
955 # CHECK: csinv x3, xzr, xzr, nv
963 # CHECK: cinc w3, w5, gt
964 # CHECK: cinc wzr, w4, le
966 # CHECK: cinc x3, x5, gt
967 # CHECK: cinc xzr, x4, le
969 # "cinc w5, w6, al" and "cinc x1, x2, nv" are invalid aliases for these two
970 # CHECK: csinc w5, w6, w6, nv
971 # CHECK: csinc x1, x2, x2, al
981 # CHECK: cinv w3, w5, gt
982 # CHECK: cinv wzr, w4, le
983 # CHECK: csetm w9, lt
984 # CHECK: cinv x3, x5, gt
985 # CHECK: cinv xzr, x4, le
986 # CHECK: csetm x9, lt
987 # "cinv x1, x0, nv" and "cinv w9, w8, al" are invalid aliases for these two
988 # CHECK: csinv x1, x0, x0, al
989 # CHECK: csinv w9, w8, w8, nv
999 # CHECK: cneg w3, w5, gt
1000 # CHECK: cneg wzr, w4, le
1001 # CHECK: cneg w9, wzr, lt
1002 # CHECK: cneg x3, x5, gt
1003 # CHECK: cneg xzr, x4, le
1004 # CHECK: cneg x9, xzr, lt
1005 # "cneg x4, x8, nv" and "cneg w5, w6, al" are invalid aliases for these two
1006 # CHECK: csneg x4, x8, x8, al
1007 # CHECK: csinv w9, w8, w8, nv
1017 #------------------------------------------------------------------------------
1018 # Data-processing (1 source)
1019 #------------------------------------------------------------------------------
1021 # CHECK: rbit w0, w7
1022 # CHECK: rbit x18, x3
1023 # CHECK: rev16 w17, w1
1024 # CHECK: rev16 x5, x2
1025 # CHECK: rev w18, w0
1026 # CHECK: rev32 x20, x1
1034 # CHECK: rev x22, x2
1035 # CHECK: clz w24, w3
1036 # CHECK: clz x26, x4
1038 # CHECK: cls x20, x5
1045 #------------------------------------------------------------------------------
1046 # Data-processing (2 source)
1047 #------------------------------------------------------------------------------
1049 # CHECK: udiv w0, w7, w10
1050 # CHECK: udiv x9, x22, x4
1051 # CHECK: sdiv w12, w21, w0
1052 # CHECK: sdiv x13, x2, x1
1053 # CHECK: lsl w11, w12, w13
1054 # CHECK: lsl x14, x15, x16
1055 # CHECK: lsr w17, w18, w19
1056 # CHECK: lsr x20, x21, x22
1057 # CHECK: asr w23, w24, w25
1058 # CHECK: asr x26, x27, x28
1059 # CHECK: ror w0, w1, w2
1060 # CHECK: ror x3, x4, x5
1074 # CHECK: lsl w6, w7, w8
1075 # CHECK: lsl x9, x10, x11
1076 # CHECK: lsr w12, w13, w14
1077 # CHECK: lsr x15, x16, x17
1078 # CHECK: asr w18, w19, w20
1079 # CHECK: asr x21, x22, x23
1080 # CHECK: ror w24, w25, w26
1081 # CHECK: ror x27, x28, x29
1091 #------------------------------------------------------------------------------
1092 # Data-processing (3 sources)
1093 #------------------------------------------------------------------------------
1095 # First check some non-canonical encodings where Ra is not 0b11111 (only umulh
1096 # and smulh have them).
1098 # CHECK: smulh x30, x29, x28
1099 # CHECK: smulh xzr, x27, x26
1100 # CHECK: umulh x30, x29, x28
1101 # CHECK: umulh x23, x30, xzr
1107 # Now onto the boilerplate stuff
1109 # CHECK: madd w1, w3, w7, w4
1110 # CHECK: madd wzr, w0, w9, w11
1111 # CHECK: madd w13, wzr, w4, w4
1112 # CHECK: madd w19, w30, wzr, w29
1113 # CHECK: mul w4, w5, w6
1120 # CHECK: madd x1, x3, x7, x4
1121 # CHECK: madd xzr, x0, x9, x11
1122 # CHECK: madd x13, xzr, x4, x4
1123 # CHECK: madd x19, x30, xzr, x29
1124 # CHECK: mul x4, x5, x6
1131 # CHECK: msub w1, w3, w7, w4
1132 # CHECK: msub wzr, w0, w9, w11
1133 # CHECK: msub w13, wzr, w4, w4
1134 # CHECK: msub w19, w30, wzr, w29
1135 # CHECK: mneg w4, w5, w6
1142 # CHECK: msub x1, x3, x7, x4
1143 # CHECK: msub xzr, x0, x9, x11
1144 # CHECK: msub x13, xzr, x4, x4
1145 # CHECK: msub x19, x30, xzr, x29
1146 # CHECK: mneg x4, x5, x6
1153 # CHECK: smaddl x3, w5, w2, x9
1154 # CHECK: smaddl xzr, w10, w11, x12
1155 # CHECK: smaddl x13, wzr, w14, x15
1156 # CHECK: smaddl x16, w17, wzr, x18
1157 # CHECK: smull x19, w20, w21
1164 # CHECK: smsubl x3, w5, w2, x9
1165 # CHECK: smsubl xzr, w10, w11, x12
1166 # CHECK: smsubl x13, wzr, w14, x15
1167 # CHECK: smsubl x16, w17, wzr, x18
1168 # CHECK: smnegl x19, w20, w21
1175 # CHECK: umaddl x3, w5, w2, x9
1176 # CHECK: umaddl xzr, w10, w11, x12
1177 # CHECK: umaddl x13, wzr, w14, x15
1178 # CHECK: umaddl x16, w17, wzr, x18
1179 # CHECK: umull x19, w20, w21
1186 # CHECK: umsubl x3, w5, w2, x9
1187 # CHECK: umsubl xzr, w10, w11, x12
1188 # CHECK: umsubl x13, wzr, w14, x15
1189 # CHECK: umsubl x16, w17, wzr, x18
1190 # CHECK: umnegl x19, w20, w21
1197 # CHECK: smulh x30, x29, x28
1198 # CHECK: smulh xzr, x27, x26
1199 # CHECK: smulh x25, xzr, x24
1200 # CHECK: smulh x23, x22, xzr
1206 # CHECK: umulh x30, x29, x28
1207 # CHECK: umulh xzr, x27, x26
1208 # CHECK: umulh x25, xzr, x24
1209 # CHECK: umulh x23, x22, xzr
1215 # CHECK: mul w3, w4, w5
1216 # CHECK: mul wzr, w6, w7
1217 # CHECK: mul w8, wzr, w9
1218 # CHECK: mul w10, w11, wzr
1219 # CHECK: mul x12, x13, x14
1220 # CHECK: mul xzr, x15, x16
1221 # CHECK: mul x17, xzr, x18
1222 # CHECK: mul x19, x20, xzr
1232 # CHECK: mneg w21, w22, w23
1233 # CHECK: mneg wzr, w24, w25
1234 # CHECK: mneg w26, wzr, w27
1235 # CHECK: mneg w28, w29, wzr
1241 # CHECK: smull x11, w13, w17
1242 # CHECK: umull x11, w13, w17
1243 # CHECK: smnegl x11, w13, w17
1244 # CHECK: umnegl x11, w13, w17
1250 #------------------------------------------------------------------------------
1251 # Exception generation
1252 #------------------------------------------------------------------------------
1255 # CHECK: svc #{{65535|0xffff}}
1259 # CHECK: hvc #{{1|0x1}}
1260 # CHECK: smc #{{12000|0x2ee0}}
1261 # CHECK: brk #{{12|0xc}}
1262 # CHECK: hlt #{{123|0x7b}}
1268 # CHECK: dcps1 #{{42|0x2a}}
1269 # CHECK: dcps2 #{{9|0x9}}
1270 # CHECK: dcps3 #{{1000|0x3e8}}
1282 #------------------------------------------------------------------------------
1283 # Extract (immediate)
1284 #------------------------------------------------------------------------------
1286 # CHECK: extr w3, w5, w7, #0
1287 # CHECK: extr w11, w13, w17, #31
1291 # CHECK: extr x3, x5, x7, #15
1292 # CHECK: extr x11, x13, x17, #63
1296 # CHECK: ror x19, x23, #24
1297 # CHECK: ror x29, xzr, #63
1298 # CHECK: ror w9, w13, #31
1303 #------------------------------------------------------------------------------
1304 # Floating-point compare
1305 #------------------------------------------------------------------------------
1307 # CHECK: fcmp s3, s5
1308 # CHECK: fcmp s31, #0.0
1309 # CHECK: fcmp s31, #0.0
1314 # CHECK: fcmpe s29, s30
1315 # CHECK: fcmpe s15, #0.0
1316 # CHECK: fcmpe s15, #0.0
1321 # CHECK: fcmp d4, d12
1322 # CHECK: fcmp d23, #0.0
1323 # CHECK: fcmp d23, #0.0
1328 # CHECK: fcmpe d26, d22
1329 # CHECK: fcmpe d29, #0.0
1330 # CHECK: fcmpe d29, #0.0
1335 #------------------------------------------------------------------------------
1336 # Floating-point conditional compare
1337 #------------------------------------------------------------------------------
1339 # CHECK: fccmp s1, s31, #0, eq
1340 # CHECK: fccmp s3, s0, #15, hs
1341 # CHECK: fccmp s31, s15, #13, hs
1346 # CHECK: fccmp d9, d31, #0, le
1347 # CHECK: fccmp d3, d0, #15, gt
1348 # CHECK: fccmp d31, d5, #7, ne
1353 # CHECK: fccmpe s1, s31, #0, eq
1354 # CHECK: fccmpe s3, s0, #15, hs
1355 # CHECK: fccmpe s31, s15, #13, hs
1360 # CHECK: fccmpe d9, d31, #0, le
1361 # CHECK: fccmpe d3, d0, #15, gt
1362 # CHECK: fccmpe d31, d5, #7, ne
1367 #-------------------------------------------------------------------------------
1368 # Floating-point conditional compare
1369 #-------------------------------------------------------------------------------
1371 # CHECK: fcsel s3, s20, s9, pl
1372 # CHECK: fcsel d9, d10, d11, mi
1376 #------------------------------------------------------------------------------
1377 # Floating-point data-processing (1 source)
1378 #------------------------------------------------------------------------------
1380 # CHECK: fmov s0, s1
1381 # CHECK: fabs s2, s3
1382 # CHECK: fneg s4, s5
1383 # CHECK: fsqrt s6, s7
1384 # CHECK: fcvt d8, s9
1385 # CHECK: fcvt h10, s11
1386 # CHECK: frintn s12, s13
1387 # CHECK: frintp s14, s15
1388 # CHECK: frintm s16, s17
1389 # CHECK: frintz s18, s19
1390 # CHECK: frinta s20, s21
1391 # CHECK: frintx s22, s23
1392 # CHECK: frinti s24, s25
1407 # CHECK: fmov d0, d1
1408 # CHECK: fabs d2, d3
1409 # CHECK: fneg d4, d5
1410 # CHECK: fsqrt d6, d7
1411 # CHECK: fcvt s8, d9
1412 # CHECK: fcvt h10, d11
1413 # CHECK: frintn d12, d13
1414 # CHECK: frintp d14, d15
1415 # CHECK: frintm d16, d17
1416 # CHECK: frintz d18, d19
1417 # CHECK: frinta d20, d21
1418 # CHECK: frintx d22, d23
1419 # CHECK: frinti d24, d25
1434 # CHECK: fcvt s26, h27
1435 # CHECK: fcvt d28, h29
1439 #------------------------------------------------------------------------------
1440 # Floating-point data-processing (2 sources)
1441 #------------------------------------------------------------------------------
1443 # CHECK: fmul s20, s19, s17
1444 # CHECK: fdiv s1, s2, s3
1445 # CHECK: fadd s4, s5, s6
1446 # CHECK: fsub s7, s8, s9
1447 # CHECK: fmax s10, s11, s12
1448 # CHECK: fmin s13, s14, s15
1449 # CHECK: fmaxnm s16, s17, s18
1450 # CHECK: fminnm s19, s20, s21
1451 # CHECK: fnmul s22, s23, s2
1463 # CHECK: fmul d20, d19, d17
1464 # CHECK: fdiv d1, d2, d3
1465 # CHECK: fadd d4, d5, d6
1466 # CHECK: fsub d7, d8, d9
1467 # CHECK: fmax d10, d11, d12
1468 # CHECK: fmin d13, d14, d15
1469 # CHECK: fmaxnm d16, d17, d18
1470 # CHECK: fminnm d19, d20, d21
1471 # CHECK: fnmul d22, d23, d24
1482 #------------------------------------------------------------------------------
1483 # Floating-point data-processing (1 source)
1484 #------------------------------------------------------------------------------
1486 # CHECK: fmadd s3, s5, s6, s31
1487 # CHECK: fmadd d3, d13, d0, d23
1488 # CHECK: fmsub s3, s5, s6, s31
1489 # CHECK: fmsub d3, d13, d0, d23
1490 # CHECK: fnmadd s3, s5, s6, s31
1491 # CHECK: fnmadd d3, d13, d0, d23
1492 # CHECK: fnmsub s3, s5, s6, s31
1493 # CHECK: fnmsub d3, d13, d0, d23
1503 #------------------------------------------------------------------------------
1504 # Floating-point <-> fixed-point conversion
1505 #------------------------------------------------------------------------------
1507 # FP16: fcvtzs w3, h5, #1
1508 # FP16: fcvtzs wzr, h20, #13
1509 # FP16: fcvtzs w19, h0, #32
1514 # FP16: fcvtzs x3, h5, #1
1515 # FP16: fcvtzs x12, h30, #45
1516 # FP16: fcvtzs x19, h0, #64
1521 # CHECK: fcvtzs w3, s5, #1
1522 # CHECK: fcvtzs wzr, s20, #13
1523 # CHECK: fcvtzs w19, s0, #32
1528 # CHECK: fcvtzs x3, s5, #1
1529 # CHECK: fcvtzs x12, s30, #45
1530 # CHECK: fcvtzs x19, s0, #64
1535 # CHECK: fcvtzs w3, d5, #1
1536 # CHECK: fcvtzs wzr, d20, #13
1537 # CHECK: fcvtzs w19, d0, #32
1542 # CHECK: fcvtzs x3, d5, #1
1543 # CHECK: fcvtzs x12, d30, #45
1544 # CHECK: fcvtzs x19, d0, #64
1549 # FP16: fcvtzu w3, h5, #1
1550 # FP16: fcvtzu wzr, h20, #13
1551 # FP16: fcvtzu w19, h0, #32
1556 # FP16: fcvtzu x3, h5, #1
1557 # FP16: fcvtzu x12, h30, #45
1558 # FP16: fcvtzu x19, h0, #64
1563 # CHECK: fcvtzu w3, s5, #1
1564 # CHECK: fcvtzu wzr, s20, #13
1565 # CHECK: fcvtzu w19, s0, #32
1570 # CHECK: fcvtzu x3, s5, #1
1571 # CHECK: fcvtzu x12, s30, #45
1572 # CHECK: fcvtzu x19, s0, #64
1577 # CHECK: fcvtzu w3, d5, #1
1578 # CHECK: fcvtzu wzr, d20, #13
1579 # CHECK: fcvtzu w19, d0, #32
1584 # CHECK: fcvtzu x3, d5, #1
1585 # CHECK: fcvtzu x12, d30, #45
1586 # CHECK: fcvtzu x19, d0, #64
1591 # FP16: scvtf h23, w19, #1
1592 # FP16: scvtf h31, wzr, #20
1593 # FP16: scvtf h14, w0, #32
1598 # FP16: scvtf h23, x19, #1
1599 # FP16: scvtf h31, xzr, #20
1600 # FP16: scvtf h14, x0, #64
1605 # CHECK: scvtf s23, w19, #1
1606 # CHECK: scvtf s31, wzr, #20
1607 # CHECK: scvtf s14, w0, #32
1612 # CHECK: scvtf s23, x19, #1
1613 # CHECK: scvtf s31, xzr, #20
1614 # CHECK: scvtf s14, x0, #64
1619 # CHECK: scvtf d23, w19, #1
1620 # CHECK: scvtf d31, wzr, #20
1621 # CHECK: scvtf d14, w0, #32
1626 # CHECK: scvtf d23, x19, #1
1627 # CHECK: scvtf d31, xzr, #20
1628 # CHECK: scvtf d14, x0, #64
1633 # FP16: ucvtf h23, w19, #1
1634 # FP16: ucvtf h31, wzr, #20
1635 # FP16: ucvtf h14, w0, #32
1640 # FP16: ucvtf h23, x19, #1
1641 # FP16: ucvtf h31, xzr, #20
1642 # FP16: ucvtf h14, x0, #64
1647 # CHECK: ucvtf s23, w19, #1
1648 # CHECK: ucvtf s31, wzr, #20
1649 # CHECK: ucvtf s14, w0, #32
1654 # CHECK: ucvtf s23, x19, #1
1655 # CHECK: ucvtf s31, xzr, #20
1656 # CHECK: ucvtf s14, x0, #64
1661 # CHECK: ucvtf d23, w19, #1
1662 # CHECK: ucvtf d31, wzr, #20
1663 # CHECK: ucvtf d14, w0, #32
1668 # CHECK: ucvtf d23, x19, #1
1669 # CHECK: ucvtf d31, xzr, #20
1670 # CHECK: ucvtf d14, x0, #64
1675 #------------------------------------------------------------------------------
1676 # Floating-point <-> integer conversion
1677 #------------------------------------------------------------------------------
1679 # FP16: fcvtns w3, h31
1680 # FP16: fcvtns xzr, h12
1681 # FP16: fcvtnu wzr, h12
1682 # FP16: fcvtnu x0, h0
1688 # FP16: fcvtps wzr, h9
1689 # FP16: fcvtps x12, h20
1690 # FP16: fcvtpu w30, h23
1691 # FP16: fcvtpu x29, h3
1697 # FP16: fcvtms w2, h3
1698 # FP16: fcvtms x4, h5
1699 # FP16: fcvtmu w6, h7
1700 # FP16: fcvtmu x8, h9
1706 # FP16: fcvtzs w10, h11
1707 # FP16: fcvtzs x12, h13
1708 # FP16: fcvtzu w14, h15
1709 # FP16: fcvtzu x15, h16
1715 # FP16: scvtf h17, w18
1716 # FP16: scvtf h19, x20
1717 # FP16: ucvtf h21, w22
1718 # FP16: scvtf h23, x24
1724 # FP16: fcvtas w25, h26
1725 # FP16: fcvtas x27, h28
1726 # FP16: fcvtau w29, h30
1727 # FP16: fcvtau xzr, h0
1733 # CHECK: fcvtns w3, s31
1734 # CHECK: fcvtns xzr, s12
1735 # CHECK: fcvtnu wzr, s12
1736 # CHECK: fcvtnu x0, s0
1742 # CHECK: fcvtps wzr, s9
1743 # CHECK: fcvtps x12, s20
1744 # CHECK: fcvtpu w30, s23
1745 # CHECK: fcvtpu x29, s3
1751 # CHECK: fcvtms w2, s3
1752 # CHECK: fcvtms x4, s5
1753 # CHECK: fcvtmu w6, s7
1754 # CHECK: fcvtmu x8, s9
1760 # CHECK: fcvtzs w10, s11
1761 # CHECK: fcvtzs x12, s13
1762 # CHECK: fcvtzu w14, s15
1763 # CHECK: fcvtzu x15, s16
1769 # CHECK: scvtf s17, w18
1770 # CHECK: scvtf s19, x20
1771 # CHECK: ucvtf s21, w22
1772 # CHECK: scvtf s23, x24
1778 # CHECK: fcvtas w25, s26
1779 # CHECK: fcvtas x27, s28
1780 # CHECK: fcvtau w29, s30
1781 # CHECK: fcvtau xzr, s0
1787 # CHECK: fcvtns w3, d31
1788 # CHECK: fcvtns xzr, d12
1789 # CHECK: fcvtnu wzr, d12
1790 # CHECK: fcvtnu x0, d0
1796 # CHECK: fcvtps wzr, d9
1797 # CHECK: fcvtps x12, d20
1798 # CHECK: fcvtpu w30, d23
1799 # CHECK: fcvtpu x29, d3
1805 # CHECK: fcvtms w2, d3
1806 # CHECK: fcvtms x4, d5
1807 # CHECK: fcvtmu w6, d7
1808 # CHECK: fcvtmu x8, d9
1814 # CHECK: fcvtzs w10, d11
1815 # CHECK: fcvtzs x12, d13
1816 # CHECK: fcvtzu w14, d15
1817 # CHECK: fcvtzu x15, d16
1823 # CHECK: scvtf d17, w18
1824 # CHECK: scvtf d19, x20
1825 # CHECK: ucvtf d21, w22
1826 # CHECK: ucvtf d23, x24
1832 # CHECK: fcvtas w25, d26
1833 # CHECK: fcvtas x27, d28
1834 # CHECK: fcvtau w29, d30
1835 # CHECK: fcvtau xzr, d0
1841 # CHECK: fmov w3, s9
1842 # CHECK: fmov s9, w3
1846 # CHECK: fmov x20, d31
1847 # CHECK: fmov d1, x15
1851 # CHECK: fmov x3, v12.d[1]
1852 # CHECK: fmov v1.d[1], x19
1856 #------------------------------------------------------------------------------
1857 # Floating-point immediate
1858 #------------------------------------------------------------------------------
1860 # CHECK: fmov s2, #0.12500000
1861 # CHECK: fmov s3, #1.00000000
1862 # CHECK: fmov d30, #16.00000000
1867 # CHECK: fmov s4, #1.06250000
1868 # CHECK: fmov d10, #1.93750000
1872 # CHECK: fmov s12, #-1.00000000
1875 # CHECK: fmov d16, #8.50000000
1878 #------------------------------------------------------------------------------
1879 # Load-register (literal)
1880 #------------------------------------------------------------------------------
1883 # CHECK: ldr x29, #4
1884 # CHECK: ldrsw xzr, #-4
1890 # CHECK: ldr d0, #1048572
1891 # CHECK: ldr q0, #-1048576
1896 # CHECK: prfm pldl1strm, #0
1897 # CHECK: prfm #22, #0
1901 #------------------------------------------------------------------------------
1902 # Load/store exclusive
1903 #------------------------------------------------------------------------------
1905 #CHECK: stxrb w18, w8, [sp]
1906 #CHECK: stxrh w24, w15, [x16]
1907 #CHECK: stxr w5, w6, [x17]
1908 #CHECK: stxr w1, x10, [x21]
1909 #CHECK: stxr w1, x10, [x21]
1916 #CHECK: ldxrb w30, [x0]
1917 #CHECK: ldxrh w17, [x4]
1918 #CHECK: ldxr w22, [sp]
1919 #CHECK: ldxr x11, [x29]
1920 #CHECK: ldxr x11, [x29]
1921 #CHECK: ldxr x11, [x29]
1929 #CHECK: stxp w12, w11, w10, [sp]
1930 #CHECK: stxp wzr, x27, x9, [x12]
1934 #CHECK: ldxp w0, wzr, [sp]
1935 #CHECK: ldxp x17, x0, [x18]
1936 #CHECK: ldxp x17, x0, [x18]
1941 #CHECK: stlxrb w12, w22, [x0]
1942 #CHECK: stlxrh w10, w1, [x1]
1943 #CHECK: stlxr w9, w2, [x2]
1944 #CHECK: stlxr w9, x3, [sp]
1951 #CHECK: ldaxrb w8, [x4]
1952 #CHECK: ldaxrh w7, [x5]
1953 #CHECK: ldaxr w6, [sp]
1954 #CHECK: ldaxr x5, [x6]
1955 #CHECK: ldaxr x5, [x6]
1956 #CHECK: ldaxr x5, [x6]
1964 #CHECK: stlxp w4, w5, w6, [sp]
1965 #CHECK: stlxp wzr, x6, x7, [x1]
1969 #CHECK: ldaxp w5, w18, [sp]
1970 #CHECK: ldaxp x6, x19, [x22]
1971 #CHECK: ldaxp x6, x19, [x22]
1976 #CHECK: stlrb w24, [sp]
1977 #CHECK: stlrh w25, [x30]
1978 #CHECK: stlr w26, [x29]
1979 #CHECK: stlr x27, [x28]
1980 #CHECK: stlr x27, [x28]
1981 #CHECK: stlr x27, [x28]
1989 #CHECK: ldarb w23, [sp]
1990 #CHECK: ldarh w22, [x30]
1991 #CHECK: ldar wzr, [x29]
1992 #CHECK: ldar x21, [x28]
1993 #CHECK: ldar x21, [x28]
1994 #CHECK: ldar x21, [x28]
2002 #------------------------------------------------------------------------------
2003 # Load/store (unscaled immediate)
2004 #------------------------------------------------------------------------------
2006 # CHECK: sturb w9, [sp]
2007 # CHECK: sturh wzr, [x12, #255]
2008 # CHECK: stur w16, [x0, #-256]
2009 # CHECK: stur x28, [x14, #1]
2015 # CHECK: ldurb w1, [x20, #255]
2016 # CHECK: ldurh w20, [x1, #255]
2017 # CHECK: ldur w12, [sp, #255]
2018 # CHECK: ldur xzr, [x12, #255]
2024 # CHECK: ldursb x9, [x7, #-256]
2025 # CHECK: ldursh x17, [x19, #-256]
2026 # CHECK: ldursw x20, [x15, #-256]
2027 # CHECK: prfum pldl2keep, [sp, #-256]
2028 # CHECK: ldursb w19, [x1, #-256]
2029 # CHECK: ldursh w15, [x21, #-256]
2037 # CHECK: stur b0, [sp, #1]
2038 # CHECK: stur h12, [x12, #-1]
2039 # CHECK: stur s15, [x0, #255]
2040 # CHECK: stur d31, [x5, #25]
2041 # CHECK: stur q9, [x5]
2048 # CHECK: ldur b3, [sp]
2049 # CHECK: ldur h5, [x4, #-256]
2050 # CHECK: ldur s7, [x12, #-1]
2051 # CHECK: ldur d11, [x19, #4]
2052 # CHECK: ldur q13, [x1, #2]
2059 #------------------------------------------------------------------------------
2060 # Load/store (immediate post-indexed)
2061 #------------------------------------------------------------------------------
2063 # E.g. "str xzr, [sp], #4" is *not* unpredictable
2064 # CHECK-NOT: warning: potentially undefined instruction encoding
2067 # CHECK: strb w9, [x2], #255
2068 # CHECK: strb w10, [x3], #1
2069 # CHECK: strb w10, [x3], #-256
2070 # CHECK: strh w9, [x2], #255
2071 # CHECK: strh w9, [x2], #1
2072 # CHECK: strh w10, [x3], #-256
2080 # CHECK: str w19, [sp], #255
2081 # CHECK: str w20, [x30], #1
2082 # CHECK: str w21, [x12], #-256
2083 # CHECK: str xzr, [x9], #255
2084 # CHECK: str x2, [x3], #1
2085 # CHECK: str x19, [x12], #-256
2093 # CHECK: ldrb w9, [x2], #255
2094 # CHECK: ldrb w10, [x3], #1
2095 # CHECK: ldrb w10, [x3], #-256
2096 # CHECK: ldrh w9, [x2], #255
2097 # CHECK: ldrh w9, [x2], #1
2098 # CHECK: ldrh w10, [x3], #-256
2106 # CHECK: ldr w19, [sp], #255
2107 # CHECK: ldr w20, [x30], #1
2108 # CHECK: ldr w21, [x12], #-256
2109 # CHECK: ldr xzr, [x9], #255
2110 # CHECK: ldr x2, [x3], #1
2111 # CHECK: ldr x19, [x12], #-256
2119 # CHECK: ldrsb xzr, [x9], #255
2120 # CHECK: ldrsb x2, [x3], #1
2121 # CHECK: ldrsb x19, [x12], #-256
2122 # CHECK: ldrsh xzr, [x9], #255
2123 # CHECK: ldrsh x2, [x3], #1
2124 # CHECK: ldrsh x19, [x12], #-256
2125 # CHECK: ldrsw xzr, [x9], #255
2126 # CHECK: ldrsw x2, [x3], #1
2127 # CHECK: ldrsw x19, [x12], #-256
2138 # CHECK: ldrsb wzr, [x9], #255
2139 # CHECK: ldrsb w2, [x3], #1
2140 # CHECK: ldrsb w19, [x12], #-256
2141 # CHECK: ldrsh wzr, [x9], #255
2142 # CHECK: ldrsh w2, [x3], #1
2143 # CHECK: ldrsh w19, [x12], #-256
2151 # CHECK: str b0, [x0], #255
2152 # CHECK: str b3, [x3], #1
2153 # CHECK: str b5, [sp], #-256
2154 # CHECK: str h10, [x10], #255
2155 # CHECK: str h13, [x23], #1
2156 # CHECK: str h15, [sp], #-256
2157 # CHECK: str s20, [x20], #255
2158 # CHECK: str s23, [x23], #1
2159 # CHECK: str s25, [x0], #-256
2160 # CHECK: str d20, [x20], #255
2161 # CHECK: str d23, [x23], #1
2162 # CHECK: str d25, [x0], #-256
2176 # CHECK: ldr b0, [x0], #255
2177 # CHECK: ldr b3, [x3], #1
2178 # CHECK: ldr b5, [sp], #-256
2179 # CHECK: ldr h10, [x10], #255
2180 # CHECK: ldr h13, [x23], #1
2181 # CHECK: ldr h15, [sp], #-256
2182 # CHECK: ldr s20, [x20], #255
2183 # CHECK: ldr s23, [x23], #1
2184 # CHECK: ldr s25, [x0], #-256
2185 # CHECK: ldr d20, [x20], #255
2186 # CHECK: ldr d23, [x23], #1
2187 # CHECK: ldr d25, [x0], #-256
2202 # CHECK: ldr q20, [x1], #255
2203 # CHECK: ldr q23, [x9], #1
2204 # CHECK: ldr q25, [x20], #-256
2205 # CHECK: str q10, [x1], #255
2206 # CHECK: str q22, [sp], #1
2207 # CHECK: str q21, [x20], #-256
2214 #-------------------------------------------------------------------------------
2215 # Load-store register (immediate pre-indexed)
2216 #-------------------------------------------------------------------------------
2218 # E.g. "str xzr, [sp, #4]!" is *not* unpredictable
2219 # CHECK-NOT: warning: potentially undefined instruction encoding
2222 # CHECK: ldr x3, [x4, #0]!
2225 # CHECK: strb w9, [x2, #255]!
2226 # CHECK: strb w10, [x3, #1]!
2227 # CHECK: strb w10, [x3, #-256]!
2228 # CHECK: strh w9, [x2, #255]!
2229 # CHECK: strh w9, [x2, #1]!
2230 # CHECK: strh w10, [x3, #-256]!
2238 # CHECK: str w19, [sp, #255]!
2239 # CHECK: str w20, [x30, #1]!
2240 # CHECK: str w21, [x12, #-256]!
2241 # CHECK: str xzr, [x9, #255]!
2242 # CHECK: str x2, [x3, #1]!
2243 # CHECK: str x19, [x12, #-256]!
2251 # CHECK: ldrb w9, [x2, #255]!
2252 # CHECK: ldrb w10, [x3, #1]!
2253 # CHECK: ldrb w10, [x3, #-256]!
2254 # CHECK: ldrh w9, [x2, #255]!
2255 # CHECK: ldrh w9, [x2, #1]!
2256 # CHECK: ldrh w10, [x3, #-256]!
2264 # CHECK: ldr w19, [sp, #255]!
2265 # CHECK: ldr w20, [x30, #1]!
2266 # CHECK: ldr w21, [x12, #-256]!
2267 # CHECK: ldr xzr, [x9, #255]!
2268 # CHECK: ldr x2, [x3, #1]!
2269 # CHECK: ldr x19, [x12, #-256]!
2277 # CHECK: ldrsb xzr, [x9, #255]!
2278 # CHECK: ldrsb x2, [x3, #1]!
2279 # CHECK: ldrsb x19, [x12, #-256]!
2280 # CHECK: ldrsh xzr, [x9, #255]!
2281 # CHECK: ldrsh x2, [x3, #1]!
2282 # CHECK: ldrsh x19, [x12, #-256]!
2283 # CHECK: ldrsw xzr, [x9, #255]!
2284 # CHECK: ldrsw x2, [x3, #1]!
2285 # CHECK: ldrsw x19, [x12, #-256]!
2296 # CHECK: ldrsb wzr, [x9, #255]!
2297 # CHECK: ldrsb w2, [x3, #1]!
2298 # CHECK: ldrsb w19, [x12, #-256]!
2299 # CHECK: ldrsh wzr, [x9, #255]!
2300 # CHECK: ldrsh w2, [x3, #1]!
2301 # CHECK: ldrsh w19, [x12, #-256]!
2309 # CHECK: str b0, [x0, #255]!
2310 # CHECK: str b3, [x3, #1]!
2311 # CHECK: str b5, [sp, #-256]!
2312 # CHECK: str h10, [x10, #255]!
2313 # CHECK: str h13, [x23, #1]!
2314 # CHECK: str h15, [sp, #-256]!
2315 # CHECK: str s20, [x20, #255]!
2316 # CHECK: str s23, [x23, #1]!
2317 # CHECK: str s25, [x0, #-256]!
2318 # CHECK: str d20, [x20, #255]!
2319 # CHECK: str d23, [x23, #1]!
2320 # CHECK: str d25, [x0, #-256]!
2334 # CHECK: ldr b0, [x0, #255]!
2335 # CHECK: ldr b3, [x3, #1]!
2336 # CHECK: ldr b5, [sp, #-256]!
2337 # CHECK: ldr h10, [x10, #255]!
2338 # CHECK: ldr h13, [x23, #1]!
2339 # CHECK: ldr h15, [sp, #-256]!
2340 # CHECK: ldr s20, [x20, #255]!
2341 # CHECK: ldr s23, [x23, #1]!
2342 # CHECK: ldr s25, [x0, #-256]!
2343 # CHECK: ldr d20, [x20, #255]!
2344 # CHECK: ldr d23, [x23, #1]!
2345 # CHECK: ldr d25, [x0, #-256]!
2359 # CHECK: ldr q20, [x1, #255]!
2360 # CHECK: ldr q23, [x9, #1]!
2361 # CHECK: ldr q25, [x20, #-256]!
2362 # CHECK: str q10, [x1, #255]!
2363 # CHECK: str q22, [sp, #1]!
2364 # CHECK: str q21, [x20, #-256]!
2372 #------------------------------------------------------------------------------
2373 # Load/store (unprivileged)
2374 #------------------------------------------------------------------------------
2376 # CHECK: sttrb w9, [sp]
2377 # CHECK: sttrh wzr, [x12, #255]
2378 # CHECK: sttr w16, [x0, #-256]
2379 # CHECK: sttr x28, [x14, #1]
2385 # CHECK: ldtrb w1, [x20, #255]
2386 # CHECK: ldtrh w20, [x1, #255]
2387 # CHECK: ldtr w12, [sp, #255]
2388 # CHECK: ldtr xzr, [x12, #255]
2394 # CHECK: ldtrsb x9, [x7, #-256]
2395 # CHECK: ldtrsh x17, [x19, #-256]
2396 # CHECK: ldtrsw x20, [x15, #-256]
2397 # CHECK: ldtrsb w19, [x1, #-256]
2398 # CHECK: ldtrsh w15, [x21, #-256]
2405 #------------------------------------------------------------------------------
2406 # Load/store (unsigned immediate)
2407 #------------------------------------------------------------------------------
2409 # CHECK: ldr x0, [x0]
2410 # CHECK: ldr x4, [x29]
2411 # CHECK: ldr x30, [x12, #32760]
2412 # CHECK: ldr x20, [sp, #8]
2418 # CHECK: ldr xzr, [sp]
2421 # CHECK: ldr w2, [sp]
2422 # CHECK: ldr w17, [sp, #16380]
2423 # CHECK: ldr w13, [x2, #4]
2428 # CHECK: ldrsw x2, [x5, #4]
2429 # CHECK: ldrsw x23, [sp, #16380]
2433 # CHECK: ldrh w2, [x4]
2434 # CHECK: ldrsh w23, [x6, #8190]
2435 # CHECK: ldrsh wzr, [sp, #2]
2436 # CHECK: ldrsh x29, [x2, #2]
2442 # CHECK: ldrb w26, [x3, #121]
2443 # CHECK: ldrb w12, [x2]
2444 # CHECK: ldrsb w27, [sp, #4095]
2445 # CHECK: ldrsb xzr, [x15]
2451 # CHECK: str x30, [sp]
2452 # CHECK: str w20, [x4, #16380]
2453 # CHECK: strh w20, [x10, #14]
2454 # CHECK: strh w17, [sp, #8190]
2455 # CHECK: strb w23, [x3, #4095]
2456 # CHECK: strb wzr, [x2]
2464 # CHECK: ldr b31, [sp, #4095]
2465 # CHECK: ldr h20, [x2, #8190]
2466 # CHECK: ldr s10, [x19, #16380]
2467 # CHECK: ldr d3, [x10, #32760]
2468 # CHECK: str q12, [sp, #65520]
2475 # CHECK: prfm pldl1keep, [sp, #8]
2476 # CHECK: prfm pldl1strm, [x3{{(, #0)?}}]
2477 # CHECK: prfm pldl2keep, [x5, #16]
2478 # CHECK: prfm pldl2strm, [x2{{(, #0)?}}]
2479 # CHECK: prfm pldl3keep, [x5{{(, #0)?}}]
2480 # CHECK: prfm pldl3strm, [x6{{(, #0)?}}]
2481 # CHECK: prfm plil1keep, [sp, #8]
2482 # CHECK: prfm plil1strm, [x3{{(, #0)?}}]
2483 # CHECK: prfm plil2keep, [x5, #16]
2484 # CHECK: prfm plil2strm, [x2{{(, #0)?}}]
2485 # CHECK: prfm plil3keep, [x5{{(, #0)?}}]
2486 # CHECK: prfm plil3strm, [x6{{(, #0)?}}]
2487 # CHECK: prfm pstl1keep, [sp, #8]
2488 # CHECK: prfm pstl1strm, [x3{{(, #0)?}}]
2489 # CHECK: prfm pstl2keep, [x5, #16]
2490 # CHECK: prfm pstl2strm, [x2{{(, #0)?}}]
2491 # CHECK: prfm pstl3keep, [x5{{(, #0)?}}]
2492 # CHECK: prfm pstl3strm, [x6{{(, #0)?}}]
2513 #------------------------------------------------------------------------------
2514 # Load/store (register offset)
2515 #------------------------------------------------------------------------------
2517 # CHECK: ldrb w3, [sp, x5]
2518 # CHECK: ldrb w9, [x27, x6]
2519 # CHECK: ldrsb w10, [x30, x7]
2520 # CHECK: ldrb w11, [x29, x3, sxtx]
2521 # CHECK: strb w12, [x28, xzr, sxtx]
2522 # CHECK: ldrb w14, [x26, w6, uxtw]
2523 # CHECK: ldrsb w15, [x25, w7, uxtw]
2524 # CHECK: ldrb w17, [x23, w9, sxtw]
2525 # CHECK: ldrsb x18, [x22, w10, sxtw]
2536 # CHECK: ldrsh w3, [sp, x5]
2537 # CHECK: ldrsh w9, [x27, x6]
2538 # CHECK: ldrh w10, [x30, x7, lsl #1]
2539 # CHECK: strh w11, [x29, x3, sxtx]
2540 # CHECK: ldrh w12, [x28, xzr, sxtx]
2541 # CHECK: ldrsh x13, [x27, x5, sxtx #1]
2542 # CHECK: ldrh w14, [x26, w6, uxtw]
2543 # CHECK: ldrh w15, [x25, w7, uxtw]
2544 # CHECK: ldrsh w16, [x24, w8, uxtw #1]
2545 # CHECK: ldrh w17, [x23, w9, sxtw]
2546 # CHECK: ldrh w18, [x22, w10, sxtw]
2547 # CHECK: strh w19, [x21, wzr, sxtw #1]
2561 # CHECK: ldr w3, [sp, x5]
2562 # CHECK: ldr s9, [x27, x6]
2563 # CHECK: ldr w10, [x30, x7, lsl #2]
2564 # CHECK: ldr w11, [x29, x3, sxtx]
2565 # CHECK: str s12, [x28, xzr, sxtx]
2566 # CHECK: str w13, [x27, x5, sxtx #2]
2567 # CHECK: str w14, [x26, w6, uxtw]
2568 # CHECK: ldr w15, [x25, w7, uxtw]
2569 # CHECK: ldr w16, [x24, w8, uxtw #2]
2570 # CHECK: ldrsw x17, [x23, w9, sxtw]
2571 # CHECK: ldr w18, [x22, w10, sxtw]
2572 # CHECK: ldrsw x19, [x21, wzr, sxtw #2]
2586 # CHECK: ldr x3, [sp, x5]
2587 # CHECK: str x9, [x27, x6]
2588 # CHECK: ldr d10, [x30, x7, lsl #3]
2589 # CHECK: str x11, [x29, x3, sxtx]
2590 # CHECK: ldr x12, [x28, xzr, sxtx]
2591 # CHECK: ldr x13, [x27, x5, sxtx #3]
2592 # CHECK: prfm pldl1keep, [x26, w6, uxtw]
2593 # CHECK: ldr x15, [x25, w7, uxtw]
2594 # CHECK: ldr x16, [x24, w8, uxtw #3]
2595 # CHECK: ldr x17, [x23, w9, sxtw]
2596 # CHECK: ldr x18, [x22, w10, sxtw]
2597 # CHECK: str d19, [x21, wzr, sxtw #3]
2611 # CHECK: ldr q3, [sp, x5]
2612 # CHECK: ldr q9, [x27, x6]
2613 # CHECK: ldr q10, [x30, x7, lsl #4]
2614 # CHECK: str q11, [x29, x3, sxtx]
2615 # CHECK: str q12, [x28, xzr, sxtx]
2616 # CHECK: str q13, [x27, x5, sxtx #4]
2617 # CHECK: ldr q14, [x26, w6, uxtw]
2618 # CHECK: ldr q15, [x25, w7, uxtw]
2619 # CHECK: ldr q16, [x24, w8, uxtw #4]
2620 # CHECK: ldr q17, [x23, w9, sxtw]
2621 # CHECK: str q18, [x22, w10, sxtw]
2622 # CHECK: ldr q19, [x21, wzr, sxtw #4]
2636 #------------------------------------------------------------------------------
2637 # Load/store register pair (offset)
2638 #------------------------------------------------------------------------------
2640 # CHECK: ldp w3, w5, [sp]
2641 # CHECK: stp wzr, w9, [sp, #252]
2642 # CHECK: ldp w2, wzr, [sp, #-256]
2643 # CHECK: ldp w9, w10, [sp, #4]
2649 # CHECK: ldpsw x9, x10, [sp, #4]
2650 # CHECK: ldpsw x9, x10, [x2, #-256]
2651 # CHECK: ldpsw x20, x30, [sp, #252]
2656 # CHECK: ldp x21, x29, [x2, #504]
2657 # CHECK: ldp x22, x23, [x3, #-512]
2658 # CHECK: ldp x24, x25, [x4, #8]
2663 # CHECK: ldp s29, s28, [sp, #252]
2664 # CHECK: stp s27, s26, [sp, #-256]
2665 # CHECK: ldp s1, s2, [x3, #44]
2670 # CHECK: stp d3, d5, [x9, #504]
2671 # CHECK: stp d7, d11, [x10, #-512]
2672 # CHECK: ldp d2, d3, [x30, #-8]
2677 # CHECK: stp q3, q5, [sp]
2678 # CHECK: stp q17, q19, [sp, #1008]
2679 # CHECK: ldp q23, q29, [x1, #-1024]
2684 #------------------------------------------------------------------------------
2685 # Load/store register pair (post-indexed)
2686 #------------------------------------------------------------------------------
2688 # CHECK: ldp w3, w5, [sp], #0
2689 # CHECK: stp wzr, w9, [sp], #252
2690 # CHECK: ldp w2, wzr, [sp], #-256
2691 # CHECK: ldp w9, w10, [sp], #4
2697 # CHECK: ldpsw x9, x10, [sp], #4
2698 # CHECK: ldpsw x9, x10, [x2], #-256
2699 # CHECK: ldpsw x20, x30, [sp], #252
2704 # CHECK: ldp x21, x29, [x2], #504
2705 # CHECK: ldp x22, x23, [x3], #-512
2706 # CHECK: ldp x24, x25, [x4], #8
2711 # CHECK: ldp s29, s28, [sp], #252
2712 # CHECK: stp s27, s26, [sp], #-256
2713 # CHECK: ldp s1, s2, [x3], #44
2718 # CHECK: stp d3, d5, [x9], #504
2719 # CHECK: stp d7, d11, [x10], #-512
2720 # CHECK: ldp d2, d3, [x30], #-8
2725 # CHECK: stp q3, q5, [sp], #0
2726 # CHECK: stp q17, q19, [sp], #1008
2727 # CHECK: ldp q23, q29, [x1], #-1024
2732 #------------------------------------------------------------------------------
2733 # Load/store register pair (pre-indexed)
2734 #------------------------------------------------------------------------------
2736 # CHECK: ldp w3, w5, [sp, #0]!
2737 # CHECK: stp wzr, w9, [sp, #252]!
2738 # CHECK: ldp w2, wzr, [sp, #-256]!
2739 # CHECK: ldp w9, w10, [sp, #4]!
2745 # CHECK: ldpsw x9, x10, [sp, #4]!
2746 # CHECK: ldpsw x9, x10, [x2, #-256]!
2747 # CHECK: ldpsw x20, x30, [sp, #252]!
2752 # CHECK: ldp x21, x29, [x2, #504]!
2753 # CHECK: ldp x22, x23, [x3, #-512]!
2754 # CHECK: ldp x24, x25, [x4, #8]!
2759 # CHECK: ldp s29, s28, [sp, #252]!
2760 # CHECK: stp s27, s26, [sp, #-256]!
2761 # CHECK: ldp s1, s2, [x3, #44]!
2766 # CHECK: stp d3, d5, [x9, #504]!
2767 # CHECK: stp d7, d11, [x10, #-512]!
2768 # CHECK: ldp d2, d3, [x30, #-8]!
2773 # CHECK: stp q3, q5, [sp, #0]!
2774 # CHECK: stp q17, q19, [sp, #1008]!
2775 # CHECK: ldp q23, q29, [x1, #-1024]!
2780 #------------------------------------------------------------------------------
2781 # Load/store register pair (offset)
2782 #------------------------------------------------------------------------------
2784 # CHECK: ldnp w3, w5, [sp]
2785 # CHECK: stnp wzr, w9, [sp, #252]
2786 # CHECK: ldnp w2, wzr, [sp, #-256]
2787 # CHECK: ldnp w9, w10, [sp, #4]
2793 # CHECK: ldnp x21, x29, [x2, #504]
2794 # CHECK: ldnp x22, x23, [x3, #-512]
2795 # CHECK: ldnp x24, x25, [x4, #8]
2800 # CHECK: ldnp s29, s28, [sp, #252]
2801 # CHECK: stnp s27, s26, [sp, #-256]
2802 # CHECK: ldnp s1, s2, [x3, #44]
2807 # CHECK: stnp d3, d5, [x9, #504]
2808 # CHECK: stnp d7, d11, [x10, #-512]
2809 # CHECK: ldnp d2, d3, [x30, #-8]
2814 # CHECK: stnp q3, q5, [sp]
2815 # CHECK: stnp q17, q19, [sp, #1008]
2816 # CHECK: ldnp q23, q29, [x1, #-1024]
2821 #------------------------------------------------------------------------------
2822 # Logical (immediate)
2823 #------------------------------------------------------------------------------
2824 # CHECK: orr w3, w9, #0xffff0000
2825 # CHECK: orr wsp, w10, #0xe00000ff
2826 # CHECK: orr w9, w10, #0x3ff
2831 # CHECK: and w14, w15, #0x80008000
2832 # CHECK: and w12, w13, #0xffc3ffc3
2833 # CHECK: and w11, wzr, #0x30003
2838 # CHECK: eor w3, w6, #0xe0e0e0e0
2839 # CHECK: eor wsp, wzr, #0x3030303
2840 # CHECK: eor w16, w17, #0x81818181
2845 # CHECK: {{ands wzr,|tst}} w18, #0xcccccccc
2846 # CHECK: ands w19, w20, #0x33333333
2847 # CHECK: ands w21, w22, #0x99999999
2852 # CHECK: {{ands wzr,|tst}} w3, #0xaaaaaaaa
2853 # CHECK: {{ands wzr,|tst}} wzr, #0x55555555
2857 # CHECK: eor x3, x5, #0xffffffffc000000
2858 # CHECK: and x9, x10, #0x7fffffffffff
2859 # CHECK: orr x11, x12, #0x8000000000000fff
2864 # CHECK: orr x3, x9, #0xffff0000ffff0000
2865 # CHECK: orr sp, x10, #0xe00000ffe00000ff
2866 # CHECK: orr x9, x10, #0x3ff000003ff
2871 # CHECK: and x14, x15, #0x8000800080008000
2872 # CHECK: and x12, x13, #0xffc3ffc3ffc3ffc3
2873 # CHECK: and x11, xzr, #0x3000300030003
2878 # CHECK: eor x3, x6, #0xe0e0e0e0e0e0e0e0
2879 # CHECK: eor sp, xzr, #0x303030303030303
2880 # CHECK: eor x16, x17, #0x8181818181818181
2885 # CHECK: {{ands xzr,|tst}} x18, #0xcccccccccccccccc
2886 # CHECK: ands x19, x20, #0x3333333333333333
2887 # CHECK: ands x21, x22, #0x9999999999999999
2892 # CHECK: {{ands xzr,|tst}} x3, #0xaaaaaaaaaaaaaaaa
2893 # CHECK: {{ands xzr,|tst}} xzr, #0x5555555555555555
2897 # CHECK: mov w3, #983055
2898 # CHECK: mov x10, #-6148914691236517206
2902 # CHECK: orr w3, wzr, #0xffff
2903 # CHECK: orr x9, xzr, #0xffff00000000
2907 #------------------------------------------------------------------------------
2908 # Logical (shifted register)
2909 #------------------------------------------------------------------------------
2911 # CHECK: and w12, w23, w21
2912 # CHECK: and w16, w15, w1, lsl #1
2913 # CHECK: and w9, w4, w10, lsl #31
2914 # CHECK: and w3, w30, w11
2915 # CHECK: and x3, x5, x7, lsl #63
2922 # CHECK: and x5, x14, x19, asr #4
2923 # CHECK: and w3, w17, w19, ror #31
2924 # CHECK: and w0, w2, wzr, lsr #17
2925 # CHECK: and w3, w30, w11, asr
2931 # CHECK: and xzr, x4, x26
2932 # CHECK: and w3, wzr, w20, ror
2933 # CHECK: and x7, x20, xzr, asr #63
2938 # CHECK: bic x13, x20, x14, lsl #47
2939 # CHECK: bic w2, w7, w9
2940 # CHECK: orr w2, w7, w0, asr #31
2941 # CHECK: orr x8, x9, x10, lsl #12
2942 # CHECK: orn x3, x5, x7, asr
2943 # CHECK: orn w2, w5, w29
2951 # CHECK: ands w7, wzr, w9, lsl #1
2952 # CHECK: ands x3, x5, x20, ror #63
2953 # CHECK: bics w3, w5, w7
2954 # CHECK: bics x3, xzr, x3, lsl #1
2955 # CHECK: tst w3, w7, lsl #31
2956 # CHECK: tst x2, x20, asr
2965 # CHECK: mov x3, xzr
2966 # CHECK: mov wzr, w2
2973 #------------------------------------------------------------------------------
2974 # Move wide (immediate)
2975 #------------------------------------------------------------------------------
2977 # N.b. (FIXME) canonical aliases aren't produced here because of
2978 # limitation in InstAlias. Lots of the "mov[nz]" instructions should
2981 # CHECK: mov w1, #{{65535|0xffff}}
2982 # CHECK: movz w2, #0, lsl #16
2983 # CHECK: mov w2, #-1235
2988 # CHECK: mov x2, #5299989643264
2989 # CHECK: movk xzr, #{{4321|0x10e1}}, lsl #48
2994 # CHECK: movk w3, #0
2995 # CHECK: movz x4, #0, lsl #16
2996 # CHECK: movk w5, #0, lsl #16
2997 # CHECK: movz x6, #0, lsl #32
2998 # CHECK: movk x7, #0, lsl #32
2999 # CHECK: movz x8, #0, lsl #48
3000 # CHECK: movk x9, #0, lsl #48
3010 #------------------------------------------------------------------------------
3011 # PC-relative addressing
3012 #------------------------------------------------------------------------------
3014 # It's slightly dodgy using immediates here, but harmless enough when
3015 # it's all that's available.
3017 # CHECK: adr x2, #1600
3018 # CHECK: adrp x21, #6553600
3019 # CHECK: adr x0, #262144
3024 #------------------------------------------------------------------------------
3026 #------------------------------------------------------------------------------
3029 # CHECK: hint #{{127|0x7f}}
3121 # CHECK: msr {{SPSel|SPSEL}}, #0
3122 # CHECK: msr {{DAIFSet|DAIFSET}}, #15
3123 # CHECK: msr {{DAIFClr|DAIFCLR}}, #12
3128 # CHECK: sys #7, c5, c9, #7, x5
3129 # CHECK: sys #0, c15, c15, #2
3130 # CHECK: sysl x9, #7, c5, c9, #7
3131 # CHECK: sysl x1, #0, c15, c15, #2
3137 # CHECK: {{sys #0, c7, c1, #0|ic ialluis}}
3138 # CHECK: {{sys #0, c7, c5, #0|ic iallu}}
3139 # CHECK: {{sys #3, c7, c5, #1|ic ivau}}, x9
3144 # CHECK: {{sys #3, c7, c4, #1|dc zva}}, x12
3145 # CHECK: {{sys #0, c7, c6, #1|dc ivac}}
3146 # CHECK: {{sys #0, c7, c6, #2|dc isw}}, x2
3147 # CHECK: {{sys #3, c7, c10, #1|dc cvac}}, x9
3148 # CHECK: {{sys #0, c7, c10, #2|dc csw}}, x10
3149 # CHECK: {{sys #3, c7, c11, #1|dc cvau}}, x0
3150 # CHECK: {{sys #3, c7, c14, #1|dc civac}}, x3
3151 # CHECK: {{sys #0, c7, c14, #2|dc cisw}}, x30
3162 # CHECK: msr {{teecr32_el1|TEECR32_EL1}}, x12
3163 # CHECK: msr {{osdtrrx_el1|OSDTRRX_EL1}}, x12
3164 # CHECK: msr {{mdccint_el1|MDCCINT_EL1}}, x12
3165 # CHECK: msr {{mdscr_el1|MDSCR_EL1}}, x12
3166 # CHECK: msr {{osdtrtx_el1|OSDTRTX_EL1}}, x12
3167 # CHECK: msr {{dbgdtr_el0|DBGDTR_EL0}}, x12
3168 # CHECK: msr {{dbgdtrtx_el0|DBGDTRTX_EL0}}, x12
3169 # CHECK: msr {{oseccr_el1|OSECCR_EL1}}, x12
3170 # CHECK: msr {{dbgvcr32_el2|DBGVCR32_EL2}}, x12
3171 # CHECK: msr {{dbgbvr0_el1|DBGBVR0_EL1}}, x12
3172 # CHECK: msr {{dbgbvr1_el1|DBGBVR1_EL1}}, x12
3173 # CHECK: msr {{dbgbvr2_el1|DBGBVR2_EL1}}, x12
3174 # CHECK: msr {{dbgbvr3_el1|DBGBVR3_EL1}}, x12
3175 # CHECK: msr {{dbgbvr4_el1|DBGBVR4_EL1}}, x12
3176 # CHECK: msr {{dbgbvr5_el1|DBGBVR5_EL1}}, x12
3177 # CHECK: msr {{dbgbvr6_el1|DBGBVR6_EL1}}, x12
3178 # CHECK: msr {{dbgbvr7_el1|DBGBVR7_EL1}}, x12
3179 # CHECK: msr {{dbgbvr8_el1|DBGBVR8_EL1}}, x12
3180 # CHECK: msr {{dbgbvr9_el1|DBGBVR9_EL1}}, x12
3181 # CHECK: msr {{dbgbvr10_el1|DBGBVR10_EL1}}, x12
3182 # CHECK: msr {{dbgbvr11_el1|DBGBVR11_EL1}}, x12
3183 # CHECK: msr {{dbgbvr12_el1|DBGBVR12_EL1}}, x12
3184 # CHECK: msr {{dbgbvr13_el1|DBGBVR13_EL1}}, x12
3185 # CHECK: msr {{dbgbvr14_el1|DBGBVR14_EL1}}, x12
3186 # CHECK: msr {{dbgbvr15_el1|DBGBVR15_EL1}}, x12
3187 # CHECK: msr {{dbgbcr0_el1|DBGBCR0_EL1}}, x12
3188 # CHECK: msr {{dbgbcr1_el1|DBGBCR1_EL1}}, x12
3189 # CHECK: msr {{dbgbcr2_el1|DBGBCR2_EL1}}, x12
3190 # CHECK: msr {{dbgbcr3_el1|DBGBCR3_EL1}}, x12
3191 # CHECK: msr {{dbgbcr4_el1|DBGBCR4_EL1}}, x12
3192 # CHECK: msr {{dbgbcr5_el1|DBGBCR5_EL1}}, x12
3193 # CHECK: msr {{dbgbcr6_el1|DBGBCR6_EL1}}, x12
3194 # CHECK: msr {{dbgbcr7_el1|DBGBCR7_EL1}}, x12
3195 # CHECK: msr {{dbgbcr8_el1|DBGBCR8_EL1}}, x12
3196 # CHECK: msr {{dbgbcr9_el1|DBGBCR9_EL1}}, x12
3197 # CHECK: msr {{dbgbcr10_el1|DBGBCR10_EL1}}, x12
3198 # CHECK: msr {{dbgbcr11_el1|DBGBCR11_EL1}}, x12
3199 # CHECK: msr {{dbgbcr12_el1|DBGBCR12_EL1}}, x12
3200 # CHECK: msr {{dbgbcr13_el1|DBGBCR13_EL1}}, x12
3201 # CHECK: msr {{dbgbcr14_el1|DBGBCR14_EL1}}, x12
3202 # CHECK: msr {{dbgbcr15_el1|DBGBCR15_EL1}}, x12
3203 # CHECK: msr {{dbgwvr0_el1|DBGWVR0_EL1}}, x12
3204 # CHECK: msr {{dbgwvr1_el1|DBGWVR1_EL1}}, x12
3205 # CHECK: msr {{dbgwvr2_el1|DBGWVR2_EL1}}, x12
3206 # CHECK: msr {{dbgwvr3_el1|DBGWVR3_EL1}}, x12
3207 # CHECK: msr {{dbgwvr4_el1|DBGWVR4_EL1}}, x12
3208 # CHECK: msr {{dbgwvr5_el1|DBGWVR5_EL1}}, x12
3209 # CHECK: msr {{dbgwvr6_el1|DBGWVR6_EL1}}, x12
3210 # CHECK: msr {{dbgwvr7_el1|DBGWVR7_EL1}}, x12
3211 # CHECK: msr {{dbgwvr8_el1|DBGWVR8_EL1}}, x12
3212 # CHECK: msr {{dbgwvr9_el1|DBGWVR9_EL1}}, x12
3213 # CHECK: msr {{dbgwvr10_el1|DBGWVR10_EL1}}, x12
3214 # CHECK: msr {{dbgwvr11_el1|DBGWVR11_EL1}}, x12
3215 # CHECK: msr {{dbgwvr12_el1|DBGWVR12_EL1}}, x12
3216 # CHECK: msr {{dbgwvr13_el1|DBGWVR13_EL1}}, x12
3217 # CHECK: msr {{dbgwvr14_el1|DBGWVR14_EL1}}, x12
3218 # CHECK: msr {{dbgwvr15_el1|DBGWVR15_EL1}}, x12
3219 # CHECK: msr {{dbgwcr0_el1|DBGWCR0_EL1}}, x12
3220 # CHECK: msr {{dbgwcr1_el1|DBGWCR1_EL1}}, x12
3221 # CHECK: msr {{dbgwcr2_el1|DBGWCR2_EL1}}, x12
3222 # CHECK: msr {{dbgwcr3_el1|DBGWCR3_EL1}}, x12
3223 # CHECK: msr {{dbgwcr4_el1|DBGWCR4_EL1}}, x12
3224 # CHECK: msr {{dbgwcr5_el1|DBGWCR5_EL1}}, x12
3225 # CHECK: msr {{dbgwcr6_el1|DBGWCR6_EL1}}, x12
3226 # CHECK: msr {{dbgwcr7_el1|DBGWCR7_EL1}}, x12
3227 # CHECK: msr {{dbgwcr8_el1|DBGWCR8_EL1}}, x12
3228 # CHECK: msr {{dbgwcr9_el1|DBGWCR9_EL1}}, x12
3229 # CHECK: msr {{dbgwcr10_el1|DBGWCR10_EL1}}, x12
3230 # CHECK: msr {{dbgwcr11_el1|DBGWCR11_EL1}}, x12
3231 # CHECK: msr {{dbgwcr12_el1|DBGWCR12_EL1}}, x12
3232 # CHECK: msr {{dbgwcr13_el1|DBGWCR13_EL1}}, x12
3233 # CHECK: msr {{dbgwcr14_el1|DBGWCR14_EL1}}, x12
3234 # CHECK: msr {{dbgwcr15_el1|DBGWCR15_EL1}}, x12
3235 # CHECK: msr {{teehbr32_el1|TEEHBR32_EL1}}, x12
3236 # CHECK: msr {{oslar_el1|OSLAR_EL1}}, x12
3237 # CHECK: msr {{osdlr_el1|OSDLR_EL1}}, x12
3238 # CHECK: msr {{dbgprcr_el1|DBGPRCR_EL1}}, x12
3239 # CHECK: msr {{dbgclaimset_el1|DBGCLAIMSET_EL1}}, x12
3240 # CHECK: msr {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}, x12
3241 # CHECK: msr {{csselr_el1|CSSELR_EL1}}, x12
3242 # CHECK: msr {{vpidr_el2|VPIDR_EL2}}, x12
3243 # CHECK: msr {{vmpidr_el2|VMPIDR_EL2}}, x12
3244 # CHECK: msr {{sctlr_el1|SCTLR_EL1}}, x12
3245 # CHECK: msr {{sctlr_el2|SCTLR_EL2}}, x12
3246 # CHECK: msr {{sctlr_el3|SCTLR_EL3}}, x12
3247 # CHECK: msr {{actlr_el1|ACTLR_EL1}}, x12
3248 # CHECK: msr {{actlr_el2|ACTLR_EL2}}, x12
3249 # CHECK: msr {{actlr_el3|ACTLR_EL3}}, x12
3250 # CHECK: msr {{cpacr_el1|CPACR_EL1}}, x12
3251 # CHECK: msr {{hcr_el2|HCR_EL2}}, x12
3252 # CHECK: msr {{scr_el3|SCR_EL3}}, x12
3253 # CHECK: msr {{mdcr_el2|MDCR_EL2}}, x12
3254 # CHECK: msr {{sder32_el3|SDER32_EL3}}, x12
3255 # CHECK: msr {{cptr_el2|CPTR_EL2}}, x12
3256 # CHECK: msr {{cptr_el3|CPTR_EL3}}, x12
3257 # CHECK: msr {{hstr_el2|HSTR_EL2}}, x12
3258 # CHECK: msr {{hacr_el2|HACR_EL2}}, x12
3259 # CHECK: msr {{mdcr_el3|MDCR_EL3}}, x12
3260 # CHECK: msr {{ttbr0_el1|TTBR0_EL1}}, x12
3261 # CHECK: msr {{ttbr0_el2|TTBR0_EL2}}, x12
3262 # CHECK: msr {{ttbr0_el3|TTBR0_EL3}}, x12
3263 # CHECK: msr {{ttbr1_el1|TTBR1_EL1}}, x12
3264 # CHECK: msr {{tcr_el1|TCR_EL1}}, x12
3265 # CHECK: msr {{tcr_el2|TCR_EL2}}, x12
3266 # CHECK: msr {{tcr_el3|TCR_EL3}}, x12
3267 # CHECK: msr {{vttbr_el2|VTTBR_EL2}}, x12
3268 # CHECK: msr {{vtcr_el2|VTCR_EL2}}, x12
3269 # CHECK: msr {{dacr32_el2|DACR32_EL2}}, x12
3270 # CHECK: msr {{spsr_el1|SPSR_EL1}}, x12
3271 # CHECK: msr {{spsr_el2|SPSR_EL2}}, x12
3272 # CHECK: msr {{spsr_el3|SPSR_EL3}}, x12
3273 # CHECK: msr {{elr_el1|ELR_EL1}}, x12
3274 # CHECK: msr {{elr_el2|ELR_EL2}}, x12
3275 # CHECK: msr {{elr_el3|ELR_EL3}}, x12
3276 # CHECK: msr {{sp_el0|SP_EL0}}, x12
3277 # CHECK: msr {{sp_el1|SP_EL1}}, x12
3278 # CHECK: msr {{sp_el2|SP_EL2}}, x12
3279 # CHECK: msr {{SPSel|SPSEL}}, x12
3280 # CHECK: msr {{nzcv|NZCV}}, x12
3281 # CHECK: msr {{daif|DAIF}}, x12
3282 # CHECK: msr S3_0_C4_C2_2, x12
3283 # CHECK: msr {{SPSR_irq|SPSR_IRQ}}, x12
3284 # CHECK: msr {{SPSR_abt|SPSR_ABT}}, x12
3285 # CHECK: msr {{SPSR_und|SPSR_UND}}, x12
3286 # CHECK: msr {{SPSR_fiq|SPSR_FIQ}}, x12
3287 # CHECK: msr {{fpcr|FPCR}}, x12
3288 # CHECK: msr {{fpsr|FPSR}}, x12
3289 # CHECK: msr {{dspsr_el0|DSPSR_EL0}}, x12
3290 # CHECK: msr {{dlr_el0|DLR_EL0}}, x12
3291 # CHECK: msr {{ifsr32_el2|IFSR32_EL2}}, x12
3292 # CHECK: msr {{afsr0_el1|AFSR0_EL1}}, x12
3293 # CHECK: msr {{afsr0_el2|AFSR0_EL2}}, x12
3294 # CHECK: msr {{afsr0_el3|AFSR0_EL3}}, x12
3295 # CHECK: msr {{afsr1_el1|AFSR1_EL1}}, x12
3296 # CHECK: msr {{afsr1_el2|AFSR1_EL2}}, x12
3297 # CHECK: msr {{afsr1_el3|AFSR1_EL3}}, x12
3298 # CHECK: msr {{esr_el1|ESR_EL1}}, x12
3299 # CHECK: msr {{esr_el2|ESR_EL2}}, x12
3300 # CHECK: msr {{esr_el3|ESR_EL3}}, x12
3301 # CHECK: msr {{fpexc32_el2|FPEXC32_EL2}}, x12
3302 # CHECK: msr {{far_el1|FAR_EL1}}, x12
3303 # CHECK: msr {{far_el2|FAR_EL2}}, x12
3304 # CHECK: msr {{far_el3|FAR_EL3}}, x12
3305 # CHECK: msr {{hpfar_el2|HPFAR_EL2}}, x12
3306 # CHECK: msr {{par_el1|PAR_EL1}}, x12
3307 # CHECK: msr {{pmcr_el0|PMCR_EL0}}, x12
3308 # CHECK: msr {{pmcntenset_el0|PMCNTENSET_EL0}}, x12
3309 # CHECK: msr {{pmcntenclr_el0|PMCNTENCLR_EL0}}, x12
3310 # CHECK: msr {{pmovsclr_el0|PMOVSCLR_EL0}}, x12
3311 # CHECK: msr {{pmselr_el0|PMSELR_EL0}}, x12
3312 # CHECK: msr {{pmccntr_el0|PMCCNTR_EL0}}, x12
3313 # CHECK: msr {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12
3314 # CHECK: msr {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12
3315 # CHECK: msr {{pmuserenr_el0|PMUSERENR_EL0}}, x12
3316 # CHECK: msr {{pmintenset_el1|PMINTENSET_EL1}}, x12
3317 # CHECK: msr {{pmintenclr_el1|PMINTENCLR_EL1}}, x12
3318 # CHECK: msr {{pmovsset_el0|PMOVSSET_EL0}}, x12
3319 # CHECK: msr {{mair_el1|MAIR_EL1}}, x12
3320 # CHECK: msr {{mair_el2|MAIR_EL2}}, x12
3321 # CHECK: msr {{mair_el3|MAIR_EL3}}, x12
3322 # CHECK: msr {{amair_el1|AMAIR_EL1}}, x12
3323 # CHECK: msr {{amair_el2|AMAIR_EL2}}, x12
3324 # CHECK: msr {{amair_el3|AMAIR_EL3}}, x12
3325 # CHECK: msr {{vbar_el1|VBAR_EL1}}, x12
3326 # CHECK: msr {{vbar_el2|VBAR_EL2}}, x12
3327 # CHECK: msr {{vbar_el3|VBAR_EL3}}, x12
3328 # CHECK: msr {{rmr_el1|RMR_EL1}}, x12
3329 # CHECK: msr {{rmr_el2|RMR_EL2}}, x12
3330 # CHECK: msr {{rmr_el3|RMR_EL3}}, x12
3331 # CHECK: msr {{tpidr_el0|TPIDR_EL0}}, x12
3332 # CHECK: msr {{tpidr_el2|TPIDR_EL2}}, x12
3333 # CHECK: msr {{tpidr_el3|TPIDR_EL3}}, x12
3334 # CHECK: msr {{tpidrro_el0|TPIDRRO_EL0}}, x12
3335 # CHECK: msr {{tpidr_el1|TPIDR_EL1}}, x12
3336 # CHECK: msr {{cntfrq_el0|CNTFRQ_EL0}}, x12
3337 # CHECK: msr {{cntvoff_el2|CNTVOFF_EL2}}, x12
3338 # CHECK: msr {{cntkctl_el1|CNTKCTL_EL1}}, x12
3339 # CHECK: msr {{cnthctl_el2|CNTHCTL_EL2}}, x12
3340 # CHECK: msr {{cntp_tval_el0|CNTP_TVAL_EL0}}, x12
3341 # CHECK: msr {{cnthp_tval_el2|CNTHP_TVAL_EL2}}, x12
3342 # CHECK: msr {{cntps_tval_el1|CNTPS_TVAL_EL1}}, x12
3343 # CHECK: msr {{cntp_ctl_el0|CNTP_CTL_EL0}}, x12
3344 # CHECK: msr {{cnthp_ctl_el2|CNTHP_CTL_EL2}}, x12
3345 # CHECK: msr {{cntps_ctl_el1|CNTPS_CTL_EL1}}, x12
3346 # CHECK: msr {{cntp_cval_el0|CNTP_CVAL_EL0}}, x12
3347 # CHECK: msr {{cnthp_cval_el2|CNTHP_CVAL_EL2}}, x12
3348 # CHECK: msr {{cntps_cval_el1|CNTPS_CVAL_EL1}}, x12
3349 # CHECK: msr {{cntv_tval_el0|CNTV_TVAL_EL0}}, x12
3350 # CHECK: msr {{cntv_ctl_el0|CNTV_CTL_EL0}}, x12
3351 # CHECK: msr {{cntv_cval_el0|CNTV_CVAL_EL0}}, x12
3352 # CHECK: msr {{pmevcntr0_el0|PMEVCNTR0_EL0}}, x12
3353 # CHECK: msr {{pmevcntr1_el0|PMEVCNTR1_EL0}}, x12
3354 # CHECK: msr {{pmevcntr2_el0|PMEVCNTR2_EL0}}, x12
3355 # CHECK: msr {{pmevcntr3_el0|PMEVCNTR3_EL0}}, x12
3356 # CHECK: msr {{pmevcntr4_el0|PMEVCNTR4_EL0}}, x12
3357 # CHECK: msr {{pmevcntr5_el0|PMEVCNTR5_EL0}}, x12
3358 # CHECK: msr {{pmevcntr6_el0|PMEVCNTR6_EL0}}, x12
3359 # CHECK: msr {{pmevcntr7_el0|PMEVCNTR7_EL0}}, x12
3360 # CHECK: msr {{pmevcntr8_el0|PMEVCNTR8_EL0}}, x12
3361 # CHECK: msr {{pmevcntr9_el0|PMEVCNTR9_EL0}}, x12
3362 # CHECK: msr {{pmevcntr10_el0|PMEVCNTR10_EL0}}, x12
3363 # CHECK: msr {{pmevcntr11_el0|PMEVCNTR11_EL0}}, x12
3364 # CHECK: msr {{pmevcntr12_el0|PMEVCNTR12_EL0}}, x12
3365 # CHECK: msr {{pmevcntr13_el0|PMEVCNTR13_EL0}}, x12
3366 # CHECK: msr {{pmevcntr14_el0|PMEVCNTR14_EL0}}, x12
3367 # CHECK: msr {{pmevcntr15_el0|PMEVCNTR15_EL0}}, x12
3368 # CHECK: msr {{pmevcntr16_el0|PMEVCNTR16_EL0}}, x12
3369 # CHECK: msr {{pmevcntr17_el0|PMEVCNTR17_EL0}}, x12
3370 # CHECK: msr {{pmevcntr18_el0|PMEVCNTR18_EL0}}, x12
3371 # CHECK: msr {{pmevcntr19_el0|PMEVCNTR19_EL0}}, x12
3372 # CHECK: msr {{pmevcntr20_el0|PMEVCNTR20_EL0}}, x12
3373 # CHECK: msr {{pmevcntr21_el0|PMEVCNTR21_EL0}}, x12
3374 # CHECK: msr {{pmevcntr22_el0|PMEVCNTR22_EL0}}, x12
3375 # CHECK: msr {{pmevcntr23_el0|PMEVCNTR23_EL0}}, x12
3376 # CHECK: msr {{pmevcntr24_el0|PMEVCNTR24_EL0}}, x12
3377 # CHECK: msr {{pmevcntr25_el0|PMEVCNTR25_EL0}}, x12
3378 # CHECK: msr {{pmevcntr26_el0|PMEVCNTR26_EL0}}, x12
3379 # CHECK: msr {{pmevcntr27_el0|PMEVCNTR27_EL0}}, x12
3380 # CHECK: msr {{pmevcntr28_el0|PMEVCNTR28_EL0}}, x12
3381 # CHECK: msr {{pmevcntr29_el0|PMEVCNTR29_EL0}}, x12
3382 # CHECK: msr {{pmevcntr30_el0|PMEVCNTR30_EL0}}, x12
3383 # CHECK: msr {{pmccfiltr_el0|PMCCFILTR_EL0}}, x12
3384 # CHECK: msr {{pmevtyper0_el0|PMEVTYPER0_EL0}}, x12
3385 # CHECK: msr {{pmevtyper1_el0|PMEVTYPER1_EL0}}, x12
3386 # CHECK: msr {{pmevtyper2_el0|PMEVTYPER2_EL0}}, x12
3387 # CHECK: msr {{pmevtyper3_el0|PMEVTYPER3_EL0}}, x12
3388 # CHECK: msr {{pmevtyper4_el0|PMEVTYPER4_EL0}}, x12
3389 # CHECK: msr {{pmevtyper5_el0|PMEVTYPER5_EL0}}, x12
3390 # CHECK: msr {{pmevtyper6_el0|PMEVTYPER6_EL0}}, x12
3391 # CHECK: msr {{pmevtyper7_el0|PMEVTYPER7_EL0}}, x12
3392 # CHECK: msr {{pmevtyper8_el0|PMEVTYPER8_EL0}}, x12
3393 # CHECK: msr {{pmevtyper9_el0|PMEVTYPER9_EL0}}, x12
3394 # CHECK: msr {{pmevtyper10_el0|PMEVTYPER10_EL0}}, x12
3395 # CHECK: msr {{pmevtyper11_el0|PMEVTYPER11_EL0}}, x12
3396 # CHECK: msr {{pmevtyper12_el0|PMEVTYPER12_EL0}}, x12
3397 # CHECK: msr {{pmevtyper13_el0|PMEVTYPER13_EL0}}, x12
3398 # CHECK: msr {{pmevtyper14_el0|PMEVTYPER14_EL0}}, x12
3399 # CHECK: msr {{pmevtyper15_el0|PMEVTYPER15_EL0}}, x12
3400 # CHECK: msr {{pmevtyper16_el0|PMEVTYPER16_EL0}}, x12
3401 # CHECK: msr {{pmevtyper17_el0|PMEVTYPER17_EL0}}, x12
3402 # CHECK: msr {{pmevtyper18_el0|PMEVTYPER18_EL0}}, x12
3403 # CHECK: msr {{pmevtyper19_el0|PMEVTYPER19_EL0}}, x12
3404 # CHECK: msr {{pmevtyper20_el0|PMEVTYPER20_EL0}}, x12
3405 # CHECK: msr {{pmevtyper21_el0|PMEVTYPER21_EL0}}, x12
3406 # CHECK: msr {{pmevtyper22_el0|PMEVTYPER22_EL0}}, x12
3407 # CHECK: msr {{pmevtyper23_el0|PMEVTYPER23_EL0}}, x12
3408 # CHECK: msr {{pmevtyper24_el0|PMEVTYPER24_EL0}}, x12
3409 # CHECK: msr {{pmevtyper25_el0|PMEVTYPER25_EL0}}, x12
3410 # CHECK: msr {{pmevtyper26_el0|PMEVTYPER26_EL0}}, x12
3411 # CHECK: msr {{pmevtyper27_el0|PMEVTYPER27_EL0}}, x12
3412 # CHECK: msr {{pmevtyper28_el0|PMEVTYPER28_EL0}}, x12
3413 # CHECK: msr {{pmevtyper29_el0|PMEVTYPER29_EL0}}, x12
3414 # CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12
3415 # CHECK: msr {{amair2_el1|AMAIR2_EL1}}, x12
3416 # CHECK: msr {{amair2_el12|AMAIR2_EL12}}, x12
3417 # CHECK: msr {{amair2_el2|AMAIR2_EL2}}, x12
3418 # CHECK: msr {{amair2_el3|AMAIR2_EL3}}, x12
3419 # CHECK: msr {{mair2_el1|MAIR2_EL1}}, x12
3420 # CHECK: msr {{mair2_el12|MAIR2_EL12}}, x12
3421 # CHECK: msr {{mair2_el2|MAIR2_EL2}}, x12
3422 # CHECK: msr {{mair2_el3|MAIR2_EL3}}, x12
3423 # CHECK: msr {{pire0_el1|PIRE0_EL1}}, x12
3424 # CHECK: msr {{pire0_el12|PIRE0_EL12}}, x12
3425 # CHECK: msr {{pire0_el2|PIRE0_EL2}}, x12
3426 # CHECK: msr {{pir_el1|PIR_EL1}}, x12
3427 # CHECK: msr {{pir_el12|PIR_EL12}}, x12
3428 # CHECK: msr {{pir_el2|PIR_EL2}}, x12
3429 # CHECK: msr {{pir_el3|PIR_EL3}}, x12
3430 # CHECK: msr {{s2pir_el2|S2PIR_EL2}}, x12
3431 # CHECK: msr {{por_el0|POR_EL0}}, x12
3432 # CHECK: msr {{por_el1|POR_EL1}}, x12
3433 # CHECK: msr {{por_el12|POR_EL12}}, x12
3434 # CHECK: msr {{por_el2|POR_EL2}}, x12
3435 # CHECK: msr {{por_el3|POR_EL3}}, x12
3436 # CHECK: msr {{s2por_el1|S2POR_EL1}}, x12
3437 # CHECK: msr {{sctlr2_el1|SCTLR2_EL1}}, x12
3438 # CHECK: msr {{sctlr2_el12|SCTLR2_EL12}}, x12
3439 # CHECK: msr {{sctlr2_el2|SCTLR2_EL2}}, x12
3440 # CHECK: msr {{tcr2_el1|TCR2_EL1}}, x12
3441 # CHECK: msr {{tcr2_el12|TCR2_EL12}}, x12
3442 # CHECK: msr {{tcr2_el2|TCR2_EL2}}, x12
3443 # CHECK: mrs x9, {{teecr32_el1|TEECR32_EL1}}
3444 # CHECK: mrs x9, {{osdtrrx_el1|OSDTRRX_EL1}}
3445 # CHECK: mrs x9, {{mdccsr_el0|MDCCSR_EL0}}
3446 # CHECK: mrs x9, {{mdccint_el1|MDCCINT_EL1}}
3447 # CHECK: mrs x9, {{mdscr_el1|MDSCR_EL1}}
3448 # CHECK: mrs x9, {{osdtrtx_el1|OSDTRTX_EL1}}
3449 # CHECK: mrs x9, {{dbgdtr_el0|DBGDTR_EL0}}
3450 # CHECK: mrs x9, {{dbgdtrrx_el0|DBGDTRRX_EL0}}
3451 # CHECK: mrs x9, {{oseccr_el1|OSECCR_EL1}}
3452 # CHECK: mrs x9, {{dbgvcr32_el2|DBGVCR32_EL2}}
3453 # CHECK: mrs x9, {{dbgbvr0_el1|DBGBVR0_EL1}}
3454 # CHECK: mrs x9, {{dbgbvr1_el1|DBGBVR1_EL1}}
3455 # CHECK: mrs x9, {{dbgbvr2_el1|DBGBVR2_EL1}}
3456 # CHECK: mrs x9, {{dbgbvr3_el1|DBGBVR3_EL1}}
3457 # CHECK: mrs x9, {{dbgbvr4_el1|DBGBVR4_EL1}}
3458 # CHECK: mrs x9, {{dbgbvr5_el1|DBGBVR5_EL1}}
3459 # CHECK: mrs x9, {{dbgbvr6_el1|DBGBVR6_EL1}}
3460 # CHECK: mrs x9, {{dbgbvr7_el1|DBGBVR7_EL1}}
3461 # CHECK: mrs x9, {{dbgbvr8_el1|DBGBVR8_EL1}}
3462 # CHECK: mrs x9, {{dbgbvr9_el1|DBGBVR9_EL1}}
3463 # CHECK: mrs x9, {{dbgbvr10_el1|DBGBVR10_EL1}}
3464 # CHECK: mrs x9, {{dbgbvr11_el1|DBGBVR11_EL1}}
3465 # CHECK: mrs x9, {{dbgbvr12_el1|DBGBVR12_EL1}}
3466 # CHECK: mrs x9, {{dbgbvr13_el1|DBGBVR13_EL1}}
3467 # CHECK: mrs x9, {{dbgbvr14_el1|DBGBVR14_EL1}}
3468 # CHECK: mrs x9, {{dbgbvr15_el1|DBGBVR15_EL1}}
3469 # CHECK: mrs x9, {{dbgbcr0_el1|DBGBCR0_EL1}}
3470 # CHECK: mrs x9, {{dbgbcr1_el1|DBGBCR1_EL1}}
3471 # CHECK: mrs x9, {{dbgbcr2_el1|DBGBCR2_EL1}}
3472 # CHECK: mrs x9, {{dbgbcr3_el1|DBGBCR3_EL1}}
3473 # CHECK: mrs x9, {{dbgbcr4_el1|DBGBCR4_EL1}}
3474 # CHECK: mrs x9, {{dbgbcr5_el1|DBGBCR5_EL1}}
3475 # CHECK: mrs x9, {{dbgbcr6_el1|DBGBCR6_EL1}}
3476 # CHECK: mrs x9, {{dbgbcr7_el1|DBGBCR7_EL1}}
3477 # CHECK: mrs x9, {{dbgbcr8_el1|DBGBCR8_EL1}}
3478 # CHECK: mrs x9, {{dbgbcr9_el1|DBGBCR9_EL1}}
3479 # CHECK: mrs x9, {{dbgbcr10_el1|DBGBCR10_EL1}}
3480 # CHECK: mrs x9, {{dbgbcr11_el1|DBGBCR11_EL1}}
3481 # CHECK: mrs x9, {{dbgbcr12_el1|DBGBCR12_EL1}}
3482 # CHECK: mrs x9, {{dbgbcr13_el1|DBGBCR13_EL1}}
3483 # CHECK: mrs x9, {{dbgbcr14_el1|DBGBCR14_EL1}}
3484 # CHECK: mrs x9, {{dbgbcr15_el1|DBGBCR15_EL1}}
3485 # CHECK: mrs x9, {{dbgwvr0_el1|DBGWVR0_EL1}}
3486 # CHECK: mrs x9, {{dbgwvr1_el1|DBGWVR1_EL1}}
3487 # CHECK: mrs x9, {{dbgwvr2_el1|DBGWVR2_EL1}}
3488 # CHECK: mrs x9, {{dbgwvr3_el1|DBGWVR3_EL1}}
3489 # CHECK: mrs x9, {{dbgwvr4_el1|DBGWVR4_EL1}}
3490 # CHECK: mrs x9, {{dbgwvr5_el1|DBGWVR5_EL1}}
3491 # CHECK: mrs x9, {{dbgwvr6_el1|DBGWVR6_EL1}}
3492 # CHECK: mrs x9, {{dbgwvr7_el1|DBGWVR7_EL1}}
3493 # CHECK: mrs x9, {{dbgwvr8_el1|DBGWVR8_EL1}}
3494 # CHECK: mrs x9, {{dbgwvr9_el1|DBGWVR9_EL1}}
3495 # CHECK: mrs x9, {{dbgwvr10_el1|DBGWVR10_EL1}}
3496 # CHECK: mrs x9, {{dbgwvr11_el1|DBGWVR11_EL1}}
3497 # CHECK: mrs x9, {{dbgwvr12_el1|DBGWVR12_EL1}}
3498 # CHECK: mrs x9, {{dbgwvr13_el1|DBGWVR13_EL1}}
3499 # CHECK: mrs x9, {{dbgwvr14_el1|DBGWVR14_EL1}}
3500 # CHECK: mrs x9, {{dbgwvr15_el1|DBGWVR15_EL1}}
3501 # CHECK: mrs x9, {{dbgwcr0_el1|DBGWCR0_EL1}}
3502 # CHECK: mrs x9, {{dbgwcr1_el1|DBGWCR1_EL1}}
3503 # CHECK: mrs x9, {{dbgwcr2_el1|DBGWCR2_EL1}}
3504 # CHECK: mrs x9, {{dbgwcr3_el1|DBGWCR3_EL1}}
3505 # CHECK: mrs x9, {{dbgwcr4_el1|DBGWCR4_EL1}}
3506 # CHECK: mrs x9, {{dbgwcr5_el1|DBGWCR5_EL1}}
3507 # CHECK: mrs x9, {{dbgwcr6_el1|DBGWCR6_EL1}}
3508 # CHECK: mrs x9, {{dbgwcr7_el1|DBGWCR7_EL1}}
3509 # CHECK: mrs x9, {{dbgwcr8_el1|DBGWCR8_EL1}}
3510 # CHECK: mrs x9, {{dbgwcr9_el1|DBGWCR9_EL1}}
3511 # CHECK: mrs x9, {{dbgwcr10_el1|DBGWCR10_EL1}}
3512 # CHECK: mrs x9, {{dbgwcr11_el1|DBGWCR11_EL1}}
3513 # CHECK: mrs x9, {{dbgwcr12_el1|DBGWCR12_EL1}}
3514 # CHECK: mrs x9, {{dbgwcr13_el1|DBGWCR13_EL1}}
3515 # CHECK: mrs x9, {{dbgwcr14_el1|DBGWCR14_EL1}}
3516 # CHECK: mrs x9, {{dbgwcr15_el1|DBGWCR15_EL1}}
3517 # CHECK: mrs x9, {{mdrar_el1|MDRAR_EL1}}
3518 # CHECK: mrs x9, {{teehbr32_el1|TEEHBR32_EL1}}
3519 # CHECK: mrs x9, {{oslsr_el1|OSLSR_EL1}}
3520 # CHECK: mrs x9, {{osdlr_el1|OSDLR_EL1}}
3521 # CHECK: mrs x9, {{dbgprcr_el1|DBGPRCR_EL1}}
3522 # CHECK: mrs x9, {{dbgclaimset_el1|DBGCLAIMSET_EL1}}
3523 # CHECK: mrs x9, {{dbgclaimclr_el1|DBGCLAIMCLR_EL1}}
3524 # CHECK: mrs x9, {{dbgauthstatus_el1|DBGAUTHSTATUS_EL1}}
3525 # CHECK: mrs x9, {{midr_el1|MIDR_EL1}}
3526 # CHECK: mrs x9, {{ccsidr_el1|CCSIDR_EL1}}
3527 # CHECK: mrs x9, {{csselr_el1|CSSELR_EL1}}
3528 # CHECK-V83: mrs x9, {{ccsidr2_el1|CCSIDR2_EL1}}
3529 # CHECK: mrs x9, {{vpidr_el2|VPIDR_EL2}}
3530 # CHECK: mrs x9, {{clidr_el1|CLIDR_EL1}}
3531 # CHECK: mrs x9, {{ctr_el0|CTR_EL0}}
3532 # CHECK: mrs x9, {{mpidr_el1|MPIDR_EL1}}
3533 # CHECK: mrs x9, {{vmpidr_el2|VMPIDR_EL2}}
3534 # CHECK: mrs x9, {{revidr_el1|REVIDR_EL1}}
3535 # CHECK: mrs x9, {{aidr_el1|AIDR_EL1}}
3536 # CHECK: mrs x9, {{dczid_el0|DCZID_EL0}}
3537 # CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}}
3538 # CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}}
3539 # CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}}
3540 # CHECK: mrs x9, {{id_dfr1_el1|ID_DFR1_EL1}}
3541 # CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}}
3542 # CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}
3543 # CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}
3544 # CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}
3545 # CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}
3546 # CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}}
3547 # CHECK: mrs x9, {{id_mmfr5_el1|ID_MMFR5_EL1}}
3548 # CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}}
3549 # CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}}
3550 # CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}}
3551 # CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}}
3552 # CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}}
3553 # CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}}
3554 # CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}}
3555 # CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}}
3556 # CHECK: mrs x9, {{mvfr2_el1|MVFR2_EL1}}
3557 # CHECK: mrs x9, {{id_aa64pfr0_el1|ID_AA64PFR0_EL1}}
3558 # CHECK: mrs x9, {{id_aa64pfr1_el1|ID_AA64PFR1_EL1}}
3559 # CHECK: mrs x9, {{id_aa64pfr2_el1|ID_AA64PFR2_EL1}}
3560 # CHECK: mrs x9, {{id_aa64dfr0_el1|ID_AA64DFR0_EL1}}
3561 # CHECK: mrs x9, {{id_aa64dfr1_el1|ID_AA64DFR1_EL1}}
3562 # CHECK: mrs x9, {{id_aa64afr0_el1|ID_AA64AFR0_EL1}}
3563 # CHECK: mrs x9, {{id_aa64afr1_el1|ID_AA64AFR1_EL1}}
3564 # CHECK: mrs x9, {{id_aa64isar0_el1|ID_AA64ISAR0_EL1}}
3565 # CHECK: mrs x9, {{id_aa64isar1_el1|ID_AA64ISAR1_EL1}}
3566 # CHECK: mrs x9, {{id_aa64isar2_el1|ID_AA64ISAR2_EL1}}
3567 # CHECK: mrs x9, {{id_aa64mmfr0_el1|ID_AA64MMFR0_EL1}}
3568 # CHECK: mrs x9, {{id_aa64mmfr1_el1|ID_AA64MMFR1_EL1}}
3569 # CHECK: mrs x9, {{id_aa64mmfr2_el1|ID_AA64MMFR2_EL1}}
3570 # CHECK: mrs x9, {{id_aa64mmfr3_el1|ID_AA64MMFR3_EL1}}
3571 # CHECK: mrs x9, {{id_aa64mmfr4_el1|ID_AA64MMFR4_EL1}}
3572 # CHECK: mrs x9, {{sctlr_el1|SCTLR_EL1}}
3573 # CHECK: mrs x9, {{sctlr_el2|SCTLR_EL2}}
3574 # CHECK: mrs x9, {{sctlr_el3|SCTLR_EL3}}
3575 # CHECK: mrs x9, {{actlr_el1|ACTLR_EL1}}
3576 # CHECK: mrs x9, {{actlr_el2|ACTLR_EL2}}
3577 # CHECK: mrs x9, {{actlr_el3|ACTLR_EL3}}
3578 # CHECK: mrs x9, {{cpacr_el1|CPACR_EL1}}
3579 # CHECK: mrs x9, {{hcr_el2|HCR_EL2}}
3580 # CHECK: mrs x9, {{scr_el3|SCR_EL3}}
3581 # CHECK: mrs x9, {{mdcr_el2|MDCR_EL2}}
3582 # CHECK: mrs x9, {{sder32_el3|SDER32_EL3}}
3583 # CHECK: mrs x9, {{cptr_el2|CPTR_EL2}}
3584 # CHECK: mrs x9, {{cptr_el3|CPTR_EL3}}
3585 # CHECK: mrs x9, {{hstr_el2|HSTR_EL2}}
3586 # CHECK: mrs x9, {{hacr_el2|HACR_EL2}}
3587 # CHECK: mrs x9, {{mdcr_el3|MDCR_EL3}}
3588 # CHECK: mrs x9, {{ttbr0_el1|TTBR0_EL1}}
3589 # CHECK: mrs x9, {{ttbr0_el2|TTBR0_EL2}}
3590 # CHECK: mrs x9, {{ttbr0_el3|TTBR0_EL3}}
3591 # CHECK: mrs x9, {{ttbr1_el1|TTBR1_EL1}}
3592 # CHECK: mrs x9, {{tcr_el1|TCR_EL1}}
3593 # CHECK: mrs x9, {{tcr_el2|TCR_EL2}}
3594 # CHECK: mrs x9, {{tcr_el3|TCR_EL3}}
3595 # CHECK: mrs x9, {{vttbr_el2|VTTBR_EL2}}
3596 # CHECK: mrs x9, {{vtcr_el2|VTCR_EL2}}
3597 # CHECK: mrs x9, {{dacr32_el2|DACR32_EL2}}
3598 # CHECK: mrs x9, {{spsr_el1|SPSR_EL1}}
3599 # CHECK: mrs x9, {{spsr_el2|SPSR_EL2}}
3600 # CHECK: mrs x9, {{spsr_el3|SPSR_EL3}}
3601 # CHECK: mrs x9, {{elr_el1|ELR_EL1}}
3602 # CHECK: mrs x9, {{elr_el2|ELR_EL2}}
3603 # CHECK: mrs x9, {{elr_el3|ELR_EL3}}
3604 # CHECK: mrs x9, {{sp_el0|SP_EL0}}
3605 # CHECK: mrs x9, {{sp_el1|SP_EL1}}
3606 # CHECK: mrs x9, {{sp_el2|SP_EL2}}
3607 # CHECK: mrs x9, {{SPSel|SPSEL}}
3608 # CHECK: mrs x9, {{nzcv|NZCV}}
3609 # CHECK: mrs x9, {{daif|DAIF}}
3610 # CHECK: mrs x9, {{CurrentEL|CURRENTEL}}
3611 # CHECK: mrs x9, {{SPSR_irq|SPSR_IRQ}}
3612 # CHECK: mrs x9, {{SPSR_abt|SPSR_ABT}}
3613 # CHECK: mrs x9, {{SPSR_und|SPSR_UND}}
3614 # CHECK: mrs x9, {{SPSR_fiq|SPSR_FIQ}}
3615 # CHECK: mrs x9, {{fpcr|FPCR}}
3616 # CHECK: mrs x9, {{fpsr|FPSR}}
3617 # CHECK: mrs x9, {{dspsr_el0|DSPSR_EL0}}
3618 # CHECK: mrs x9, {{dlr_el0|DLR_EL0}}
3619 # CHECK: mrs x9, {{ifsr32_el2|IFSR32_EL2}}
3620 # CHECK: mrs x9, {{afsr0_el1|AFSR0_EL1}}
3621 # CHECK: mrs x9, {{afsr0_el2|AFSR0_EL2}}
3622 # CHECK: mrs x9, {{afsr0_el3|AFSR0_EL3}}
3623 # CHECK: mrs x9, {{afsr1_el1|AFSR1_EL1}}
3624 # CHECK: mrs x9, {{afsr1_el2|AFSR1_EL2}}
3625 # CHECK: mrs x9, {{afsr1_el3|AFSR1_EL3}}
3626 # CHECK: mrs x9, {{esr_el1|ESR_EL1}}
3627 # CHECK: mrs x9, {{esr_el2|ESR_EL2}}
3628 # CHECK: mrs x9, {{esr_el3|ESR_EL3}}
3629 # CHECK: mrs x9, {{fpexc32_el2|FPEXC32_EL2}}
3630 # CHECK: mrs x9, {{far_el1|FAR_EL1}}
3631 # CHECK: mrs x9, {{far_el2|FAR_EL2}}
3632 # CHECK: mrs x9, {{far_el3|FAR_EL3}}
3633 # CHECK: mrs x9, {{hpfar_el2|HPFAR_EL2}}
3634 # CHECK: mrs x9, {{par_el1|PAR_EL1}}
3635 # CHECK: mrs x9, {{pmcr_el0|PMCR_EL0}}
3636 # CHECK: mrs x9, {{pmcntenset_el0|PMCNTENSET_EL0}}
3637 # CHECK: mrs x9, {{pmcntenclr_el0|PMCNTENCLR_EL0}}
3638 # CHECK: mrs x9, {{pmovsclr_el0|PMOVSCLR_EL0}}
3639 # CHECK: mrs x9, {{pmselr_el0|PMSELR_EL0}}
3640 # CHECK: mrs x9, {{pmceid0_el0|PMCEID0_EL0}}
3641 # CHECK: mrs x9, {{pmceid1_el0|PMCEID1_EL0}}
3642 # CHECK: mrs x9, {{pmccntr_el0|PMCCNTR_EL0}}
3643 # CHECK: mrs x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}}
3644 # CHECK: mrs x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}}
3645 # CHECK: mrs x9, {{pmuserenr_el0|PMUSERENR_EL0}}
3646 # CHECK: mrs x9, {{pmintenset_el1|PMINTENSET_EL1}}
3647 # CHECK: mrs x9, {{pmintenclr_el1|PMINTENCLR_EL1}}
3648 # CHECK: mrs x9, {{pmovsset_el0|PMOVSSET_EL0}}
3649 # CHECK: mrs x9, {{mair_el1|MAIR_EL1}}
3650 # CHECK: mrs x9, {{mair_el2|MAIR_EL2}}
3651 # CHECK: mrs x9, {{mair_el3|MAIR_EL3}}
3652 # CHECK: mrs x9, {{amair_el1|AMAIR_EL1}}
3653 # CHECK: mrs x9, {{amair_el2|AMAIR_EL2}}
3654 # CHECK: mrs x9, {{amair_el3|AMAIR_EL3}}
3655 # CHECK: mrs x9, {{vbar_el1|VBAR_EL1}}
3656 # CHECK: mrs x9, {{vbar_el2|VBAR_EL2}}
3657 # CHECK: mrs x9, {{vbar_el3|VBAR_EL3}}
3658 # CHECK: mrs x9, {{rvbar_el1|RVBAR_EL1}}
3659 # CHECK: mrs x9, {{rvbar_el2|RVBAR_EL2}}
3660 # CHECK: mrs x9, {{rvbar_el3|RVBAR_EL3}}
3661 # CHECK: mrs x9, {{rmr_el1|RMR_EL1}}
3662 # CHECK: mrs x9, {{rmr_el2|RMR_EL2}}
3663 # CHECK: mrs x9, {{rmr_el3|RMR_EL3}}
3664 # CHECK: mrs x9, {{isr_el1|ISR_EL1}}
3665 # CHECK: mrs x9, {{contextidr_el1|CONTEXTIDR_EL1}}
3666 # CHECK: mrs x9, {{tpidr_el0|TPIDR_EL0}}
3667 # CHECK: mrs x9, {{tpidr_el2|TPIDR_EL2}}
3668 # CHECK: mrs x9, {{tpidr_el3|TPIDR_EL3}}
3669 # CHECK: mrs x9, {{tpidrro_el0|TPIDRRO_EL0}}
3670 # CHECK: mrs x9, {{tpidr_el1|TPIDR_EL1}}
3671 # CHECK: mrs x9, {{cntfrq_el0|CNTFRQ_EL0}}
3672 # CHECK: mrs x9, {{cntpct_el0|CNTPCT_EL0}}
3673 # CHECK: mrs x9, {{cntvct_el0|CNTVCT_EL0}}
3674 # CHECK: mrs x9, {{cntvoff_el2|CNTVOFF_EL2}}
3675 # CHECK: mrs x9, {{cntkctl_el1|CNTKCTL_EL1}}
3676 # CHECK: mrs x9, {{cnthctl_el2|CNTHCTL_EL2}}
3677 # CHECK: mrs x9, {{cntp_tval_el0|CNTP_TVAL_EL0}}
3678 # CHECK: mrs x9, {{cnthp_tval_el2|CNTHP_TVAL_EL2}}
3679 # CHECK: mrs x9, {{cntps_tval_el1|CNTPS_TVAL_EL1}}
3680 # CHECK: mrs x9, {{cntp_ctl_el0|CNTP_CTL_EL0}}
3681 # CHECK: mrs x9, {{cnthp_ctl_el2|CNTHP_CTL_EL2}}
3682 # CHECK: mrs x9, {{cntps_ctl_el1|CNTPS_CTL_EL1}}
3683 # CHECK: mrs x9, {{cntp_cval_el0|CNTP_CVAL_EL0}}
3684 # CHECK: mrs x9, {{cnthp_cval_el2|CNTHP_CVAL_EL2}}
3685 # CHECK: mrs x9, {{cntps_cval_el1|CNTPS_CVAL_EL1}}
3686 # CHECK: mrs x9, {{cntv_tval_el0|CNTV_TVAL_EL0}}
3687 # CHECK: mrs x9, {{cntv_ctl_el0|CNTV_CTL_EL0}}
3688 # CHECK: mrs x9, {{cntv_cval_el0|CNTV_CVAL_EL0}}
3689 # CHECK: mrs x9, {{pmevcntr0_el0|PMEVCNTR0_EL0}}
3690 # CHECK: mrs x9, {{pmevcntr1_el0|PMEVCNTR1_EL0}}
3691 # CHECK: mrs x9, {{pmevcntr2_el0|PMEVCNTR2_EL0}}
3692 # CHECK: mrs x9, {{pmevcntr3_el0|PMEVCNTR3_EL0}}
3693 # CHECK: mrs x9, {{pmevcntr4_el0|PMEVCNTR4_EL0}}
3694 # CHECK: mrs x9, {{pmevcntr5_el0|PMEVCNTR5_EL0}}
3695 # CHECK: mrs x9, {{pmevcntr6_el0|PMEVCNTR6_EL0}}
3696 # CHECK: mrs x9, {{pmevcntr7_el0|PMEVCNTR7_EL0}}
3697 # CHECK: mrs x9, {{pmevcntr8_el0|PMEVCNTR8_EL0}}
3698 # CHECK: mrs x9, {{pmevcntr9_el0|PMEVCNTR9_EL0}}
3699 # CHECK: mrs x9, {{pmevcntr10_el0|PMEVCNTR10_EL0}}
3700 # CHECK: mrs x9, {{pmevcntr11_el0|PMEVCNTR11_EL0}}
3701 # CHECK: mrs x9, {{pmevcntr12_el0|PMEVCNTR12_EL0}}
3702 # CHECK: mrs x9, {{pmevcntr13_el0|PMEVCNTR13_EL0}}
3703 # CHECK: mrs x9, {{pmevcntr14_el0|PMEVCNTR14_EL0}}
3704 # CHECK: mrs x9, {{pmevcntr15_el0|PMEVCNTR15_EL0}}
3705 # CHECK: mrs x9, {{pmevcntr16_el0|PMEVCNTR16_EL0}}
3706 # CHECK: mrs x9, {{pmevcntr17_el0|PMEVCNTR17_EL0}}
3707 # CHECK: mrs x9, {{pmevcntr18_el0|PMEVCNTR18_EL0}}
3708 # CHECK: mrs x9, {{pmevcntr19_el0|PMEVCNTR19_EL0}}
3709 # CHECK: mrs x9, {{pmevcntr20_el0|PMEVCNTR20_EL0}}
3710 # CHECK: mrs x9, {{pmevcntr21_el0|PMEVCNTR21_EL0}}
3711 # CHECK: mrs x9, {{pmevcntr22_el0|PMEVCNTR22_EL0}}
3712 # CHECK: mrs x9, {{pmevcntr23_el0|PMEVCNTR23_EL0}}
3713 # CHECK: mrs x9, {{pmevcntr24_el0|PMEVCNTR24_EL0}}
3714 # CHECK: mrs x9, {{pmevcntr25_el0|PMEVCNTR25_EL0}}
3715 # CHECK: mrs x9, {{pmevcntr26_el0|PMEVCNTR26_EL0}}
3716 # CHECK: mrs x9, {{pmevcntr27_el0|PMEVCNTR27_EL0}}
3717 # CHECK: mrs x9, {{pmevcntr28_el0|PMEVCNTR28_EL0}}
3718 # CHECK: mrs x9, {{pmevcntr29_el0|PMEVCNTR29_EL0}}
3719 # CHECK: mrs x9, {{pmevcntr30_el0|PMEVCNTR30_EL0}}
3720 # CHECK: mrs x9, {{pmccfiltr_el0|PMCCFILTR_EL0}}
3721 # CHECK: mrs x9, {{pmevtyper0_el0|PMEVTYPER0_EL0}}
3722 # CHECK: mrs x9, {{pmevtyper1_el0|PMEVTYPER1_EL0}}
3723 # CHECK: mrs x9, {{pmevtyper2_el0|PMEVTYPER2_EL0}}
3724 # CHECK: mrs x9, {{pmevtyper3_el0|PMEVTYPER3_EL0}}
3725 # CHECK: mrs x9, {{pmevtyper4_el0|PMEVTYPER4_EL0}}
3726 # CHECK: mrs x9, {{pmevtyper5_el0|PMEVTYPER5_EL0}}
3727 # CHECK: mrs x9, {{pmevtyper6_el0|PMEVTYPER6_EL0}}
3728 # CHECK: mrs x9, {{pmevtyper7_el0|PMEVTYPER7_EL0}}
3729 # CHECK: mrs x9, {{pmevtyper8_el0|PMEVTYPER8_EL0}}
3730 # CHECK: mrs x9, {{pmevtyper9_el0|PMEVTYPER9_EL0}}
3731 # CHECK: mrs x9, {{pmevtyper10_el0|PMEVTYPER10_EL0}}
3732 # CHECK: mrs x9, {{pmevtyper11_el0|PMEVTYPER11_EL0}}
3733 # CHECK: mrs x9, {{pmevtyper12_el0|PMEVTYPER12_EL0}}
3734 # CHECK: mrs x9, {{pmevtyper13_el0|PMEVTYPER13_EL0}}
3735 # CHECK: mrs x9, {{pmevtyper14_el0|PMEVTYPER14_EL0}}
3736 # CHECK: mrs x9, {{pmevtyper15_el0|PMEVTYPER15_EL0}}
3737 # CHECK: mrs x9, {{pmevtyper16_el0|PMEVTYPER16_EL0}}
3738 # CHECK: mrs x9, {{pmevtyper17_el0|PMEVTYPER17_EL0}}
3739 # CHECK: mrs x9, {{pmevtyper18_el0|PMEVTYPER18_EL0}}
3740 # CHECK: mrs x9, {{pmevtyper19_el0|PMEVTYPER19_EL0}}
3741 # CHECK: mrs x9, {{pmevtyper20_el0|PMEVTYPER20_EL0}}
3742 # CHECK: mrs x9, {{pmevtyper21_el0|PMEVTYPER21_EL0}}
3743 # CHECK: mrs x9, {{pmevtyper22_el0|PMEVTYPER22_EL0}}
3744 # CHECK: mrs x9, {{pmevtyper23_el0|PMEVTYPER23_EL0}}
3745 # CHECK: mrs x9, {{pmevtyper24_el0|PMEVTYPER24_EL0}}
3746 # CHECK: mrs x9, {{pmevtyper25_el0|PMEVTYPER25_EL0}}
3747 # CHECK: mrs x9, {{pmevtyper26_el0|PMEVTYPER26_EL0}}
3748 # CHECK: mrs x9, {{pmevtyper27_el0|PMEVTYPER27_EL0}}
3749 # CHECK: mrs x9, {{pmevtyper28_el0|PMEVTYPER28_EL0}}
3750 # CHECK: mrs x9, {{pmevtyper29_el0|PMEVTYPER29_EL0}}
3751 # CHECK: mrs x9, {{pmevtyper30_el0|PMEVTYPER30_EL0}}
3752 # CHECK: mrs x9, {{amair2_el1|AMAIR2_EL1}}
3753 # CHECK: mrs x9, {{amair2_el12|AMAIR2_EL12}}
3754 # CHECK: mrs x9, {{amair2_el2|AMAIR2_EL2}}
3755 # CHECK: mrs x9, {{amair2_el3|AMAIR2_EL3}}
3756 # CHECK: mrs x9, {{mair2_el1|MAIR2_EL1}}
3757 # CHECK: mrs x9, {{mair2_el12|MAIR2_EL12}}
3758 # CHECK: mrs x9, {{mair2_el2|MAIR2_EL2}}
3759 # CHECK: mrs x9, {{mair2_el3|MAIR2_EL3}}
3760 # CHECK: mrs x9, {{pire0_el1|PIRE0_EL1}}
3761 # CHECK: mrs x9, {{pire0_el12|PIRE0_EL12}}
3762 # CHECK: mrs x9, {{pire0_el2|PIRE0_EL2}}
3763 # CHECK: mrs x9, {{pir_el1|PIR_EL1}}
3764 # CHECK: mrs x9, {{pir_el12|PIR_EL12}}
3765 # CHECK: mrs x9, {{pir_el2|PIR_EL2}}
3766 # CHECK: mrs x9, {{pir_el3|PIR_EL3}}
3767 # CHECK: mrs x9, {{s2pir_el2|S2PIR_EL2}}
3768 # CHECK: mrs x9, {{por_el0|POR_EL0}}
3769 # CHECK: mrs x9, {{por_el1|POR_EL1}}
3770 # CHECK: mrs x9, {{por_el12|POR_EL12}}
3771 # CHECK: mrs x9, {{por_el2|POR_EL2}}
3772 # CHECK: mrs x9, {{por_el3|POR_EL3}}
3773 # CHECK: mrs x9, {{s2por_el1|S2POR_EL1}}
3774 # CHECK: mrs x9, {{sctlr2_el1|SCTLR2_EL1}}
3775 # CHECK: mrs x9, {{sctlr2_el12|SCTLR2_EL12}}
3776 # CHECK: mrs x9, {{sctlr2_el2|SCTLR2_EL2}}
3777 # CHECK: mrs x9, {{sctlr2_el3|SCTLR2_EL3}}
3778 # CHECK: mrs x9, {{tcr2_el1|TCR2_EL1}}
3779 # CHECK: mrs x9, {{tcr2_el12|TCR2_EL12}}
3780 # CHECK: mrs x9, {{tcr2_el2|TCR2_EL2}}
4405 # CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}
4406 # CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}}
4407 # CHECK: mrs xzr, {{s0_0_c4_c0_0|S0_0_C4_C0_0}}
4408 # CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12
4409 # CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5
4410 # CHECK: msr {{s0_0_c4_c0_0|S0_0_C4_C0_0}}, xzr
4418 #------------------------------------------------------------------------------
4419 # Test and branch (immediate)
4420 #------------------------------------------------------------------------------
4422 # CHECK: tbz x12, #62, #0
4423 # CHECK: tbz x12, #62, #4
4424 # CHECK: tbz x12, #62, #-32768
4425 # CHECK: tbnz x12, #60, #32764
4431 #------------------------------------------------------------------------------
4432 # Unconditional branch (immediate)
4433 #------------------------------------------------------------------------------
4437 # CHECK: b #134217724
4442 #------------------------------------------------------------------------------
4443 # Unconditional branch (register)
4444 #------------------------------------------------------------------------------