llvm/test/MC/Hexagon/hvx-tmp-accum-no-erros.s

   1 # RUN: llvm-mc -triple=hexagon -mattr=+hvxv68 -filetype=obj %s | llvm-objdump --no-print-imm-hex --mattr=+hvxv68 -d - | FileCheck %s
   2
   3 # packet w/accum with register different from one loaded to
   4 {
   5     v1.tmp = vmem(r0+#0)
   6     v0.w += vrmpy(v1.b,v2.b)
   7 }
   8
   9 # CHECK: { v0.w += vrmpy(v1.b,v2.b)
  10 # CHECK-NEXT:  v1.tmp = vmem(r0+#0) }
  11
  12 # packet w/accum and store or other non-def register use
  13 {
  14     v1.tmp = vmem(r0+#0)
  15     v0 += vrmpyub(v1, v3)
  16     vmem(r0) = v0
  17 }
  18
  19 # CHECK: { v0.uw += vrmpy(v1.ub,v3.ub)
  20 # CHECK-NEXT:  v1.tmp = vmem(r0+#0)
  21 # CHECK-NEXT:  vmem(r0+#0) = v0 }
  22
  23 # packet w/non-accum and otherwise-legal register def/use
  24 {
  25     v0.tmp =vmem(r2+#0)
  26     Q3 = vcmp.eq(v0.w, v5.w)
  27 }
  28
  29 # CHECK: { q3 = vcmp.eq(v0.w,v5.w)
  30 # CHECK-NEXT: v0.tmp = vmem(r2+#0) }
  31
  32 # scalar "accums" unaffected by this change.
  33 {
  34     r0 += add(r1, r2)
  35 }
  36
  37 # CHECK { r0 += add(r1,r2) }