llvm/test/MC/Hexagon/sysregs3.s

   1 # RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s
   2 #
   3
   4 # Verify exceptions to the grouping rules for some registers.
   5
   6         { r6=ssr; r0=memw(r0) }
   7 # CHECK: { r6 = ssr
   8         { r7:6=ccr:ssr; r1:0=memd(r0) }
   9 # CHECK: { r7:6 = s7:6
  10         { ssr=r6; r0=memw(r0) }
  11 # CHECK: { ssr = r6
  12         { s7:6=r7:6; r1:0=memd(r0) }
  13 # CHECK: { s7:6 = r7:6