1 # RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
2 # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
3 # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
4 # RUN: | llvm-objdump -d - \
5 # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
7 ##################################
8 # Hypervisor Configuration
9 ##################################
13 # CHECK-INST: csrrs t1, henvcfgh, zero
14 # CHECK-ENC: encoding: [0x73,0x23,0xa0,0x61]
15 # CHECK-INST-ALIAS: csrr t1, henvcfgh
17 # CHECK-INST: csrrs t2, henvcfgh, zero
18 # CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x61]
19 # CHECK-INST-ALIAS: csrr t2, henvcfgh
21 csrrs t1
, henvcfgh
, zero
25 #####################################################
26 # Hypervisor Counter/Timer Virtualization Registers
27 #####################################################
31 # CHECK-INST: csrrs t1, htimedeltah, zero
32 # CHECK-ENC: encoding: [0x73,0x23,0x50,0x61]
33 # CHECK-INST-ALIAS: csrr t1, htimedeltah
35 # CHECK-INST: csrrs t2, htimedeltah, zero
36 # CHECK-ENC: encoding: [0xf3,0x23,0x50,0x61]
37 # CHECK-INST-ALIAS: csrr t2, htimedeltah
39 csrrs t1
, htimedeltah
, zero
43 ################################
44 # Virtual Supervisor Registers
45 ################################
49 # CHECK-INST: csrrs t1, vstimecmph, zero
50 # CHECK-ENC: encoding: [0x73,0x23,0xd0,0x25]
51 # CHECK-INST-ALIAS: csrr t1, vstimecmph
53 # CHECK-INST: csrrs t2, vstimecmph, zero
54 # CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x25]
55 # CHECK-INST-ALIAS: csrr t2, vstimecmph
57 csrrs t1
, vstimecmph
, zero
61 #########################################
62 # State Enable Extension (Smstateen)
63 #########################################
67 # CHECK-INST: csrrs t1, hstateen0h, zero
68 # CHECK-ENC: encoding: [0x73,0x23,0xc0,0x61]
69 # CHECK-INST-ALIAS: csrr t1, hstateen0h
71 # CHECK-INST: csrrs t2, hstateen0h, zero
72 # CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x61]
73 # CHECK-INST-ALIAS: csrr t2, hstateen0h
75 csrrs t1
, hstateen0h
, zero
81 # CHECK-INST: csrrs t1, hstateen1h, zero
82 # CHECK-ENC: encoding: [0x73,0x23,0xd0,0x61]
83 # CHECK-INST-ALIAS: csrr t1, hstateen1h
85 # CHECK-INST: csrrs t2, hstateen1h, zero
86 # CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x61]
87 # CHECK-INST-ALIAS: csrr t2, hstateen1h
89 csrrs t1
, hstateen1h
, zero
95 # CHECK-INST: csrrs t1, hstateen2h, zero
96 # CHECK-ENC: encoding: [0x73,0x23,0xe0,0x61]
97 # CHECK-INST-ALIAS: csrr t1, hstateen2h
99 # CHECK-INST: csrrs t2, hstateen2h, zero
100 # CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x61]
101 # CHECK-INST-ALIAS: csrr t2, hstateen2h
103 csrrs t1
, hstateen2h
, zero
105 csrrs t2
, 0x61E, zero
109 # CHECK-INST: csrrs t1, hstateen3h, zero
110 # CHECK-ENC: encoding: [0x73,0x23,0xf0,0x61]
111 # CHECK-INST-ALIAS: csrr t1, hstateen3h
113 # CHECK-INST: csrrs t2, hstateen3h, zero
114 # CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x61]
115 # CHECK-INST-ALIAS: csrr t2, hstateen3h
117 csrrs t1
, hstateen3h
, zero
119 csrrs t2
, 0x61F, zero
121 #########################################
122 # Advanced Interrupt Architecture (Smaia and Ssaia)
123 #########################################
127 # CHECK-INST: csrrs t1, hidelegh, zero
128 # CHECK-ENC: encoding: [0x73,0x23,0x30,0x61]
129 # CHECK-INST-ALIAS: csrr t1, hidelegh
131 # CHECK-INST: csrrs t2, hidelegh, zero
132 # CHECK-ENC: encoding: [0xf3,0x23,0x30,0x61]
133 # CHECK-INST-ALIAS: csrr t2, hidelegh
135 csrrs t1
, hidelegh
, zero
137 csrrs t2
, 0x613, zero
141 # CHECK-INST: csrrs t1, hvienh, zero
142 # CHECK-ENC: encoding: [0x73,0x23,0x80,0x61]
143 # CHECK-INST-ALIAS: csrr t1, hvienh
145 # CHECK-INST: csrrs t2, hvienh, zero
146 # CHECK-ENC: encoding: [0xf3,0x23,0x80,0x61]
147 # CHECK-INST-ALIAS: csrr t2, hvienh
149 csrrs t1
, hvienh
, zero
151 csrrs t2
, 0x618, zero
155 # CHECK-INST: csrrs t1, hviph, zero
156 # CHECK-ENC: encoding: [0x73,0x23,0x50,0x65]
157 # CHECK-INST-ALIAS: csrr t1, hviph
159 # CHECK-INST: csrrs t2, hviph, zero
160 # CHECK-ENC: encoding: [0xf3,0x23,0x50,0x65]
161 # CHECK-INST-ALIAS: csrr t2, hviph
163 csrrs t1
, hviph
, zero
165 csrrs t2
, 0x655, zero
169 # CHECK-INST: csrrs t1, hviprio1h, zero
170 # CHECK-ENC: encoding: [0x73,0x23,0x60,0x65]
171 # CHECK-INST-ALIAS: csrr t1, hviprio1h
173 # CHECK-INST: csrrs t2, hviprio1h, zero
174 # CHECK-ENC: encoding: [0xf3,0x23,0x60,0x65]
175 # CHECK-INST-ALIAS: csrr t2, hviprio1h
177 csrrs t1
, hviprio1h
, zero
179 csrrs t2
, 0x656, zero
183 # CHECK-INST: csrrs t1, hviprio2h, zero
184 # CHECK-ENC: encoding: [0x73,0x23,0x70,0x65]
185 # CHECK-INST-ALIAS: csrr t1, hviprio2h
187 # CHECK-INST: csrrs t2, hviprio2h, zero
188 # CHECK-ENC: encoding: [0xf3,0x23,0x70,0x65]
189 # CHECK-INST-ALIAS: csrr t2, hviprio2h
191 csrrs t1
, hviprio2h
, zero
193 csrrs t2
, 0x657, zero
197 # CHECK-INST: csrrs t1, vsieh, zero
198 # CHECK-ENC: encoding: [0x73,0x23,0x40,0x21]
199 # CHECK-INST-ALIAS: csrr t1, vsieh
201 # CHECK-INST: csrrs t2, vsieh, zero
202 # CHECK-ENC: encoding: [0xf3,0x23,0x40,0x21]
203 # CHECK-INST-ALIAS: csrr t2, vsieh
205 csrrs t1
, vsieh
, zero
207 csrrs t2
, 0x214, zero
211 # CHECK-INST: csrrs t1, vsiph, zero
212 # CHECK-ENC: encoding: [0x73,0x23,0x40,0x25]
213 # CHECK-INST-ALIAS: csrr t1, vsiph
215 # CHECK-INST: csrrs t2, vsiph, zero
216 # CHECK-ENC: encoding: [0xf3,0x23,0x40,0x25]
217 # CHECK-INST-ALIAS: csrr t2, vsiph
219 csrrs t1
, vsiph
, zero
221 csrrs t2
, 0x254, zero