llvm/test/MC/RISCV/rv64zfinx-valid.s

   1 # RUN: llvm-mc %s -triple=riscv64 -mattr=+zfinx -riscv-no-aliases -show-encoding \
   2 # RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
   3 # RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zfinx %s \
   4 # RUN:     | llvm-objdump --mattr=+zfinx -M no-aliases -d -r - \
   5 # RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
   6 #
   7 # RUN: not llvm-mc -triple riscv32 -mattr=+zfinx %s 2>&1 \
   8 # RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
   9
  10 # CHECK-ASM-AND-OBJ: fcvt.l.s a0, t0, dyn
  11 # CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc0]
  12 # CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
  13 fcvt.l.s a0, t0, dyn
  14 # CHECK-ASM-AND-OBJ: fcvt.lu.s a1, t1, dyn
  15 # CHECK-ASM: encoding: [0xd3,0x75,0x33,0xc0]
  16 # CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
  17 fcvt.lu.s a1, t1, dyn
  18 # CHECK-ASM-AND-OBJ: fcvt.s.l t2, a2, dyn
  19 # CHECK-ASM: encoding: [0xd3,0x73,0x26,0xd0]
  20 # CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
  21 fcvt.s.l t2, a2, dyn
  22 # CHECK-ASM-AND-OBJ: fcvt.s.lu t3, a3, dyn
  23 # CHECK-ASM: encoding: [0x53,0xfe,0x36,0xd0]
  24 # CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
  25 fcvt.s.lu t3, a3, dyn
  26
  27 # Rounding modes
  28 # CHECK-ASM-AND-OBJ: fcvt.l.s a4, t4, rne
  29 # CHECK-ASM: encoding: [0x53,0x87,0x2e,0xc0]
  30 # CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
  31 fcvt.l.s a4, t4, rne
  32 # CHECK-ASM-AND-OBJ: fcvt.lu.s a5, t5, rtz
  33 # CHECK-ASM: encoding: [0xd3,0x17,0x3f,0xc0]
  34 # CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
  35 fcvt.lu.s a5, t5, rtz
  36 # CHECK-ASM-AND-OBJ: fcvt.s.l t6, a6, rdn
  37 # CHECK-ASM: encoding: [0xd3,0x2f,0x28,0xd0]
  38 # CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
  39 fcvt.s.l t6, a6, rdn
  40 # CHECK-ASM-AND-OBJ: fcvt.s.lu s7, a7, rup
  41 # CHECK-ASM: encoding: [0xd3,0xbb,0x38,0xd0]
  42 # CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
  43 fcvt.s.lu s7, a7, rup