llvm/test/MC/RISCV/xsfcie-valid.s

   1 # SCIE - SiFive Custom Instructions Extension.
   2 # RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
   3 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
   4 # RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding \
   5 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
   6 # RUN: llvm-mc %s -triple=riscv32 -mattr=+xsfcie -riscv-no-aliases -show-encoding 2>&1 \
   7 # RUN:     | FileCheck -check-prefixes=CHECK-WARN %s
   8 # RUN: llvm-mc %s -triple=riscv64 -mattr=+xsfcie -riscv-no-aliases -show-encoding 2>&1 \
   9 # RUN:     | FileCheck -check-prefixes=CHECK-WARN %s
  10 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xsfcie < %s \
  11 # RUN:     | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
  12 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
  13 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+xsfcie < %s \
  14 # RUN:     | llvm-objdump --mattr=+xsfcie -M no-aliases -d - \
  15 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
  16 # RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding \
  17 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s
  18 # RUN: llvm-mc %s -triple=riscv64 -mcpu=sifive-s76 -riscv-no-aliases -show-encoding 2>&1 \
  19 # RUN:     | FileCheck -check-prefixes=CHECK-WARN %s
  20 # RUN: llvm-mc -filetype=obj -triple riscv64 -mcpu=sifive-s76 < %s \
  21 # RUN:     | llvm-objdump --mcpu=sifive-s76 -M no-aliases -d - \
  22 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
  23
  24 # CHECK-INST: cflush.d.l1     zero
  25 # CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
  26 # CHECK-INST: cflush.d.l1     zero
  27 # CHECK-ENC: encoding: [0x73,0x00,0x00,0xfc]
  28 cflush.d.l1 x0
  29 cflush.d.l1
  30
  31 # CHECK-INST: cflush.d.l1     t2
  32 # CHECK-ENC: encoding: [0x73,0x80,0x03,0xfc]
  33 cflush.d.l1 x7
  34
  35 # CHECK-INST: cdiscard.d.l1   zero
  36 # CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
  37 # CHECK-INST: cdiscard.d.l1     zero
  38 # CHECK-ENC: encoding: [0x73,0x00,0x20,0xfc]
  39 cdiscard.d.l1 x0
  40 cdiscard.d.l1
  41
  42 # CHECK-INST: cdiscard.d.l1   t2
  43 # CHECK-ENC: encoding: [0x73,0x80,0x23,0xfc]
  44 cdiscard.d.l1 x7
  45
  46 # CHECK-INST: cease
  47 # CHECK-ENC: encoding: [0x73,0x00,0x50,0x30]
  48 cease
  49
  50 # mbpm
  51 # name
  52 # CHECK-INST: csrrs t2, mbpm, zero
  53 # CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
  54 # uimm12
  55 # CHECK-INST: csrrs t2, mbpm, zero
  56 # CHECK-ENC: encoding: [0xf3,0x23,0x00,0x7c]
  57 # name
  58 csrrs t2, mbpm, zero
  59 # uimm12
  60 csrrs t2, 0x7C0, zero
  61
  62 # mfd
  63 # name
  64 # CHECK-INST: csrrs t2, mfd, zero
  65 # CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
  66 # uimm12
  67 # CHECK-INST: csrrs t2, mfd, zero
  68 # CHECK-ENC: encoding: [0xf3,0x23,0x10,0x7c]
  69 # name
  70 csrrs t2, mfd, zero
  71 # uimm12
  72 csrrs t2, 0x7C1, zero
  73
  74 # mpd
  75 # name
  76 # CHECK-INST: csrrs t2, mpd, zero
  77 # CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
  78 # uimm12
  79 # CHECK-INST: csrrs t2, mpd, zero
  80 # CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7c]
  81 # name
  82 csrrs t2, mpd, zero
  83 # uimm12
  84 csrrs t2, 0x7C8, zero
  85
  86 # mnscratch
  87 # name
  88 # CHECK-INST: csrrs t1, mnscratch, zero
  89 # CHECK-ENC: encoding: [0x73,0x23,0x00,0x35]
  90 # CHECK-WARN: warning: 'miselect' CSR is not available on the current subtarget. Instead 'mnscratch' CSR will be used.
  91 # uimm12
  92 # CHECK-INST: csrrs t2, mnscratch, zero
  93 # CHECK-ENC: encoding: [0xf3,0x23,0x00,0x35]
  94 # name
  95 csrrs t1, mnscratch, zero
  96 csrrs t1, miselect, zero
  97 # uimm12
  98 csrrs t2, 0x350, zero
  99
 100 # mnepc
 101 # name
 102 # CHECK-INST: csrrs t1, mnepc, zero
 103 # CHECK-ENC: encoding: [0x73,0x23,0x10,0x35]
 104 # CHECK-WARN: warning: 'mireg' CSR is not available on the current subtarget. Instead 'mnepc' CSR will be used.
 105 # uimm12
 106 # CHECK-INST: csrrs t2, mnepc, zero
 107 # CHECK-ENC: encoding: [0xf3,0x23,0x10,0x35]
 108 # name
 109 csrrs t1, mnepc, zero
 110 csrrs t1, mireg, zero
 111 # uimm12
 112 csrrs t2, 0x351, zero
 113
 114 # mncause
 115 # name
 116 # CHECK-INST: csrrs t1, mncause, zero
 117 # CHECK-ENC: encoding: [0x73,0x23,0x20,0x35]
 118 # uimm12
 119 # CHECK-INST: csrrs t2, mncause, zero
 120 # CHECK-ENC: encoding: [0xf3,0x23,0x20,0x35]
 121 # name
 122 csrrs t1, mncause, zero
 123 # uimm12
 124 csrrs t2, 0x352, zero
 125
 126 # mnstatus
 127 # name
 128 # CHECK-INST: csrrs t1, mnstatus, zero
 129 # CHECK-ENC: encoding: [0x73,0x23,0x30,0x35]
 130 # uimm12
 131 # CHECK-INST: csrrs t2, mnstatus, zero
 132 # CHECK-ENC: encoding: [0xf3,0x23,0x30,0x35]
 133 # name
 134 csrrs t1, mnstatus, zero
 135 # uimm12
 136 csrrs t2, 0x353, zero