1 # REQUIRES: aarch64-registered-target
2 # RUN: not --crash llc -verify-machineinstrs -mtriple aarch64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
10 %bank:gpr(s32) = COPY $w0
11 %class:gpr32(s32) = COPY $w1
13 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***
14 ; CHECK: instruction: %bank_mismatch:fpr(s32) = G_ASSERT_ZEXT %bank:gpr, 16
15 %bank_mismatch:fpr(s32) = G_ASSERT_ZEXT %bank, 16
17 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT source and destination register classes must match ***
18 ; CHECK: instruction: %class_mismatch_gpr:gpr32all(s32) = G_ASSERT_ZEXT %class:gpr32, 16
19 %class_mismatch_gpr:gpr32all(s32) = G_ASSERT_ZEXT %class, 16
21 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***
22 ; CHECK: instruction: %class_mismatch_fpr:fpr32(s32) = G_ASSERT_ZEXT %class:gpr32, 16
23 %class_mismatch_fpr:fpr32(s32) = G_ASSERT_ZEXT %class, 16
25 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT source and destination register classes must match ***
26 ; CHECK: instruction: %dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_ZEXT %bank:gpr, 16
27 %dst_has_class_src_has_bank:gpr32all(s32) = G_ASSERT_ZEXT %bank, 16
29 ; CHECK: *** Bad machine code: Generic instruction cannot have physical register ***
30 ; CHECK: instruction: %implicit_physreg:gpr(s32) = G_ASSERT_ZEXT %class:gpr32, 16, implicit-def $w0
31 %implicit_physreg:gpr(s32) = G_ASSERT_ZEXT %class, 16, implicit-def $w0
33 %nothing:_(s32) = G_IMPLICIT_DEF
35 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***
36 ; CHECK: %only_dst_has_bank:gpr(s32) = G_ASSERT_ZEXT %nothing:_, 4
37 %only_dst_has_bank:gpr(s32) = G_ASSERT_ZEXT %nothing, 4
39 ; CHECK: *** Bad machine code: G_ASSERT_ZEXT cannot change register bank ***
40 ; CHECK: %only_dst_has_class:gpr32all(s32) = G_ASSERT_ZEXT %nothing:_, 4
41 %only_dst_has_class:gpr32all(s32) = G_ASSERT_ZEXT %nothing, 4