llvm/test/tools/llvm-mca/X86/BdVer2/register-files-3.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -register-file-size=5 -iterations=2 -dispatch-stats -register-file-stats -timeline < %s | FileCheck %s
   3
   4 idiv %eax
   5
   6 # CHECK:      Iterations:        2
   7 # CHECK-NEXT: Instructions:      2
   8 # CHECK-NEXT: Total Cycles:      42
   9 # CHECK-NEXT: Total uOps:        4
  10
  11 # CHECK:      Dispatch Width:    4
  12 # CHECK-NEXT: uOps Per Cycle:    0.10
  13 # CHECK-NEXT: IPC:               0.05
  14 # CHECK-NEXT: Block RThroughput: 25.0
  15
  16 # CHECK:      Instruction Info:
  17 # CHECK-NEXT: [1]: #uOps
  18 # CHECK-NEXT: [2]: Latency
  19 # CHECK-NEXT: [3]: RThroughput
  20 # CHECK-NEXT: [4]: MayLoad
  21 # CHECK-NEXT: [5]: MayStore
  22 # CHECK-NEXT: [6]: HasSideEffects (U)
  23
  24 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  25 # CHECK-NEXT:  2      14    25.00                 U     idivl   %eax
  26
  27 # CHECK:      Dynamic Dispatch Stall Cycles:
  28 # CHECK-NEXT: RAT     - Register unavailable:                      16  (38.1%)
  29 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 0
  30 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
  31 # CHECK-NEXT: LQ      - Load queue full:                           0
  32 # CHECK-NEXT: SQ      - Store queue full:                          0
  33 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
  34 # CHECK-NEXT: USH     - Uncategorised Structural Hazard:           0
  35
  36 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
  37 # CHECK-NEXT: [# dispatched], [# cycles]
  38 # CHECK-NEXT:  0,              40  (95.2%)
  39 # CHECK-NEXT:  2,              2  (4.8%)
  40
  41 # CHECK:      Register File statistics:
  42 # CHECK-NEXT: Total number of mappings created:    6
  43 # CHECK-NEXT: Max number of mappings used:         3
  44
  45 # CHECK:      *  Register File #1 -- PdFpuPRF:
  46 # CHECK-NEXT:    Number of physical registers:     160
  47 # CHECK-NEXT:    Total number of mappings created: 0
  48 # CHECK-NEXT:    Max number of mappings used:      0
  49
  50 # CHECK:      *  Register File #2 -- PdIntegerPRF:
  51 # CHECK-NEXT:    Number of physical registers:     96
  52 # CHECK-NEXT:    Total number of mappings created: 6
  53 # CHECK-NEXT:    Max number of mappings used:      3
  54
  55 # CHECK:      Resources:
  56 # CHECK-NEXT: [0.0] - PdAGLU01
  57 # CHECK-NEXT: [0.1] - PdAGLU01
  58 # CHECK-NEXT: [1]   - PdBranch
  59 # CHECK-NEXT: [2]   - PdCount
  60 # CHECK-NEXT: [3]   - PdDiv
  61 # CHECK-NEXT: [4]   - PdEX0
  62 # CHECK-NEXT: [5]   - PdEX1
  63 # CHECK-NEXT: [6]   - PdFPCVT
  64 # CHECK-NEXT: [7.0] - PdFPFMA
  65 # CHECK-NEXT: [7.1] - PdFPFMA
  66 # CHECK-NEXT: [8.0] - PdFPMAL
  67 # CHECK-NEXT: [8.1] - PdFPMAL
  68 # CHECK-NEXT: [9]   - PdFPMMA
  69 # CHECK-NEXT: [10]  - PdFPSTO
  70 # CHECK-NEXT: [11]  - PdFPU0
  71 # CHECK-NEXT: [12]  - PdFPU1
  72 # CHECK-NEXT: [13]  - PdFPU2
  73 # CHECK-NEXT: [14]  - PdFPU3
  74 # CHECK-NEXT: [15]  - PdFPXBR
  75 # CHECK-NEXT: [16.0] - PdLoad
  76 # CHECK-NEXT: [16.1] - PdLoad
  77 # CHECK-NEXT: [17]  - PdMul
  78 # CHECK-NEXT: [18]  - PdStore
  79
  80 # CHECK:      Resource pressure per iteration:
  81 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]
  82 # CHECK-NEXT:  -      -      -      -     25.00   -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -
  83
  84 # CHECK:      Resource pressure by instruction:
  85 # CHECK-NEXT: [0.0]  [0.1]  [1]    [2]    [3]    [4]    [5]    [6]    [7.0]  [7.1]  [8.0]  [8.1]  [9]    [10]   [11]   [12]   [13]   [14]   [15]   [16.0] [16.1] [17]   [18]   Instructions:
  86 # CHECK-NEXT:  -      -      -      -     25.00   -     1.00    -      -      -      -      -      -      -      -      -      -      -      -      -      -      -      -     idivl    %eax
  87
  88 # CHECK:      Timeline view:
  89 # CHECK-NEXT:                     0123456789          0123456789
  90 # CHECK-NEXT: Index     0123456789          0123456789          01
  91
  92 # CHECK:      [0,0]     DeeeeeeeeeeeeeeER   .    .    .    .    ..   idivl      %eax
  93 # CHECK-NEXT: [1,0]     .    .    .    .D=========eeeeeeeeeeeeeeER   idivl      %eax
  94
  95 # CHECK:      Average Wait times (based on the timeline view):
  96 # CHECK-NEXT: [0]: Executions
  97 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  98 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  99 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 100
 101 # CHECK:            [0]    [1]    [2]    [3]
 102 # CHECK-NEXT: 0.     2     5.5    5.5    0.0       idivl        %eax