Run DCE after a LoopFlatten test to reduce spurious output [nfc]
[llvm-project.git] / llvm / unittests / Target / AArch64 / AddressingModes.cpp
blob284ea7ae9233ed175340039a5122aef6ac3ecb29
1 #include "AArch64Subtarget.h"
2 #include "AArch64TargetMachine.h"
3 #include "llvm/IR/DataLayout.h"
4 #include "llvm/MC/TargetRegistry.h"
5 #include "llvm/Support/TargetSelect.h"
7 #include "gtest/gtest.h"
8 #include <initializer_list>
9 #include <memory>
11 using namespace llvm;
13 namespace {
15 struct AddrMode : public TargetLowering::AddrMode {
16 constexpr AddrMode(GlobalValue *GV, int64_t Offs, bool HasBase, int64_t S) {
17 BaseGV = GV;
18 BaseOffs = Offs;
19 HasBaseReg = HasBase;
20 Scale = S;
23 struct TestCase {
24 AddrMode AM;
25 unsigned TypeBits;
26 bool Result;
29 const std::initializer_list<TestCase> Tests = {
30 // {BaseGV, BaseOffs, HasBaseReg, Scale}, Bits, Result
31 {{reinterpret_cast<GlobalValue *>(-1), 0, false, 0}, 64, false},
32 {{nullptr, 8, true, 1}, 64, false},
33 {{nullptr, 0, false, 2}, 64, true},
34 {{nullptr, 0, false, 1}, 64, true},
35 {{nullptr, 4, false, 0}, 64, false},
37 {{nullptr, 0, true, 1}, 64, true},
38 {{nullptr, 0, true, 1}, 32, true},
39 {{nullptr, 0, true, 1}, 16, true},
40 {{nullptr, 0, true, 1}, 8, true},
42 {{nullptr, 0, true, 2}, 64, false},
43 {{nullptr, 0, true, 2}, 32, false},
44 {{nullptr, 0, true, 2}, 16, true},
45 {{nullptr, 0, true, 2}, 8, false},
46 {{nullptr, 0, true, 4}, 64, false},
47 {{nullptr, 0, true, 4}, 32, true},
48 {{nullptr, 0, true, 4}, 16, false},
49 {{nullptr, 0, true, 4}, 8, false},
51 {{nullptr, 0, true, 8}, 64, true},
52 {{nullptr, 0, true, 8}, 32, false},
53 {{nullptr, 0, true, 8}, 16, false},
54 {{nullptr, 0, true, 8}, 8, false},
56 {{nullptr, 0, true, 16}, 64, false},
57 {{nullptr, 0, true, 16}, 32, false},
58 {{nullptr, 0, true, 16}, 16, false},
59 {{nullptr, 0, true, 16}, 8, false},
61 {{nullptr, -257, true, 0}, 64, false},
62 {{nullptr, -256, true, 0}, 64, true},
63 {{nullptr, -255, true, 0}, 64, true},
64 {{nullptr, -1, true, 0}, 64, true},
65 {{nullptr, 0, true, 0}, 64, true},
66 {{nullptr, 1, true, 0}, 64, true},
67 {{nullptr, 254, true, 0}, 64, true},
68 {{nullptr, 255, true, 0}, 64, true},
69 {{nullptr, 256, true, 0}, 64, true},
70 {{nullptr, 257, true, 0}, 64, false},
71 {{nullptr, 258, true, 0}, 64, false},
72 {{nullptr, 259, true, 0}, 64, false},
73 {{nullptr, 260, true, 0}, 64, false},
74 {{nullptr, 261, true, 0}, 64, false},
75 {{nullptr, 262, true, 0}, 64, false},
76 {{nullptr, 263, true, 0}, 64, false},
77 {{nullptr, 264, true, 0}, 64, true},
79 {{nullptr, 4096 * 8 - 8, true, 0}, 64, true},
80 {{nullptr, 4096 * 8 - 7, true, 0}, 64, false},
81 {{nullptr, 4096 * 8 - 6, true, 0}, 64, false},
82 {{nullptr, 4096 * 8 - 5, true, 0}, 64, false},
83 {{nullptr, 4096 * 8 - 4, true, 0}, 64, false},
84 {{nullptr, 4096 * 8 - 3, true, 0}, 64, false},
85 {{nullptr, 4096 * 8 - 2, true, 0}, 64, false},
86 {{nullptr, 4096 * 8 - 1, true, 0}, 64, false},
87 {{nullptr, 4096 * 8, true, 0}, 64, false},
88 {{nullptr, 4096 * 8 + 1, true, 0}, 64, false},
89 {{nullptr, 4096 * 8 + 2, true, 0}, 64, false},
90 {{nullptr, 4096 * 8 + 3, true, 0}, 64, false},
91 {{nullptr, 4096 * 8 + 4, true, 0}, 64, false},
92 {{nullptr, 4096 * 8 + 5, true, 0}, 64, false},
93 {{nullptr, 4096 * 8 + 6, true, 0}, 64, false},
94 {{nullptr, 4096 * 8 + 7, true, 0}, 64, false},
95 {{nullptr, 4096 * 8 + 8, true, 0}, 64, false},
97 {{nullptr, -257, true, 0}, 32, false},
98 {{nullptr, -256, true, 0}, 32, true},
99 {{nullptr, -255, true, 0}, 32, true},
100 {{nullptr, -1, true, 0}, 32, true},
101 {{nullptr, 0, true, 0}, 32, true},
102 {{nullptr, 1, true, 0}, 32, true},
103 {{nullptr, 254, true, 0}, 32, true},
104 {{nullptr, 255, true, 0}, 32, true},
105 {{nullptr, 256, true, 0}, 32, true},
106 {{nullptr, 257, true, 0}, 32, false},
107 {{nullptr, 258, true, 0}, 32, false},
108 {{nullptr, 259, true, 0}, 32, false},
109 {{nullptr, 260, true, 0}, 32, true},
111 {{nullptr, 4096 * 4 - 4, true, 0}, 32, true},
112 {{nullptr, 4096 * 4 - 3, true, 0}, 32, false},
113 {{nullptr, 4096 * 4 - 2, true, 0}, 32, false},
114 {{nullptr, 4096 * 4 - 1, true, 0}, 32, false},
115 {{nullptr, 4096 * 4, true, 0}, 32, false},
116 {{nullptr, 4096 * 4 + 1, true, 0}, 32, false},
117 {{nullptr, 4096 * 4 + 2, true, 0}, 32, false},
118 {{nullptr, 4096 * 4 + 3, true, 0}, 32, false},
119 {{nullptr, 4096 * 4 + 4, true, 0}, 32, false},
121 {{nullptr, -257, true, 0}, 16, false},
122 {{nullptr, -256, true, 0}, 16, true},
123 {{nullptr, -255, true, 0}, 16, true},
124 {{nullptr, -1, true, 0}, 16, true},
125 {{nullptr, 0, true, 0}, 16, true},
126 {{nullptr, 1, true, 0}, 16, true},
127 {{nullptr, 254, true, 0}, 16, true},
128 {{nullptr, 255, true, 0}, 16, true},
129 {{nullptr, 256, true, 0}, 16, true},
130 {{nullptr, 257, true, 0}, 16, false},
131 {{nullptr, 258, true, 0}, 16, true},
133 {{nullptr, 4096 * 2 - 2, true, 0}, 16, true},
134 {{nullptr, 4096 * 2 - 1, true, 0}, 16, false},
135 {{nullptr, 4096 * 2, true, 0}, 16, false},
136 {{nullptr, 4096 * 2 + 1, true, 0}, 16, false},
137 {{nullptr, 4096 * 2 + 2, true, 0}, 16, false},
139 {{nullptr, -257, true, 0}, 8, false},
140 {{nullptr, -256, true, 0}, 8, true},
141 {{nullptr, -255, true, 0}, 8, true},
142 {{nullptr, -1, true, 0}, 8, true},
143 {{nullptr, 0, true, 0}, 8, true},
144 {{nullptr, 1, true, 0}, 8, true},
145 {{nullptr, 254, true, 0}, 8, true},
146 {{nullptr, 255, true, 0}, 8, true},
147 {{nullptr, 256, true, 0}, 8, true},
148 {{nullptr, 257, true, 0}, 8, true},
150 {{nullptr, 4096 - 2, true, 0}, 8, true},
151 {{nullptr, 4096 - 1, true, 0}, 8, true},
152 {{nullptr, 4096, true, 0}, 8, false},
153 {{nullptr, 4096 + 1, true, 0}, 8, false},
156 } // namespace
158 TEST(AddressingModes, AddressingModes) {
159 LLVMInitializeAArch64TargetInfo();
160 LLVMInitializeAArch64Target();
161 LLVMInitializeAArch64TargetMC();
163 std::string Error;
164 auto TT = Triple::normalize("aarch64");
165 const Target *T = TargetRegistry::lookupTarget(TT, Error);
167 std::unique_ptr<TargetMachine> TM(
168 T->createTargetMachine(TT, "generic", "", TargetOptions(), std::nullopt,
169 std::nullopt, CodeGenOptLevel::Default));
170 AArch64Subtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
171 TM->getTargetCPU(), TM->getTargetFeatureString(), *TM,
172 true);
174 auto *TLI = ST.getTargetLowering();
175 DataLayout DL("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
176 LLVMContext Ctx;
178 for (const auto &Test : Tests) {
179 Type *Typ = Type::getIntNTy(Ctx, Test.TypeBits);
180 ASSERT_EQ(TLI->isLegalAddressingMode(DL, Test.AM, Typ, 0), Test.Result);