llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp

   1 //===- llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp ------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "AMDGPUTargetMachine.h"
  10 #include "AMDGPUUnitTests.h"
  11 #include "gtest/gtest.h"
  12
  13 using namespace llvm;
  14
  15 TEST(AMDGPU, TestWave64DwarfRegMapping) {
  16   for (auto Triple :
  17        {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
  18     auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize64");
  19     if (TM) {
  20       GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
  21                       std::string(TM->getTargetFeatureString()), *TM);
  22       auto MRI = ST.getRegisterInfo();
  23       if (MRI) {
  24         // Wave64 Dwarf register mapping test numbers
  25         // PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
  26         // S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
  27         // A0 => 3072, A255 => 3327
  28         for (int llvmReg :
  29              {16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
  30           MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
  31           EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
  32         }
  33       }
  34     }
  35   }
  36 }
  37
  38 TEST(AMDGPU, TestWave32DwarfRegMapping) {
  39   for (auto Triple :
  40        {"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
  41     auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
  42     if (TM) {
  43       GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
  44                       std::string(TM->getTargetFeatureString()), *TM);
  45       auto MRI = ST.getRegisterInfo();
  46       if (MRI) {
  47         // Wave32 Dwarf register mapping test numbers
  48         // PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
  49         // S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
  50         // A0 => 2048, A255 => 2303
  51         for (int llvmReg :
  52              {16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
  53           MCRegister PCReg(*MRI->getLLVMRegNum(llvmReg, false));
  54           EXPECT_EQ(llvmReg, MRI->getDwarfRegNum(PCReg, false));
  55         }
  56       }
  57     }
  58   }
  59 }