llvm/utils/TableGen/CodeGenSchedule.h

   1 //===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines structures to encapsulate the machine model as described in
  10 // the target description.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
  15 #define LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
  16
  17 #include "llvm/ADT/APInt.h"
  18 #include "llvm/ADT/ArrayRef.h"
  19 #include "llvm/ADT/DenseMap.h"
  20 #include "llvm/ADT/DenseSet.h"
  21 #include "llvm/ADT/STLExtras.h"
  22 #include "llvm/ADT/StringRef.h"
  23 #include "llvm/TableGen/Record.h"
  24 #include "llvm/TableGen/SetTheory.h"
  25 #include <cassert>
  26 #include <string>
  27 #include <utility>
  28 #include <vector>
  29
  30 namespace llvm {
  31
  32 class CodeGenTarget;
  33 class CodeGenSchedModels;
  34 class CodeGenInstruction;
  35
  36 using RecVec = std::vector<Record*>;
  37 using RecIter = std::vector<Record*>::const_iterator;
  38
  39 using IdxVec = std::vector<unsigned>;
  40 using IdxIter = std::vector<unsigned>::const_iterator;
  41
  42 /// We have two kinds of SchedReadWrites. Explicitly defined and inferred
  43 /// sequences.  TheDef is nonnull for explicit SchedWrites, but Sequence may or
  44 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
  45 /// be nonempty.
  46 ///
  47 /// IsVariadic controls whether the variants are expanded into multiple operands
  48 /// or a sequence of writes on one operand.
  49 struct CodeGenSchedRW {
  50   unsigned Index;
  51   std::string Name;
  52   Record *TheDef;
  53   bool IsRead;
  54   bool IsAlias;
  55   bool HasVariants;
  56   bool IsVariadic;
  57   bool IsSequence;
  58   IdxVec Sequence;
  59   RecVec Aliases;
  60
  61   CodeGenSchedRW()
  62     : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
  63       HasVariants(false), IsVariadic(false), IsSequence(false) {}
  64   CodeGenSchedRW(unsigned Idx, Record *Def)
  65     : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
  66     Name = std::string(Def->getName());
  67     IsRead = Def->isSubClassOf("SchedRead");
  68     HasVariants = Def->isSubClassOf("SchedVariant");
  69     if (HasVariants)
  70       IsVariadic = Def->getValueAsBit("Variadic");
  71
  72     // Read records don't currently have sequences, but it can be easily
  73     // added. Note that implicit Reads (from ReadVariant) may have a Sequence
  74     // (but no record).
  75     IsSequence = Def->isSubClassOf("WriteSequence");
  76   }
  77
  78   CodeGenSchedRW(unsigned Idx, bool Read, ArrayRef<unsigned> Seq,
  79                  const std::string &Name)
  80       : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
  81         HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
  82     assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
  83   }
  84
  85   bool isValid() const {
  86     assert((!HasVariants || TheDef) && "Variant write needs record def");
  87     assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
  88     assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
  89     assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
  90     assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases");
  91     return TheDef || !Sequence.empty();
  92   }
  93
  94 #ifndef NDEBUG
  95   void dump() const;
  96 #endif
  97 };
  98
  99 /// Represent a transition between SchedClasses induced by SchedVariant.
 100 struct CodeGenSchedTransition {
 101   unsigned ToClassIdx;
 102   unsigned ProcIndex;
 103   RecVec PredTerm;
 104 };
 105
 106 /// Scheduling class.
 107 ///
 108 /// Each instruction description will be mapped to a scheduling class. There are
 109 /// four types of classes:
 110 ///
 111 /// 1) An explicitly defined itinerary class with ItinClassDef set.
 112 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
 113 ///
 114 /// 2) An implied class with a list of SchedWrites and SchedReads that are
 115 /// defined in an instruction definition and which are common across all
 116 /// subtargets. ProcIndices contains 0 for any processor.
 117 ///
 118 /// 3) An implied class with a list of InstRW records that map instructions to
 119 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
 120 /// instructions to this class. ProcIndices contains all the processors that
 121 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
 122 /// still be defined for processors with no InstRW entry.
 123 ///
 124 /// 4) An inferred class represents a variant of another class that may be
 125 /// resolved at runtime. ProcIndices contains the set of processors that may
 126 /// require the class. ProcIndices are propagated through SchedClasses as
 127 /// variants are expanded. Multiple SchedClasses may be inferred from an
 128 /// itinerary class. Each inherits the processor index from the ItinRW record
 129 /// that mapped the itinerary class to the variant Writes or Reads.
 130 struct CodeGenSchedClass {
 131   unsigned Index;
 132   std::string Name;
 133   Record *ItinClassDef;
 134
 135   IdxVec Writes;
 136   IdxVec Reads;
 137   // Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
 138   IdxVec ProcIndices;
 139
 140   std::vector<CodeGenSchedTransition> Transitions;
 141
 142   // InstRW records associated with this class. These records may refer to an
 143   // Instruction no longer mapped to this class by InstrClassMap. These
 144   // Instructions should be ignored by this class because they have been split
 145   // off to join another inferred class.
 146   RecVec InstRWs;
 147   // InstRWs processor indices. Filled in inferFromInstRWs
 148   DenseSet<unsigned> InstRWProcIndices;
 149
 150   CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef)
 151     : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
 152
 153   bool isKeyEqual(Record *IC, ArrayRef<unsigned> W,
 154                   ArrayRef<unsigned> R) const {
 155     return ItinClassDef == IC && ArrayRef(Writes) == W && ArrayRef(Reads) == R;
 156   }
 157
 158   // Is this class generated from a variants if existing classes? Instructions
 159   // are never mapped directly to inferred scheduling classes.
 160   bool isInferred() const { return !ItinClassDef; }
 161
 162 #ifndef NDEBUG
 163   void dump(const CodeGenSchedModels *SchedModels) const;
 164 #endif
 165 };
 166
 167 /// Represent the cost of allocating a register of register class RCDef.
 168 ///
 169 /// The cost of allocating a register is equivalent to the number of physical
 170 /// registers used by the register renamer. Register costs are defined at
 171 /// register class granularity.
 172 struct CodeGenRegisterCost {
 173   Record *RCDef;
 174   unsigned Cost;
 175   bool AllowMoveElimination;
 176   CodeGenRegisterCost(Record *RC, unsigned RegisterCost, bool AllowMoveElim = false)
 177       : RCDef(RC), Cost(RegisterCost), AllowMoveElimination(AllowMoveElim) {}
 178   CodeGenRegisterCost(const CodeGenRegisterCost &) = default;
 179   CodeGenRegisterCost &operator=(const CodeGenRegisterCost &) = delete;
 180 };
 181
 182 /// A processor register file.
 183 ///
 184 /// This class describes a processor register file. Register file information is
 185 /// currently consumed by external tools like llvm-mca to predict dispatch
 186 /// stalls due to register pressure.
 187 struct CodeGenRegisterFile {
 188   std::string Name;
 189   Record *RegisterFileDef;
 190   unsigned MaxMovesEliminatedPerCycle;
 191   bool AllowZeroMoveEliminationOnly;
 192
 193   unsigned NumPhysRegs;
 194   std::vector<CodeGenRegisterCost> Costs;
 195
 196   CodeGenRegisterFile(StringRef name, Record *def, unsigned MaxMoveElimPerCy = 0,
 197                       bool AllowZeroMoveElimOnly = false)
 198       : Name(name), RegisterFileDef(def),
 199         MaxMovesEliminatedPerCycle(MaxMoveElimPerCy),
 200         AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly),
 201         NumPhysRegs(0) {}
 202
 203   bool hasDefaultCosts() const { return Costs.empty(); }
 204 };
 205
 206 // Processor model.
 207 //
 208 // ModelName is a unique name used to name an instantiation of MCSchedModel.
 209 //
 210 // ModelDef is NULL for inferred Models. This happens when a processor defines
 211 // an itinerary but no machine model. If the processor defines neither a machine
 212 // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
 213 // the special "NoModel" field set to true.
 214 //
 215 // ItinsDef always points to a valid record definition, but may point to the
 216 // default NoItineraries. NoItineraries has an empty list of InstrItinData
 217 // records.
 218 //
 219 // ItinDefList orders this processor's InstrItinData records by SchedClass idx.
 220 struct CodeGenProcModel {
 221   unsigned Index;
 222   std::string ModelName;
 223   Record *ModelDef;
 224   Record *ItinsDef;
 225
 226   // Derived members...
 227
 228   // Array of InstrItinData records indexed by a CodeGenSchedClass index.
 229   // This list is empty if the Processor has no value for Itineraries.
 230   // Initialized by collectProcItins().
 231   RecVec ItinDefList;
 232
 233   // Map itinerary classes to per-operand resources.
 234   // This list is empty if no ItinRW refers to this Processor.
 235   RecVec ItinRWDefs;
 236
 237   // List of unsupported feature.
 238   // This list is empty if the Processor has no UnsupportedFeatures.
 239   RecVec UnsupportedFeaturesDefs;
 240
 241   // All read/write resources associated with this processor.
 242   RecVec WriteResDefs;
 243   RecVec ReadAdvanceDefs;
 244
 245   // Per-operand machine model resources associated with this processor.
 246   RecVec ProcResourceDefs;
 247
 248   // List of Register Files.
 249   std::vector<CodeGenRegisterFile> RegisterFiles;
 250
 251   // Optional Retire Control Unit definition.
 252   Record *RetireControlUnit;
 253
 254   // Load/Store queue descriptors.
 255   Record *LoadQueue;
 256   Record *StoreQueue;
 257
 258   CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef,
 259                    Record *IDef) :
 260     Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef),
 261     RetireControlUnit(nullptr), LoadQueue(nullptr), StoreQueue(nullptr) {}
 262
 263   bool hasItineraries() const {
 264     return !ItinsDef->getValueAsListOfDefs("IID").empty();
 265   }
 266
 267   bool hasInstrSchedModel() const {
 268     return !WriteResDefs.empty() || !ItinRWDefs.empty();
 269   }
 270
 271   bool hasExtraProcessorInfo() const {
 272     return RetireControlUnit || LoadQueue || StoreQueue ||
 273            !RegisterFiles.empty();
 274   }
 275
 276   unsigned getProcResourceIdx(Record *PRDef) const;
 277
 278   bool isUnsupported(const CodeGenInstruction &Inst) const;
 279
 280 #ifndef NDEBUG
 281   void dump() const;
 282 #endif
 283 };
 284
 285 /// Used to correlate instructions to MCInstPredicates specified by
 286 /// InstructionEquivalentClass tablegen definitions.
 287 ///
 288 /// Example: a XOR of a register with self, is a known zero-idiom for most
 289 /// X86 processors.
 290 ///
 291 /// Each processor can use a (potentially different) InstructionEquivalenceClass
 292 ///  definition to classify zero-idioms. That means, XORrr is likely to appear
 293 /// in more than one equivalence class (where each class definition is
 294 /// contributed by a different processor).
 295 ///
 296 /// There is no guarantee that the same MCInstPredicate will be used to describe
 297 /// equivalence classes that identify XORrr as a zero-idiom.
 298 ///
 299 /// To be more specific, the requirements for being a zero-idiom XORrr may be
 300 /// different for different processors.
 301 ///
 302 /// Class PredicateInfo identifies a subset of processors that specify the same
 303 /// requirements (i.e. same MCInstPredicate and OperandMask) for an instruction
 304 /// opcode.
 305 ///
 306 /// Back to the example. Field `ProcModelMask` will have one bit set for every
 307 /// processor model that sees XORrr as a zero-idiom, and that specifies the same
 308 /// set of constraints.
 309 ///
 310 /// By construction, there can be multiple instances of PredicateInfo associated
 311 /// with a same instruction opcode. For example, different processors may define
 312 /// different constraints on the same opcode.
 313 ///
 314 /// Field OperandMask can be used as an extra constraint.
 315 /// It may be used to describe conditions that appy only to a subset of the
 316 /// operands of a machine instruction, and the operands subset may not be the
 317 /// same for all processor models.
 318 struct PredicateInfo {
 319   llvm::APInt ProcModelMask; // A set of processor model indices.
 320   llvm::APInt OperandMask;   // An operand mask.
 321   const Record *Predicate;   // MCInstrPredicate definition.
 322   PredicateInfo(llvm::APInt CpuMask, llvm::APInt Operands, const Record *Pred)
 323       : ProcModelMask(CpuMask), OperandMask(Operands), Predicate(Pred) {}
 324
 325   bool operator==(const PredicateInfo &Other) const {
 326     return ProcModelMask == Other.ProcModelMask &&
 327            OperandMask == Other.OperandMask && Predicate == Other.Predicate;
 328   }
 329 };
 330
 331 /// A collection of PredicateInfo objects.
 332 ///
 333 /// There is at least one OpcodeInfo object for every opcode specified by a
 334 /// TIPredicate definition.
 335 class OpcodeInfo {
 336   std::vector<PredicateInfo> Predicates;
 337
 338   OpcodeInfo(const OpcodeInfo &Other) = delete;
 339   OpcodeInfo &operator=(const OpcodeInfo &Other) = delete;
 340
 341 public:
 342   OpcodeInfo() = default;
 343   OpcodeInfo &operator=(OpcodeInfo &&Other) = default;
 344   OpcodeInfo(OpcodeInfo &&Other) = default;
 345
 346   ArrayRef<PredicateInfo> getPredicates() const { return Predicates; }
 347
 348   void addPredicateForProcModel(const llvm::APInt &CpuMask,
 349                                 const llvm::APInt &OperandMask,
 350                                 const Record *Predicate);
 351 };
 352
 353 /// Used to group together tablegen instruction definitions that are subject
 354 /// to a same set of constraints (identified by an instance of OpcodeInfo).
 355 class OpcodeGroup {
 356   OpcodeInfo Info;
 357   std::vector<const Record *> Opcodes;
 358
 359   OpcodeGroup(const OpcodeGroup &Other) = delete;
 360   OpcodeGroup &operator=(const OpcodeGroup &Other) = delete;
 361
 362 public:
 363   OpcodeGroup(OpcodeInfo &&OpInfo) : Info(std::move(OpInfo)) {}
 364   OpcodeGroup(OpcodeGroup &&Other) = default;
 365
 366   void addOpcode(const Record *Opcode) {
 367     assert(!llvm::is_contained(Opcodes, Opcode) && "Opcode already in set!");
 368     Opcodes.push_back(Opcode);
 369   }
 370
 371   ArrayRef<const Record *> getOpcodes() const { return Opcodes; }
 372   const OpcodeInfo &getOpcodeInfo() const { return Info; }
 373 };
 374
 375 /// An STIPredicateFunction descriptor used by tablegen backends to
 376 /// auto-generate the body of a predicate function as a member of tablegen'd
 377 /// class XXXGenSubtargetInfo.
 378 class STIPredicateFunction {
 379   const Record *FunctionDeclaration;
 380
 381   std::vector<const Record *> Definitions;
 382   std::vector<OpcodeGroup> Groups;
 383
 384   STIPredicateFunction(const STIPredicateFunction &Other) = delete;
 385   STIPredicateFunction &operator=(const STIPredicateFunction &Other) = delete;
 386
 387 public:
 388   STIPredicateFunction(const Record *Rec) : FunctionDeclaration(Rec) {}
 389   STIPredicateFunction(STIPredicateFunction &&Other) = default;
 390
 391   bool isCompatibleWith(const STIPredicateFunction &Other) const {
 392     return FunctionDeclaration == Other.FunctionDeclaration;
 393   }
 394
 395   void addDefinition(const Record *Def) { Definitions.push_back(Def); }
 396   void addOpcode(const Record *OpcodeRec, OpcodeInfo &&Info) {
 397     if (Groups.empty() ||
 398         Groups.back().getOpcodeInfo().getPredicates() != Info.getPredicates())
 399       Groups.emplace_back(std::move(Info));
 400     Groups.back().addOpcode(OpcodeRec);
 401   }
 402
 403   StringRef getName() const {
 404     return FunctionDeclaration->getValueAsString("Name");
 405   }
 406   const Record *getDefaultReturnPredicate() const {
 407     return FunctionDeclaration->getValueAsDef("DefaultReturnValue");
 408   }
 409
 410   const Record *getDeclaration() const { return FunctionDeclaration; }
 411   ArrayRef<const Record *> getDefinitions() const { return Definitions; }
 412   ArrayRef<OpcodeGroup> getGroups() const { return Groups; }
 413 };
 414
 415 using ProcModelMapTy = DenseMap<const Record *, unsigned>;
 416
 417 /// Top level container for machine model data.
 418 class CodeGenSchedModels {
 419   RecordKeeper &Records;
 420   const CodeGenTarget &Target;
 421
 422   // Map dag expressions to Instruction lists.
 423   SetTheory Sets;
 424
 425   // List of unique processor models.
 426   std::vector<CodeGenProcModel> ProcModels;
 427
 428   // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
 429   ProcModelMapTy ProcModelMap;
 430
 431   // Per-operand SchedReadWrite types.
 432   std::vector<CodeGenSchedRW> SchedWrites;
 433   std::vector<CodeGenSchedRW> SchedReads;
 434
 435   // List of unique SchedClasses.
 436   std::vector<CodeGenSchedClass> SchedClasses;
 437
 438   // Any inferred SchedClass has an index greater than NumInstrSchedClassses.
 439   unsigned NumInstrSchedClasses;
 440
 441   RecVec ProcResourceDefs;
 442   RecVec ProcResGroups;
 443
 444   // Map each instruction to its unique SchedClass index considering the
 445   // combination of it's itinerary class, SchedRW list, and InstRW records.
 446   using InstClassMapTy = DenseMap<Record*, unsigned>;
 447   InstClassMapTy InstrClassMap;
 448
 449   std::vector<STIPredicateFunction> STIPredicates;
 450   std::vector<unsigned> getAllProcIndices() const;
 451
 452 public:
 453   CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
 454
 455   // iterator access to the scheduling classes.
 456   using class_iterator = std::vector<CodeGenSchedClass>::iterator;
 457   using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator;
 458   class_iterator classes_begin() { return SchedClasses.begin(); }
 459   const_class_iterator classes_begin() const { return SchedClasses.begin(); }
 460   class_iterator classes_end() { return SchedClasses.end(); }
 461   const_class_iterator classes_end() const { return SchedClasses.end(); }
 462   iterator_range<class_iterator> classes() {
 463    return make_range(classes_begin(), classes_end());
 464   }
 465   iterator_range<const_class_iterator> classes() const {
 466    return make_range(classes_begin(), classes_end());
 467   }
 468   iterator_range<class_iterator> explicit_classes() {
 469     return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
 470   }
 471   iterator_range<const_class_iterator> explicit_classes() const {
 472     return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
 473   }
 474
 475   Record *getModelOrItinDef(Record *ProcDef) const {
 476     Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
 477     Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
 478     if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
 479       assert(ModelDef->getValueAsBit("NoModel")
 480              && "Itineraries must be defined within SchedMachineModel");
 481       return ItinsDef;
 482     }
 483     return ModelDef;
 484   }
 485
 486   const CodeGenProcModel &getModelForProc(Record *ProcDef) const {
 487     Record *ModelDef = getModelOrItinDef(ProcDef);
 488     ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
 489     assert(I != ProcModelMap.end() && "missing machine model");
 490     return ProcModels[I->second];
 491   }
 492
 493   CodeGenProcModel &getProcModel(Record *ModelDef) {
 494     ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
 495     assert(I != ProcModelMap.end() && "missing machine model");
 496     return ProcModels[I->second];
 497   }
 498   const CodeGenProcModel &getProcModel(Record *ModelDef) const {
 499     return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
 500   }
 501
 502   // Iterate over the unique processor models.
 503   using ProcIter = std::vector<CodeGenProcModel>::const_iterator;
 504   ProcIter procModelBegin() const { return ProcModels.begin(); }
 505   ProcIter procModelEnd() const { return ProcModels.end(); }
 506   ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; }
 507
 508   // Return true if any processors have itineraries.
 509   bool hasItineraries() const;
 510
 511   // Get a SchedWrite from its index.
 512   const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
 513     assert(Idx < SchedWrites.size() && "bad SchedWrite index");
 514     assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
 515     return SchedWrites[Idx];
 516   }
 517   // Get a SchedWrite from its index.
 518   const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
 519     assert(Idx < SchedReads.size() && "bad SchedRead index");
 520     assert(SchedReads[Idx].isValid() && "invalid SchedRead");
 521     return SchedReads[Idx];
 522   }
 523
 524   const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
 525     return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
 526   }
 527   CodeGenSchedRW &getSchedRW(Record *Def) {
 528     bool IsRead = Def->isSubClassOf("SchedRead");
 529     unsigned Idx = getSchedRWIdx(Def, IsRead);
 530     return const_cast<CodeGenSchedRW&>(
 531       IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
 532   }
 533   const CodeGenSchedRW &getSchedRW(Record *Def) const {
 534     return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
 535   }
 536
 537   unsigned getSchedRWIdx(const Record *Def, bool IsRead) const;
 538
 539   // Return true if the given write record is referenced by a ReadAdvance.
 540   bool hasReadOfWrite(Record *WriteDef) const;
 541
 542   // Get a SchedClass from its index.
 543   CodeGenSchedClass &getSchedClass(unsigned Idx) {
 544     assert(Idx < SchedClasses.size() && "bad SchedClass index");
 545     return SchedClasses[Idx];
 546   }
 547   const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
 548     assert(Idx < SchedClasses.size() && "bad SchedClass index");
 549     return SchedClasses[Idx];
 550   }
 551
 552   // Get the SchedClass index for an instruction. Instructions with no
 553   // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
 554   // for NoItinerary.
 555   unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
 556
 557   using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator;
 558   SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
 559   SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
 560   ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; }
 561
 562   unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
 563
 564   void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
 565   void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
 566   void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
 567   void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
 568                           const CodeGenProcModel &ProcModel) const;
 569
 570   unsigned addSchedClass(Record *ItinDef, ArrayRef<unsigned> OperWrites,
 571                          ArrayRef<unsigned> OperReads,
 572                          ArrayRef<unsigned> ProcIndices);
 573
 574   unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead);
 575
 576   Record *findProcResUnits(Record *ProcResKind, const CodeGenProcModel &PM,
 577                            ArrayRef<SMLoc> Loc) const;
 578
 579   ArrayRef<STIPredicateFunction> getSTIPredicates() const {
 580     return STIPredicates;
 581   }
 582 private:
 583   void collectProcModels();
 584
 585   // Initialize a new processor model if it is unique.
 586   void addProcModel(Record *ProcDef);
 587
 588   void collectSchedRW();
 589
 590   std::string genRWName(ArrayRef<unsigned> Seq, bool IsRead);
 591   unsigned findRWForSequence(ArrayRef<unsigned> Seq, bool IsRead);
 592
 593   void collectSchedClasses();
 594
 595   void collectRetireControlUnits();
 596
 597   void collectRegisterFiles();
 598
 599   void collectOptionalProcessorInfo();
 600
 601   std::string createSchedClassName(Record *ItinClassDef,
 602                                    ArrayRef<unsigned> OperWrites,
 603                                    ArrayRef<unsigned> OperReads);
 604   std::string createSchedClassName(const RecVec &InstDefs);
 605   void createInstRWClass(Record *InstRWDef);
 606
 607   void collectProcItins();
 608
 609   void collectProcItinRW();
 610
 611   void collectProcUnsupportedFeatures();
 612
 613   void inferSchedClasses();
 614
 615   void checkMCInstPredicates() const;
 616
 617   void checkSTIPredicates() const;
 618
 619   void collectSTIPredicates();
 620
 621   void collectLoadStoreQueueInfo();
 622
 623   void checkCompleteness();
 624
 625   void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads,
 626                    unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices);
 627   void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
 628   void inferFromInstRWs(unsigned SCIdx);
 629
 630   bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM);
 631   void verifyProcResourceGroups(CodeGenProcModel &PM);
 632
 633   void collectProcResources();
 634
 635   void collectItinProcResources(Record *ItinClassDef);
 636
 637   void collectRWResources(unsigned RWIdx, bool IsRead,
 638                           ArrayRef<unsigned> ProcIndices);
 639
 640   void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
 641                           ArrayRef<unsigned> ProcIndices);
 642
 643   void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM,
 644                        ArrayRef<SMLoc> Loc);
 645
 646   void addWriteRes(Record *ProcWriteResDef, unsigned PIdx);
 647
 648   void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx);
 649 };
 650
 651 } // namespace llvm
 652
 653 #endif