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Run DCE after a LoopFlatten test to reduce spurious output [nfc]
[llvm-project.git] / llvm / utils / TableGen / CodeGenTarget.cpp
blob53efa66f9dfc1b428624ec795e3a0ef5e7a6f5be
1 //===- CodeGenTarget.cpp - CodeGen Target Class Wrapper -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This class wraps target description classes used by the various code
10 // generation TableGen backends. This makes it easier to access the data and
11 // provides a single place that needs to check it for validity. All of these
12 // classes abort on error conditions.
13 //
14 //===----------------------------------------------------------------------===//
15
16 #include "CodeGenTarget.h"
17 #include "CodeGenInstruction.h"
18 #include "CodeGenRegisters.h"
19 #include "CodeGenSchedule.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Twine.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/TableGen/Error.h"
25 #include "llvm/TableGen/Record.h"
26 #include <algorithm>
27 #include <iterator>
28 #include <tuple>
29 using namespace llvm;
30
31 cl::OptionCategory AsmParserCat("Options for -gen-asm-parser");
32 cl::OptionCategory AsmWriterCat("Options for -gen-asm-writer");
33
34 static cl::opt<unsigned>
35 AsmParserNum("asmparsernum", cl::init(0),
36 cl::desc("Make -gen-asm-parser emit assembly parser #N"),
37 cl::cat(AsmParserCat));
38
39 static cl::opt<unsigned>
40 AsmWriterNum("asmwriternum", cl::init(0),
41 cl::desc("Make -gen-asm-writer emit assembly writer #N"),
42 cl::cat(AsmWriterCat));
43
44 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
45 /// record corresponds to.
46 MVT::SimpleValueType llvm::getValueType(const Record *Rec) {
47 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
48 }
49
50 StringRef llvm::getName(MVT::SimpleValueType T) {
51 switch (T) {
52 case MVT::Other: return "UNKNOWN";
53 case MVT::iPTR: return "TLI.getPointerTy()";
54 case MVT::iPTRAny: return "TLI.getPointerTy()";
55 default: return getEnumName(T);
56 }
57 }
58
59 StringRef llvm::getEnumName(MVT::SimpleValueType T) {
60 // clang-format off
61 switch (T) {
62 case MVT::Other: return "MVT::Other";
63 case MVT::i1: return "MVT::i1";
64 case MVT::i2: return "MVT::i2";
65 case MVT::i4: return "MVT::i4";
66 case MVT::i8: return "MVT::i8";
67 case MVT::i16: return "MVT::i16";
68 case MVT::i32: return "MVT::i32";
69 case MVT::i64: return "MVT::i64";
70 case MVT::i128: return "MVT::i128";
71 case MVT::Any: return "MVT::Any";
72 case MVT::iAny: return "MVT::iAny";
73 case MVT::fAny: return "MVT::fAny";
74 case MVT::vAny: return "MVT::vAny";
75 case MVT::f16: return "MVT::f16";
76 case MVT::bf16: return "MVT::bf16";
77 case MVT::f32: return "MVT::f32";
78 case MVT::f64: return "MVT::f64";
79 case MVT::f80: return "MVT::f80";
80 case MVT::f128: return "MVT::f128";
81 case MVT::ppcf128: return "MVT::ppcf128";
82 case MVT::x86mmx: return "MVT::x86mmx";
83 case MVT::x86amx: return "MVT::x86amx";
84 case MVT::aarch64svcount: return "MVT::aarch64svcount";
85 case MVT::i64x8: return "MVT::i64x8";
86 case MVT::Glue: return "MVT::Glue";
87 case MVT::isVoid: return "MVT::isVoid";
88 case MVT::v1i1: return "MVT::v1i1";
89 case MVT::v2i1: return "MVT::v2i1";
90 case MVT::v4i1: return "MVT::v4i1";
91 case MVT::v8i1: return "MVT::v8i1";
92 case MVT::v16i1: return "MVT::v16i1";
93 case MVT::v32i1: return "MVT::v32i1";
94 case MVT::v64i1: return "MVT::v64i1";
95 case MVT::v128i1: return "MVT::v128i1";
96 case MVT::v256i1: return "MVT::v256i1";
97 case MVT::v512i1: return "MVT::v512i1";
98 case MVT::v1024i1: return "MVT::v1024i1";
99 case MVT::v2048i1: return "MVT::v2048i1";
100 case MVT::v128i2: return "MVT::v128i2";
101 case MVT::v256i2: return "MVT::v256i2";
102 case MVT::v64i4: return "MVT::v64i4";
103 case MVT::v128i4: return "MVT::v128i4";
104 case MVT::v1i8: return "MVT::v1i8";
105 case MVT::v2i8: return "MVT::v2i8";
106 case MVT::v4i8: return "MVT::v4i8";
107 case MVT::v8i8: return "MVT::v8i8";
108 case MVT::v16i8: return "MVT::v16i8";
109 case MVT::v32i8: return "MVT::v32i8";
110 case MVT::v64i8: return "MVT::v64i8";
111 case MVT::v128i8: return "MVT::v128i8";
112 case MVT::v256i8: return "MVT::v256i8";
113 case MVT::v512i8: return "MVT::v512i8";
114 case MVT::v1024i8: return "MVT::v1024i8";
115 case MVT::v1i16: return "MVT::v1i16";
116 case MVT::v2i16: return "MVT::v2i16";
117 case MVT::v3i16: return "MVT::v3i16";
118 case MVT::v4i16: return "MVT::v4i16";
119 case MVT::v8i16: return "MVT::v8i16";
120 case MVT::v16i16: return "MVT::v16i16";
121 case MVT::v32i16: return "MVT::v32i16";
122 case MVT::v64i16: return "MVT::v64i16";
123 case MVT::v128i16: return "MVT::v128i16";
124 case MVT::v256i16: return "MVT::v256i16";
125 case MVT::v512i16: return "MVT::v512i16";
126 case MVT::v1i32: return "MVT::v1i32";
127 case MVT::v2i32: return "MVT::v2i32";
128 case MVT::v3i32: return "MVT::v3i32";
129 case MVT::v4i32: return "MVT::v4i32";
130 case MVT::v5i32: return "MVT::v5i32";
131 case MVT::v6i32: return "MVT::v6i32";
132 case MVT::v7i32: return "MVT::v7i32";
133 case MVT::v8i32: return "MVT::v8i32";
134 case MVT::v9i32: return "MVT::v9i32";
135 case MVT::v10i32: return "MVT::v10i32";
136 case MVT::v11i32: return "MVT::v11i32";
137 case MVT::v12i32: return "MVT::v12i32";
138 case MVT::v16i32: return "MVT::v16i32";
139 case MVT::v32i32: return "MVT::v32i32";
140 case MVT::v64i32: return "MVT::v64i32";
141 case MVT::v128i32: return "MVT::v128i32";
142 case MVT::v256i32: return "MVT::v256i32";
143 case MVT::v512i32: return "MVT::v512i32";
144 case MVT::v1024i32: return "MVT::v1024i32";
145 case MVT::v2048i32: return "MVT::v2048i32";
146 case MVT::v1i64: return "MVT::v1i64";
147 case MVT::v2i64: return "MVT::v2i64";
148 case MVT::v3i64: return "MVT::v3i64";
149 case MVT::v4i64: return "MVT::v4i64";
150 case MVT::v8i64: return "MVT::v8i64";
151 case MVT::v16i64: return "MVT::v16i64";
152 case MVT::v32i64: return "MVT::v32i64";
153 case MVT::v64i64: return "MVT::v64i64";
154 case MVT::v128i64: return "MVT::v128i64";
155 case MVT::v256i64: return "MVT::v256i64";
156 case MVT::v1i128: return "MVT::v1i128";
157 case MVT::v1f16: return "MVT::v1f16";
158 case MVT::v2f16: return "MVT::v2f16";
159 case MVT::v3f16: return "MVT::v3f16";
160 case MVT::v4f16: return "MVT::v4f16";
161 case MVT::v8f16: return "MVT::v8f16";
162 case MVT::v16f16: return "MVT::v16f16";
163 case MVT::v32f16: return "MVT::v32f16";
164 case MVT::v64f16: return "MVT::v64f16";
165 case MVT::v128f16: return "MVT::v128f16";
166 case MVT::v256f16: return "MVT::v256f16";
167 case MVT::v512f16: return "MVT::v512f16";
168 case MVT::v2bf16: return "MVT::v2bf16";
169 case MVT::v3bf16: return "MVT::v3bf16";
170 case MVT::v4bf16: return "MVT::v4bf16";
171 case MVT::v8bf16: return "MVT::v8bf16";
172 case MVT::v16bf16: return "MVT::v16bf16";
173 case MVT::v32bf16: return "MVT::v32bf16";
174 case MVT::v64bf16: return "MVT::v64bf16";
175 case MVT::v128bf16: return "MVT::v128bf16";
176 case MVT::v1f32: return "MVT::v1f32";
177 case MVT::v2f32: return "MVT::v2f32";
178 case MVT::v3f32: return "MVT::v3f32";
179 case MVT::v4f32: return "MVT::v4f32";
180 case MVT::v5f32: return "MVT::v5f32";
181 case MVT::v6f32: return "MVT::v6f32";
182 case MVT::v7f32: return "MVT::v7f32";
183 case MVT::v8f32: return "MVT::v8f32";
184 case MVT::v9f32: return "MVT::v9f32";
185 case MVT::v10f32: return "MVT::v10f32";
186 case MVT::v11f32: return "MVT::v11f32";
187 case MVT::v12f32: return "MVT::v12f32";
188 case MVT::v16f32: return "MVT::v16f32";
189 case MVT::v32f32: return "MVT::v32f32";
190 case MVT::v64f32: return "MVT::v64f32";
191 case MVT::v128f32: return "MVT::v128f32";
192 case MVT::v256f32: return "MVT::v256f32";
193 case MVT::v512f32: return "MVT::v512f32";
194 case MVT::v1024f32: return "MVT::v1024f32";
195 case MVT::v2048f32: return "MVT::v2048f32";
196 case MVT::v1f64: return "MVT::v1f64";
197 case MVT::v2f64: return "MVT::v2f64";
198 case MVT::v3f64: return "MVT::v3f64";
199 case MVT::v4f64: return "MVT::v4f64";
200 case MVT::v8f64: return "MVT::v8f64";
201 case MVT::v16f64: return "MVT::v16f64";
202 case MVT::v32f64: return "MVT::v32f64";
203 case MVT::v64f64: return "MVT::v64f64";
204 case MVT::v128f64: return "MVT::v128f64";
205 case MVT::v256f64: return "MVT::v256f64";
206 case MVT::nxv1i1: return "MVT::nxv1i1";
207 case MVT::nxv2i1: return "MVT::nxv2i1";
208 case MVT::nxv4i1: return "MVT::nxv4i1";
209 case MVT::nxv8i1: return "MVT::nxv8i1";
210 case MVT::nxv16i1: return "MVT::nxv16i1";
211 case MVT::nxv32i1: return "MVT::nxv32i1";
212 case MVT::nxv64i1: return "MVT::nxv64i1";
213 case MVT::nxv1i8: return "MVT::nxv1i8";
214 case MVT::nxv2i8: return "MVT::nxv2i8";
215 case MVT::nxv4i8: return "MVT::nxv4i8";
216 case MVT::nxv8i8: return "MVT::nxv8i8";
217 case MVT::nxv16i8: return "MVT::nxv16i8";
218 case MVT::nxv32i8: return "MVT::nxv32i8";
219 case MVT::nxv64i8: return "MVT::nxv64i8";
220 case MVT::nxv1i16: return "MVT::nxv1i16";
221 case MVT::nxv2i16: return "MVT::nxv2i16";
222 case MVT::nxv4i16: return "MVT::nxv4i16";
223 case MVT::nxv8i16: return "MVT::nxv8i16";
224 case MVT::nxv16i16: return "MVT::nxv16i16";
225 case MVT::nxv32i16: return "MVT::nxv32i16";
226 case MVT::nxv1i32: return "MVT::nxv1i32";
227 case MVT::nxv2i32: return "MVT::nxv2i32";
228 case MVT::nxv4i32: return "MVT::nxv4i32";
229 case MVT::nxv8i32: return "MVT::nxv8i32";
230 case MVT::nxv16i32: return "MVT::nxv16i32";
231 case MVT::nxv32i32: return "MVT::nxv32i32";
232 case MVT::nxv1i64: return "MVT::nxv1i64";
233 case MVT::nxv2i64: return "MVT::nxv2i64";
234 case MVT::nxv4i64: return "MVT::nxv4i64";
235 case MVT::nxv8i64: return "MVT::nxv8i64";
236 case MVT::nxv16i64: return "MVT::nxv16i64";
237 case MVT::nxv32i64: return "MVT::nxv32i64";
238 case MVT::nxv1f16: return "MVT::nxv1f16";
239 case MVT::nxv2f16: return "MVT::nxv2f16";
240 case MVT::nxv4f16: return "MVT::nxv4f16";
241 case MVT::nxv8f16: return "MVT::nxv8f16";
242 case MVT::nxv16f16: return "MVT::nxv16f16";
243 case MVT::nxv32f16: return "MVT::nxv32f16";
244 case MVT::nxv1bf16: return "MVT::nxv1bf16";
245 case MVT::nxv2bf16: return "MVT::nxv2bf16";
246 case MVT::nxv4bf16: return "MVT::nxv4bf16";
247 case MVT::nxv8bf16: return "MVT::nxv8bf16";
248 case MVT::nxv16bf16: return "MVT::nxv16bf16";
249 case MVT::nxv32bf16: return "MVT::nxv32bf16";
250 case MVT::nxv1f32: return "MVT::nxv1f32";
251 case MVT::nxv2f32: return "MVT::nxv2f32";
252 case MVT::nxv4f32: return "MVT::nxv4f32";
253 case MVT::nxv8f32: return "MVT::nxv8f32";
254 case MVT::nxv16f32: return "MVT::nxv16f32";
255 case MVT::nxv1f64: return "MVT::nxv1f64";
256 case MVT::nxv2f64: return "MVT::nxv2f64";
257 case MVT::nxv4f64: return "MVT::nxv4f64";
258 case MVT::nxv8f64: return "MVT::nxv8f64";
259 case MVT::token: return "MVT::token";
260 case MVT::Metadata: return "MVT::Metadata";
261 case MVT::iPTR: return "MVT::iPTR";
262 case MVT::iPTRAny: return "MVT::iPTRAny";
263 case MVT::Untyped: return "MVT::Untyped";
264 case MVT::funcref: return "MVT::funcref";
265 case MVT::externref: return "MVT::externref";
266 default: llvm_unreachable("ILLEGAL VALUE TYPE!");
267 }
268 // clang-format on
269 }
270
271 /// getQualifiedName - Return the name of the specified record, with a
272 /// namespace qualifier if the record contains one.
273 ///
274 std::string llvm::getQualifiedName(const Record *R) {
275 std::string Namespace;
276 if (R->getValue("Namespace"))
277 Namespace = std::string(R->getValueAsString("Namespace"));
278 if (Namespace.empty())
279 return std::string(R->getName());
280 return Namespace + "::" + R->getName().str();
281 }
282
283
284 /// getTarget - Return the current instance of the Target class.
285 ///
286 CodeGenTarget::CodeGenTarget(RecordKeeper &records)
287 : Records(records), CGH(records) {
288 std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
289 if (Targets.size() == 0)
290 PrintFatalError("No 'Target' subclasses defined!");
291 if (Targets.size() != 1)
292 PrintFatalError("Multiple subclasses of Target defined!");
293 TargetRec = Targets[0];
294 }
295
296 CodeGenTarget::~CodeGenTarget() {
297 }
298
299 StringRef CodeGenTarget::getName() const { return TargetRec->getName(); }
300
301 /// getInstNamespace - Find and return the target machine's instruction
302 /// namespace. The namespace is cached because it is requested multiple times.
303 StringRef CodeGenTarget::getInstNamespace() const {
304 if (InstNamespace.empty()) {
305 for (const CodeGenInstruction *Inst : getInstructionsByEnumValue()) {
306 // We are not interested in the "TargetOpcode" namespace.
307 if (Inst->Namespace != "TargetOpcode") {
308 InstNamespace = Inst->Namespace;
309 break;
310 }
311 }
312 }
313
314 return InstNamespace;
315 }
316
317 StringRef CodeGenTarget::getRegNamespace() const {
318 auto &RegClasses = RegBank->getRegClasses();
319 return RegClasses.size() > 0 ? RegClasses.front().Namespace : "";
320 }
321
322 Record *CodeGenTarget::getInstructionSet() const {
323 return TargetRec->getValueAsDef("InstructionSet");
324 }
325
326 bool CodeGenTarget::getAllowRegisterRenaming() const {
327 return TargetRec->getValueAsInt("AllowRegisterRenaming");
328 }
329
330 /// getAsmParser - Return the AssemblyParser definition for this target.
331 ///
332 Record *CodeGenTarget::getAsmParser() const {
333 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyParsers");
334 if (AsmParserNum >= LI.size())
335 PrintFatalError("Target does not have an AsmParser #" +
336 Twine(AsmParserNum) + "!");
337 return LI[AsmParserNum];
338 }
339
340 /// getAsmParserVariant - Return the AssemblyParserVariant definition for
341 /// this target.
342 ///
343 Record *CodeGenTarget::getAsmParserVariant(unsigned i) const {
344 std::vector<Record*> LI =
345 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
346 if (i >= LI.size())
347 PrintFatalError("Target does not have an AsmParserVariant #" + Twine(i) +
348 "!");
349 return LI[i];
350 }
351
352 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition
353 /// available for this target.
354 ///
355 unsigned CodeGenTarget::getAsmParserVariantCount() const {
356 std::vector<Record*> LI =
357 TargetRec->getValueAsListOfDefs("AssemblyParserVariants");
358 return LI.size();
359 }
360
361 /// getAsmWriter - Return the AssemblyWriter definition for this target.
362 ///
363 Record *CodeGenTarget::getAsmWriter() const {
364 std::vector<Record*> LI = TargetRec->getValueAsListOfDefs("AssemblyWriters");
365 if (AsmWriterNum >= LI.size())
366 PrintFatalError("Target does not have an AsmWriter #" +
367 Twine(AsmWriterNum) + "!");
368 return LI[AsmWriterNum];
369 }
370
371 CodeGenRegBank &CodeGenTarget::getRegBank() const {
372 if (!RegBank)
373 RegBank = std::make_unique<CodeGenRegBank>(Records, getHwModes());
374 return *RegBank;
375 }
376
377 std::optional<CodeGenRegisterClass *> CodeGenTarget::getSuperRegForSubReg(
378 const ValueTypeByHwMode &ValueTy, CodeGenRegBank &RegBank,
379 const CodeGenSubRegIndex *SubIdx, bool MustBeAllocatable) const {
380 std::vector<CodeGenRegisterClass *> Candidates;
381 auto &RegClasses = RegBank.getRegClasses();
382
383 // Try to find a register class which supports ValueTy, and also contains
384 // SubIdx.
385 for (CodeGenRegisterClass &RC : RegClasses) {
386 // Is there a subclass of this class which contains this subregister index?
387 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx);
388 if (!SubClassWithSubReg)
389 continue;
390
391 // We have a class. Check if it supports this value type.
392 if (!llvm::is_contained(SubClassWithSubReg->VTs, ValueTy))
393 continue;
394
395 // If necessary, check that it is allocatable.
396 if (MustBeAllocatable && !SubClassWithSubReg->Allocatable)
397 continue;
398
399 // We have a register class which supports both the value type and
400 // subregister index. Remember it.
401 Candidates.push_back(SubClassWithSubReg);
402 }
403
404 // If we didn't find anything, we're done.
405 if (Candidates.empty())
406 return std::nullopt;
407
408 // Find and return the largest of our candidate classes.
409 llvm::stable_sort(Candidates, [&](const CodeGenRegisterClass *A,
410 const CodeGenRegisterClass *B) {
411 if (A->getMembers().size() > B->getMembers().size())
412 return true;
413
414 if (A->getMembers().size() < B->getMembers().size())
415 return false;
416
417 // Order by name as a tie-breaker.
418 return StringRef(A->getName()) < B->getName();
419 });
420
421 return Candidates[0];
422 }
423
424 void CodeGenTarget::ReadRegAltNameIndices() const {
425 RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex");
426 llvm::sort(RegAltNameIndices, LessRecord());
427 }
428
429 /// getRegisterByName - If there is a register with the specific AsmName,
430 /// return it.
431 const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
432 return getRegBank().getRegistersByName().lookup(Name);
433 }
434
435 const CodeGenRegisterClass &CodeGenTarget::getRegisterClass(Record *R) const {
436 return *getRegBank().getRegClass(R);
437 }
438
439 std::vector<ValueTypeByHwMode> CodeGenTarget::getRegisterVTs(Record *R)
440 const {
441 const CodeGenRegister *Reg = getRegBank().getReg(R);
442 std::vector<ValueTypeByHwMode> Result;
443 for (const auto &RC : getRegBank().getRegClasses()) {
444 if (RC.contains(Reg)) {
445 ArrayRef<ValueTypeByHwMode> InVTs = RC.getValueTypes();
446 llvm::append_range(Result, InVTs);
447 }
448 }
449
450 // Remove duplicates.
451 llvm::sort(Result);
452 Result.erase(std::unique(Result.begin(), Result.end()), Result.end());
453 return Result;
454 }
455
456
457 void CodeGenTarget::ReadLegalValueTypes() const {
458 for (const auto &RC : getRegBank().getRegClasses())
459 llvm::append_range(LegalValueTypes, RC.VTs);
460
461 // Remove duplicates.
462 llvm::sort(LegalValueTypes);
463 LegalValueTypes.erase(std::unique(LegalValueTypes.begin(),
464 LegalValueTypes.end()),
465 LegalValueTypes.end());
466 }
467
468 CodeGenSchedModels &CodeGenTarget::getSchedModels() const {
469 if (!SchedModels)
470 SchedModels = std::make_unique<CodeGenSchedModels>(Records, *this);
471 return *SchedModels;
472 }
473
474 void CodeGenTarget::ReadInstructions() const {
475 std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
476 if (Insts.size() <= 2)
477 PrintFatalError("No 'Instruction' subclasses defined!");
478
479 // Parse the instructions defined in the .td file.
480 for (unsigned i = 0, e = Insts.size(); i != e; ++i)
481 Instructions[Insts[i]] = std::make_unique<CodeGenInstruction>(Insts[i]);
482 }
483
484 static const CodeGenInstruction *
485 GetInstByName(const char *Name,
486 const DenseMap<const Record*,
487 std::unique_ptr<CodeGenInstruction>> &Insts,
488 RecordKeeper &Records) {
489 const Record *Rec = Records.getDef(Name);
490
491 const auto I = Insts.find(Rec);
492 if (!Rec || I == Insts.end())
493 PrintFatalError(Twine("Could not find '") + Name + "' instruction!");
494 return I->second.get();
495 }
496
497 static const char *FixedInstrs[] = {
498 #define HANDLE_TARGET_OPCODE(OPC) #OPC,
499 #include "llvm/Support/TargetOpcodes.def"
500 nullptr};
501
502 unsigned CodeGenTarget::getNumFixedInstructions() {
503 return std::size(FixedInstrs) - 1;
504 }
505
506 /// Return all of the instructions defined by the target, ordered by
507 /// their enum value.
508 void CodeGenTarget::ComputeInstrsByEnum() const {
509 const auto &Insts = getInstructions();
510 for (const char *const *p = FixedInstrs; *p; ++p) {
511 const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
512 assert(Instr && "Missing target independent instruction");
513 assert(Instr->Namespace == "TargetOpcode" && "Bad namespace");
514 InstrsByEnum.push_back(Instr);
515 }
516 unsigned EndOfPredefines = InstrsByEnum.size();
517 assert(EndOfPredefines == getNumFixedInstructions() &&
518 "Missing generic opcode");
519
520 for (const auto &I : Insts) {
521 const CodeGenInstruction *CGI = I.second.get();
522 if (CGI->Namespace != "TargetOpcode") {
523 InstrsByEnum.push_back(CGI);
524 if (CGI->TheDef->getValueAsBit("isPseudo"))
525 ++NumPseudoInstructions;
526 }
527 }
528
529 assert(InstrsByEnum.size() == Insts.size() && "Missing predefined instr");
530
531 // All of the instructions are now in random order based on the map iteration.
532 llvm::sort(
533 InstrsByEnum.begin() + EndOfPredefines, InstrsByEnum.end(),
534 [](const CodeGenInstruction *Rec1, const CodeGenInstruction *Rec2) {
535 const auto &D1 = *Rec1->TheDef;
536 const auto &D2 = *Rec2->TheDef;
537 return std::make_tuple(!D1.getValueAsBit("isPseudo"), D1.getName()) <
538 std::make_tuple(!D2.getValueAsBit("isPseudo"), D2.getName());
539 });
540 }
541
542
543 /// isLittleEndianEncoding - Return whether this target encodes its instruction
544 /// in little-endian format, i.e. bits laid out in the order [0..n]
545 ///
546 bool CodeGenTarget::isLittleEndianEncoding() const {
547 return getInstructionSet()->getValueAsBit("isLittleEndianEncoding");
548 }
549
550 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
551 /// encodings, reverse the bit order of all instructions.
552 void CodeGenTarget::reverseBitsForLittleEndianEncoding() {
553 if (!isLittleEndianEncoding())
554 return;
555
556 std::vector<Record *> Insts =
557 Records.getAllDerivedDefinitions("InstructionEncoding");
558 for (Record *R : Insts) {
559 if (R->getValueAsString("Namespace") == "TargetOpcode" ||
560 R->getValueAsBit("isPseudo"))
561 continue;
562
563 BitsInit *BI = R->getValueAsBitsInit("Inst");
564
565 unsigned numBits = BI->getNumBits();
566
567 SmallVector<Init *, 16> NewBits(numBits);
568
569 for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) {
570 unsigned bitSwapIdx = numBits - bit - 1;
571 Init *OrigBit = BI->getBit(bit);
572 Init *BitSwap = BI->getBit(bitSwapIdx);
573 NewBits[bit] = BitSwap;
574 NewBits[bitSwapIdx] = OrigBit;
575 }
576 if (numBits % 2) {
577 unsigned middle = (numBits + 1) / 2;
578 NewBits[middle] = BI->getBit(middle);
579 }
580
581 BitsInit *NewBI = BitsInit::get(Records, NewBits);
582
583 // Update the bits in reversed order so that emitInstrOpBits will get the
584 // correct endianness.
585 R->getValue("Inst")->setValue(NewBI);
586 }
587 }
588
589 /// guessInstructionProperties - Return true if it's OK to guess instruction
590 /// properties instead of raising an error.
591 ///
592 /// This is configurable as a temporary migration aid. It will eventually be
593 /// permanently false.
594 bool CodeGenTarget::guessInstructionProperties() const {
595 return getInstructionSet()->getValueAsBit("guessInstructionProperties");
596 }
597
598 //===----------------------------------------------------------------------===//
599 // ComplexPattern implementation
600 //
601 ComplexPattern::ComplexPattern(Record *R) {
602 Ty = R->getValueAsDef("Ty");
603 NumOperands = R->getValueAsInt("NumOperands");
604 SelectFunc = std::string(R->getValueAsString("SelectFunc"));
605 RootNodes = R->getValueAsListOfDefs("RootNodes");
606
607 // FIXME: This is a hack to statically increase the priority of patterns which
608 // maps a sub-dag to a complex pattern. e.g. favors LEA over ADD. To get best
609 // possible pattern match we'll need to dynamically calculate the complexity
610 // of all patterns a dag can potentially map to.
611 int64_t RawComplexity = R->getValueAsInt("Complexity");
612 if (RawComplexity == -1)
613 Complexity = NumOperands * 3;
614 else
615 Complexity = RawComplexity;
616
617 // FIXME: Why is this different from parseSDPatternOperatorProperties?
618 // Parse the properties.
619 Properties = 0;
620 std::vector<Record*> PropList = R->getValueAsListOfDefs("Properties");
621 for (unsigned i = 0, e = PropList.size(); i != e; ++i)
622 if (PropList[i]->getName() == "SDNPHasChain") {
623 Properties |= 1 << SDNPHasChain;
624 } else if (PropList[i]->getName() == "SDNPOptInGlue") {
625 Properties |= 1 << SDNPOptInGlue;
626 } else if (PropList[i]->getName() == "SDNPMayStore") {
627 Properties |= 1 << SDNPMayStore;
628 } else if (PropList[i]->getName() == "SDNPMayLoad") {
629 Properties |= 1 << SDNPMayLoad;
630 } else if (PropList[i]->getName() == "SDNPSideEffect") {
631 Properties |= 1 << SDNPSideEffect;
632 } else if (PropList[i]->getName() == "SDNPMemOperand") {
633 Properties |= 1 << SDNPMemOperand;
634 } else if (PropList[i]->getName() == "SDNPVariadic") {
635 Properties |= 1 << SDNPVariadic;
636 } else if (PropList[i]->getName() == "SDNPWantRoot") {
637 Properties |= 1 << SDNPWantRoot;
638 } else if (PropList[i]->getName() == "SDNPWantParent") {
639 Properties |= 1 << SDNPWantParent;
640 } else {
641 PrintFatalError(R->getLoc(), "Unsupported SD Node property '" +
642 PropList[i]->getName() +
643 "' on ComplexPattern '" + R->getName() +
644 "'!");
645 }
646 }
LLVM monorepo