llvm/utils/TableGen/PseudoLoweringEmitter.cpp

   1 //===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #include "CodeGenInstruction.h"
  10 #include "CodeGenTarget.h"
  11 #include "llvm/ADT/IndexedMap.h"
  12 #include "llvm/ADT/SmallVector.h"
  13 #include "llvm/ADT/StringMap.h"
  14 #include "llvm/Support/Debug.h"
  15 #include "llvm/Support/ErrorHandling.h"
  16 #include "llvm/TableGen/Error.h"
  17 #include "llvm/TableGen/Record.h"
  18 #include "llvm/TableGen/TableGenBackend.h"
  19 #include <vector>
  20 using namespace llvm;
  21
  22 #define DEBUG_TYPE "pseudo-lowering"
  23
  24 namespace {
  25 class PseudoLoweringEmitter {
  26   struct OpData {
  27     enum MapKind { Operand, Imm, Reg };
  28     MapKind Kind;
  29     union {
  30       unsigned Operand;   // Operand number mapped to.
  31       uint64_t Imm;       // Integer immedate value.
  32       Record *Reg;        // Physical register.
  33     } Data;
  34   };
  35   struct PseudoExpansion {
  36     CodeGenInstruction Source;  // The source pseudo instruction definition.
  37     CodeGenInstruction Dest;    // The destination instruction to lower to.
  38     IndexedMap<OpData> OperandMap;
  39
  40     PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
  41                     IndexedMap<OpData> &m) :
  42       Source(s), Dest(d), OperandMap(m) {}
  43   };
  44
  45   RecordKeeper &Records;
  46
  47   // It's overkill to have an instance of the full CodeGenTarget object,
  48   // but it loads everything on demand, not in the constructor, so it's
  49   // lightweight in performance, so it works out OK.
  50   CodeGenTarget Target;
  51
  52   SmallVector<PseudoExpansion, 64> Expansions;
  53
  54   unsigned addDagOperandMapping(Record *Rec, DagInit *Dag,
  55                                 CodeGenInstruction &Insn,
  56                                 IndexedMap<OpData> &OperandMap,
  57                                 unsigned BaseIdx);
  58   void evaluateExpansion(Record *Pseudo);
  59   void emitLoweringEmitter(raw_ostream &o);
  60 public:
  61   PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {}
  62
  63   /// run - Output the pseudo-lowerings.
  64   void run(raw_ostream &o);
  65 };
  66 } // End anonymous namespace
  67
  68 // FIXME: This pass currently can only expand a pseudo to a single instruction.
  69 //        The pseudo expansion really should take a list of dags, not just
  70 //        a single dag, so we can do fancier things.
  71
  72 unsigned PseudoLoweringEmitter::
  73 addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
  74                      IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
  75   unsigned OpsAdded = 0;
  76   for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
  77     if (DefInit *DI = dyn_cast<DefInit>(Dag->getArg(i))) {
  78       // Physical register reference. Explicit check for the special case
  79       // "zero_reg" definition.
  80       if (DI->getDef()->isSubClassOf("Register") ||
  81           DI->getDef()->getName() == "zero_reg") {
  82         OperandMap[BaseIdx + i].Kind = OpData::Reg;
  83         OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
  84         ++OpsAdded;
  85         continue;
  86       }
  87
  88       // Normal operands should always have the same type, or we have a
  89       // problem.
  90       // FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
  91       assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
  92       // FIXME: Are the message operand types backward?
  93       if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) {
  94         PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
  95                         "', operand type '" + DI->getDef()->getName() +
  96                         "' does not match expansion operand type '" +
  97                         Insn.Operands[BaseIdx + i].Rec->getName() + "'");
  98         PrintFatalNote(DI->getDef(),
  99                        "Value was assigned at the following location:");
 100       }
 101       // Source operand maps to destination operand. The Data element
 102       // will be filled in later, just set the Kind for now. Do it
 103       // for each corresponding MachineInstr operand, not just the first.
 104       for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
 105         OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
 106       OpsAdded += Insn.Operands[i].MINumOperands;
 107     } else if (IntInit *II = dyn_cast<IntInit>(Dag->getArg(i))) {
 108       OperandMap[BaseIdx + i].Kind = OpData::Imm;
 109       OperandMap[BaseIdx + i].Data.Imm = II->getValue();
 110       ++OpsAdded;
 111     } else if (auto *BI = dyn_cast<BitsInit>(Dag->getArg(i))) {
 112       auto *II =
 113           cast<IntInit>(BI->convertInitializerTo(IntRecTy::get(Records)));
 114       OperandMap[BaseIdx + i].Kind = OpData::Imm;
 115       OperandMap[BaseIdx + i].Data.Imm = II->getValue();
 116       ++OpsAdded;
 117     } else if (DagInit *SubDag = dyn_cast<DagInit>(Dag->getArg(i))) {
 118       // Just add the operands recursively. This is almost certainly
 119       // a constant value for a complex operand (> 1 MI operand).
 120       unsigned NewOps =
 121         addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
 122       OpsAdded += NewOps;
 123       // Since we added more than one, we also need to adjust the base.
 124       BaseIdx += NewOps - 1;
 125     } else
 126       llvm_unreachable("Unhandled pseudo-expansion argument type!");
 127   }
 128   return OpsAdded;
 129 }
 130
 131 void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
 132   LLVM_DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n");
 133
 134   // Validate that the result pattern has the corrent number and types
 135   // of arguments for the instruction it references.
 136   DagInit *Dag = Rec->getValueAsDag("ResultInst");
 137   assert(Dag && "Missing result instruction in pseudo expansion!");
 138   LLVM_DEBUG(dbgs() << "  Result: " << *Dag << "\n");
 139
 140   DefInit *OpDef = dyn_cast<DefInit>(Dag->getOperator());
 141   if (!OpDef) {
 142     PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
 143                     "', result operator is not a record");
 144     PrintFatalNote(Rec->getValue("ResultInst"),
 145                    "Result was assigned at the following location:");
 146   }
 147   Record *Operator = OpDef->getDef();
 148   if (!Operator->isSubClassOf("Instruction")) {
 149     PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
 150                     "', result operator '" + Operator->getName() +
 151                     "' is not an instruction");
 152     PrintFatalNote(Rec->getValue("ResultInst"),
 153                    "Result was assigned at the following location:");
 154   }
 155
 156   CodeGenInstruction Insn(Operator);
 157
 158   if (Insn.isCodeGenOnly || Insn.isPseudo) {
 159     PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
 160                     "', result operator '" + Operator->getName() +
 161                     "' cannot be a pseudo instruction");
 162     PrintFatalNote(Rec->getValue("ResultInst"),
 163                    "Result was assigned at the following location:");
 164   }
 165
 166   if (Insn.Operands.size() != Dag->getNumArgs()) {
 167     PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
 168                     "', result operator '" + Operator->getName() +
 169                     "' has the wrong number of operands");
 170     PrintFatalNote(Rec->getValue("ResultInst"),
 171                    "Result was assigned at the following location:");
 172   }
 173
 174   unsigned NumMIOperands = 0;
 175   for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
 176     NumMIOperands += Insn.Operands[i].MINumOperands;
 177   IndexedMap<OpData> OperandMap;
 178   OperandMap.grow(NumMIOperands);
 179
 180   addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
 181
 182   // If there are more operands that weren't in the DAG, they have to
 183   // be operands that have default values, or we have an error. Currently,
 184   // Operands that are a subclass of OperandWithDefaultOp have default values.
 185
 186   // Validate that each result pattern argument has a matching (by name)
 187   // argument in the source instruction, in either the (outs) or (ins) list.
 188   // Also check that the type of the arguments match.
 189   //
 190   // Record the mapping of the source to result arguments for use by
 191   // the lowering emitter.
 192   CodeGenInstruction SourceInsn(Rec);
 193   StringMap<unsigned> SourceOperands;
 194   for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i)
 195     SourceOperands[SourceInsn.Operands[i].Name] = i;
 196
 197   LLVM_DEBUG(dbgs() << "  Operand mapping:\n");
 198   for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) {
 199     // We've already handled constant values. Just map instruction operands
 200     // here.
 201     if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)
 202       continue;
 203     StringMap<unsigned>::iterator SourceOp =
 204       SourceOperands.find(Dag->getArgNameStr(i));
 205     if (SourceOp == SourceOperands.end()) {
 206       PrintError(Rec, "In pseudo instruction '" + Rec->getName() +
 207                       "', output operand '" + Dag->getArgNameStr(i) +
 208                       "' has no matching source operand");
 209       PrintFatalNote(Rec->getValue("ResultInst"),
 210                      "Value was assigned at the following location:");
 211     }
 212     // Map the source operand to the destination operand index for each
 213     // MachineInstr operand.
 214     for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
 215       OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand =
 216         SourceOp->getValue();
 217
 218     LLVM_DEBUG(dbgs() << "    " << SourceOp->getValue() << " ==> " << i
 219                       << "\n");
 220   }
 221
 222   Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap));
 223 }
 224
 225 void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
 226   // Emit file header.
 227   emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
 228
 229   o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
 230     << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
 231     << "                            const MachineInstr *MI) {\n";
 232
 233   if (!Expansions.empty()) {
 234     o << "  switch (MI->getOpcode()) {\n"
 235       << "  default: return false;\n";
 236     for (auto &Expansion : Expansions) {
 237       CodeGenInstruction &Source = Expansion.Source;
 238       CodeGenInstruction &Dest = Expansion.Dest;
 239       o << "  case " << Source.Namespace << "::"
 240         << Source.TheDef->getName() << ": {\n"
 241         << "    MCInst TmpInst;\n"
 242         << "    MCOperand MCOp;\n"
 243         << "    TmpInst.setOpcode(" << Dest.Namespace << "::"
 244         << Dest.TheDef->getName() << ");\n";
 245
 246       // Copy the operands from the source instruction.
 247       // FIXME: Instruction operands with defaults values (predicates and cc_out
 248       //        in ARM, for example shouldn't need explicit values in the
 249       //        expansion DAG.
 250       unsigned MIOpNo = 0;
 251       for (const auto &DestOperand : Dest.Operands) {
 252         o << "    // Operand: " << DestOperand.Name << "\n";
 253         for (unsigned i = 0, e = DestOperand.MINumOperands; i != e; ++i) {
 254           switch (Expansion.OperandMap[MIOpNo + i].Kind) {
 255             case OpData::Operand:
 256             o << "    lowerOperand(MI->getOperand("
 257               << Source.Operands[Expansion.OperandMap[MIOpNo].Data
 258               .Operand].MIOperandNo + i
 259               << "), MCOp);\n"
 260               << "    TmpInst.addOperand(MCOp);\n";
 261             break;
 262             case OpData::Imm:
 263             o << "    TmpInst.addOperand(MCOperand::createImm("
 264               << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
 265             break;
 266             case OpData::Reg: {
 267               Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
 268               o << "    TmpInst.addOperand(MCOperand::createReg(";
 269               // "zero_reg" is special.
 270               if (Reg->getName() == "zero_reg")
 271                 o << "0";
 272               else
 273                 o << Reg->getValueAsString("Namespace") << "::"
 274                   << Reg->getName();
 275               o << "));\n";
 276               break;
 277             }
 278           }
 279         }
 280         MIOpNo += DestOperand.MINumOperands;
 281       }
 282       if (Dest.Operands.isVariadic) {
 283         MIOpNo = Source.Operands.size() + 1;
 284         o << "    // variable_ops\n";
 285         o << "    for (unsigned i = " << MIOpNo
 286           << ", e = MI->getNumOperands(); i != e; ++i)\n"
 287           << "      if (lowerOperand(MI->getOperand(i), MCOp))\n"
 288           << "        TmpInst.addOperand(MCOp);\n";
 289       }
 290       o << "    EmitToStreamer(OutStreamer, TmpInst);\n"
 291         << "    break;\n"
 292         << "  }\n";
 293     }
 294     o << "  }\n  return true;";
 295   } else
 296     o << "  return false;";
 297
 298   o << "\n}\n\n";
 299 }
 300
 301 void PseudoLoweringEmitter::run(raw_ostream &o) {
 302   StringRef Classes[] = {"PseudoInstExpansion", "Instruction"};
 303   std::vector<Record *> Insts = Records.getAllDerivedDefinitions(Classes);
 304
 305   // Process the pseudo expansion definitions, validating them as we do so.
 306   Records.startTimer("Process definitions");
 307   for (unsigned i = 0, e = Insts.size(); i != e; ++i)
 308     evaluateExpansion(Insts[i]);
 309
 310   // Generate expansion code to lower the pseudo to an MCInst of the real
 311   // instruction.
 312   Records.startTimer("Emit expansion code");
 313   emitLoweringEmitter(o);
 314 }
 315
 316 static TableGen::Emitter::OptClass<PseudoLoweringEmitter>
 317     X("gen-pseudo-lowering", "Generate pseudo instruction lowering");