llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp

   1 //===- utils/TableGen/X86EVEX2VEXTablesEmitter.cpp - X86 backend-*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// This tablegen backend is responsible for emitting the X86 backend EVEX2VEX
  10 /// compression tables.
  11 ///
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "CodeGenInstruction.h"
  15 #include "CodeGenTarget.h"
  16 #include "X86RecognizableInstr.h"
  17 #include "llvm/TableGen/Error.h"
  18 #include "llvm/TableGen/Record.h"
  19 #include "llvm/TableGen/TableGenBackend.h"
  20
  21 using namespace llvm;
  22 using namespace X86Disassembler;
  23
  24 namespace {
  25
  26 class X86EVEX2VEXTablesEmitter {
  27   RecordKeeper &Records;
  28   CodeGenTarget Target;
  29
  30   // Hold all non-masked & non-broadcasted EVEX encoded instructions
  31   std::vector<const CodeGenInstruction *> EVEXInsts;
  32   // Hold all VEX encoded instructions. Divided into groups with same opcodes
  33   // to make the search more efficient
  34   std::map<uint64_t, std::vector<const CodeGenInstruction *>> VEXInsts;
  35
  36   typedef std::pair<const CodeGenInstruction *, const CodeGenInstruction *> Entry;
  37   typedef std::pair<StringRef, StringRef> Predicate;
  38
  39   // Represent both compress tables
  40   std::vector<Entry> EVEX2VEX128;
  41   std::vector<Entry> EVEX2VEX256;
  42   // Represent predicates of VEX instructions.
  43   std::vector<Predicate> EVEX2VEXPredicates;
  44
  45 public:
  46   X86EVEX2VEXTablesEmitter(RecordKeeper &R) : Records(R), Target(R) {}
  47
  48   // run - Output X86 EVEX2VEX tables.
  49   void run(raw_ostream &OS);
  50
  51 private:
  52   // Prints the given table as a C++ array of type
  53   // X86EvexToVexCompressTableEntry
  54   void printTable(const std::vector<Entry> &Table, raw_ostream &OS);
  55   // Prints function which checks target feature specific predicate.
  56   void printCheckPredicate(const std::vector<Predicate> &Predicates,
  57                            raw_ostream &OS);
  58 };
  59
  60 void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
  61                                           raw_ostream &OS) {
  62   StringRef Size = (Table == EVEX2VEX128) ? "128" : "256";
  63
  64   OS << "// X86 EVEX encoded instructions that have a VEX " << Size
  65      << " encoding\n"
  66      << "// (table format: <EVEX opcode, VEX-" << Size << " opcode>).\n"
  67      << "static const X86EvexToVexCompressTableEntry X86EvexToVex" << Size
  68      << "CompressTable[] = {\n"
  69      << "  // EVEX scalar with corresponding VEX.\n";
  70
  71   // Print all entries added to the table
  72   for (const auto &Pair : Table) {
  73     OS << "  { X86::" << Pair.first->TheDef->getName()
  74        << ", X86::" << Pair.second->TheDef->getName() << " },\n";
  75   }
  76
  77   OS << "};\n\n";
  78 }
  79
  80 void X86EVEX2VEXTablesEmitter::printCheckPredicate(
  81     const std::vector<Predicate> &Predicates, raw_ostream &OS) {
  82   OS << "static bool CheckVEXInstPredicate"
  83      << "(MachineInstr &MI, const X86Subtarget *Subtarget) {\n"
  84      << "  unsigned Opc = MI.getOpcode();\n"
  85      << "  switch (Opc) {\n"
  86      << "    default: return true;\n";
  87   for (const auto &Pair : Predicates)
  88     OS << "    case X86::" << Pair.first << ": return " << Pair.second << ";\n";
  89   OS << "  }\n"
  90      << "}\n\n";
  91 }
  92
  93 // Return true if the 2 BitsInits are equal
  94 // Calculates the integer value residing BitsInit object
  95 static inline uint64_t getValueFromBitsInit(const BitsInit *B) {
  96   uint64_t Value = 0;
  97   for (unsigned i = 0, e = B->getNumBits(); i != e; ++i) {
  98     if (BitInit *Bit = dyn_cast<BitInit>(B->getBit(i)))
  99       Value |= uint64_t(Bit->getValue()) << i;
 100     else
 101       PrintFatalError("Invalid VectSize bit");
 102   }
 103   return Value;
 104 }
 105
 106 // Function object - Operator() returns true if the given VEX instruction
 107 // matches the EVEX instruction of this object.
 108 class IsMatch {
 109   const CodeGenInstruction *EVEXInst;
 110
 111 public:
 112   IsMatch(const CodeGenInstruction *EVEXInst) : EVEXInst(EVEXInst) {}
 113
 114   bool operator()(const CodeGenInstruction *VEXInst) {
 115     RecognizableInstrBase VEXRI(*VEXInst);
 116     RecognizableInstrBase EVEXRI(*EVEXInst);
 117     bool VEX_W = VEXRI.HasREX_W;
 118     bool EVEX_W = EVEXRI.HasREX_W;
 119     bool VEX_WIG  = VEXRI.IgnoresW;
 120     bool EVEX_WIG  = EVEXRI.IgnoresW;
 121     bool EVEX_W1_VEX_W0 = EVEXInst->TheDef->getValueAsBit("EVEX_W1_VEX_W0");
 122
 123     if (VEXRI.IsCodeGenOnly != EVEXRI.IsCodeGenOnly ||
 124         // VEX/EVEX fields
 125         VEXRI.OpPrefix != EVEXRI.OpPrefix || VEXRI.OpMap != EVEXRI.OpMap ||
 126         VEXRI.HasVEX_4V != EVEXRI.HasVEX_4V ||
 127         VEXRI.HasVEX_L != EVEXRI.HasVEX_L ||
 128         // Match is allowed if either is VEX_WIG, or they match, or EVEX
 129         // is VEX_W1X and VEX is VEX_W0.
 130         (!(VEX_WIG || (!EVEX_WIG && EVEX_W == VEX_W) ||
 131            (EVEX_W1_VEX_W0 && EVEX_W && !VEX_W))) ||
 132         // Instruction's format
 133         VEXRI.Form != EVEXRI.Form)
 134       return false;
 135
 136     // This is needed for instructions with intrinsic version (_Int).
 137     // Where the only difference is the size of the operands.
 138     // For example: VUCOMISDZrm and Int_VUCOMISDrm
 139     // Also for instructions that their EVEX version was upgraded to work with
 140     // k-registers. For example VPCMPEQBrm (xmm output register) and
 141     // VPCMPEQBZ128rm (k register output register).
 142     for (unsigned i = 0, e = EVEXInst->Operands.size(); i < e; i++) {
 143       Record *OpRec1 = EVEXInst->Operands[i].Rec;
 144       Record *OpRec2 = VEXInst->Operands[i].Rec;
 145
 146       if (OpRec1 == OpRec2)
 147         continue;
 148
 149       if (isRegisterOperand(OpRec1) && isRegisterOperand(OpRec2)) {
 150         if (getRegOperandSize(OpRec1) != getRegOperandSize(OpRec2))
 151           return false;
 152       } else if (isMemoryOperand(OpRec1) && isMemoryOperand(OpRec2)) {
 153         return false;
 154       } else if (isImmediateOperand(OpRec1) && isImmediateOperand(OpRec2)) {
 155         if (OpRec1->getValueAsDef("Type") != OpRec2->getValueAsDef("Type")) {
 156           return false;
 157         }
 158       } else
 159         return false;
 160     }
 161
 162     return true;
 163   }
 164 };
 165
 166 void X86EVEX2VEXTablesEmitter::run(raw_ostream &OS) {
 167   auto getPredicates = [&](const CodeGenInstruction *Inst) {
 168     std::vector<Record *> PredicatesRecords =
 169         Inst->TheDef->getValueAsListOfDefs("Predicates");
 170     // Currently we only do AVX related checks and assume each instruction
 171     // has one and only one AVX related predicates.
 172     for (unsigned i = 0, e = PredicatesRecords.size(); i != e; ++i)
 173       if (PredicatesRecords[i]->getName().startswith("HasAVX"))
 174         return PredicatesRecords[i]->getValueAsString("CondString");
 175     llvm_unreachable(
 176         "Instruction with checkPredicate set must have one predicate!");
 177   };
 178
 179   emitSourceFileHeader("X86 EVEX2VEX tables", OS);
 180
 181   ArrayRef<const CodeGenInstruction *> NumberedInstructions =
 182       Target.getInstructionsByEnumValue();
 183
 184   for (const CodeGenInstruction *Inst : NumberedInstructions) {
 185     const Record *Def = Inst->TheDef;
 186     // Filter non-X86 instructions.
 187     if (!Def->isSubClassOf("X86Inst"))
 188       continue;
 189     // _REV instruction should not appear before encoding optimization
 190     if (Def->getName().endswith("_REV"))
 191       continue;
 192     RecognizableInstrBase RI(*Inst);
 193
 194     // Add VEX encoded instructions to one of VEXInsts vectors according to
 195     // it's opcode.
 196     if (RI.Encoding == X86Local::VEX)
 197       VEXInsts[RI.Opcode].push_back(Inst);
 198     // Add relevant EVEX encoded instructions to EVEXInsts
 199     else if (RI.Encoding == X86Local::EVEX && !RI.HasEVEX_K && !RI.HasEVEX_B &&
 200              !RI.HasEVEX_L2 && !Def->getValueAsBit("notEVEX2VEXConvertible"))
 201       EVEXInsts.push_back(Inst);
 202   }
 203
 204   for (const CodeGenInstruction *EVEXInst : EVEXInsts) {
 205     uint64_t Opcode = getValueFromBitsInit(EVEXInst->TheDef->
 206                                            getValueAsBitsInit("Opcode"));
 207     // For each EVEX instruction look for a VEX match in the appropriate vector
 208     // (instructions with the same opcode) using function object IsMatch.
 209     // Allow EVEX2VEXOverride to explicitly specify a match.
 210     const CodeGenInstruction *VEXInst = nullptr;
 211     if (!EVEXInst->TheDef->isValueUnset("EVEX2VEXOverride")) {
 212       StringRef AltInstStr =
 213         EVEXInst->TheDef->getValueAsString("EVEX2VEXOverride");
 214       Record *AltInstRec = Records.getDef(AltInstStr);
 215       assert(AltInstRec && "EVEX2VEXOverride instruction not found!");
 216       VEXInst = &Target.getInstruction(AltInstRec);
 217     } else {
 218       auto Match = llvm::find_if(VEXInsts[Opcode], IsMatch(EVEXInst));
 219       if (Match != VEXInsts[Opcode].end())
 220         VEXInst = *Match;
 221     }
 222
 223     if (!VEXInst)
 224       continue;
 225
 226     // In case a match is found add new entry to the appropriate table
 227     if (EVEXInst->TheDef->getValueAsBit("hasVEX_L"))
 228       EVEX2VEX256.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,1}
 229     else
 230       EVEX2VEX128.push_back(std::make_pair(EVEXInst, VEXInst)); // {0,0}
 231
 232     // Adding predicate check to EVEX2VEXPredicates table when needed.
 233     if (VEXInst->TheDef->getValueAsBit("checkVEXPredicate"))
 234       EVEX2VEXPredicates.push_back(
 235           std::make_pair(EVEXInst->TheDef->getName(), getPredicates(VEXInst)));
 236   }
 237
 238   // Print both tables
 239   printTable(EVEX2VEX128, OS);
 240   printTable(EVEX2VEX256, OS);
 241   // Print CheckVEXInstPredicate function.
 242   printCheckPredicate(EVEX2VEXPredicates, OS);
 243 }
 244 } // namespace
 245
 246 static TableGen::Emitter::OptClass<X86EVEX2VEXTablesEmitter>
 247     X("gen-x86-EVEX2VEX-tables", "Generate X86 EVEX to VEX compress tables");