| blob | db2bff4b181a3bdc236fa51825f547a6235f5864 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck -check-prefix=GFX7 %s
3 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
4 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s
6 define i32 @s_add_co_select_user() {
7 ; GFX7-LABEL: s_add_co_select_user:
8 ; GFX7: ; %bb.0: ; %bb
9 ; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10 ; GFX7-NEXT: s_mov_b64 s[4:5], 0
11 ; GFX7-NEXT: s_load_dword s6, s[4:5], 0x0
12 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
13 ; GFX7-NEXT: v_add_i32_e64 v0, s[4:5], s6, s6
14 ; GFX7-NEXT: s_or_b32 s4, s4, s5
15 ; GFX7-NEXT: s_cmp_lg_u32 s4, 0
16 ; GFX7-NEXT: s_addc_u32 s4, s6, 0
17 ; GFX7-NEXT: v_mov_b32_e32 v1, s4
18 ; GFX7-NEXT: s_cselect_b64 vcc, -1, 0
19 ; GFX7-NEXT: s_cmp_gt_u32 s6, 31
20 ; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
21 ; GFX7-NEXT: s_cselect_b64 vcc, -1, 0
22 ; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
23 ; GFX7-NEXT: s_setpc_b64 s[30:31]
24 ;
25 ; GFX9-LABEL: s_add_co_select_user:
26 ; GFX9: ; %bb.0: ; %bb
27 ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
28 ; GFX9-NEXT: s_mov_b64 s[4:5], 0
29 ; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0
30 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
31 ; GFX9-NEXT: v_add_co_u32_e64 v0, s[4:5], s6, s6
32 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0
33 ; GFX9-NEXT: s_addc_u32 s4, s6, 0
34 ; GFX9-NEXT: v_mov_b32_e32 v1, s4
35 ; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
36 ; GFX9-NEXT: s_cmp_gt_u32 s6, 31
37 ; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
38 ; GFX9-NEXT: s_cselect_b64 vcc, -1, 0
39 ; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
40 ; GFX9-NEXT: s_setpc_b64 s[30:31]
41 ;
42 ; GFX10-LABEL: s_add_co_select_user:
43 ; GFX10: ; %bb.0: ; %bb
44 ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
45 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
46 ; GFX10-NEXT: s_mov_b64 s[4:5], 0
47 ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0
48 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
49 ; GFX10-NEXT: v_add_co_u32 v0, s5, s4, s4
50 ; GFX10-NEXT: s_cmpk_lg_u32 s5, 0x0
51 ; GFX10-NEXT: s_addc_u32 s5, s4, 0
52 ; GFX10-NEXT: s_cselect_b32 s6, -1, 0
53 ; GFX10-NEXT: s_cmp_gt_u32 s4, 31
54 ; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, s5, s6
55 ; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0
56 ; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
57 ; GFX10-NEXT: s_setpc_b64 s[30:31]
58 bb:
59 %i = load volatile i32, i32 addrspace(4)* null, align 8
60 %i1 = add i32 %i, %i
61 %i2 = icmp ult i32 %i1, %i
62 %i3 = zext i1 %i2 to i32
63 %i4 = add nuw nsw i32 %i3, 0
64 %i5 = add i32 %i4, %i
65 %i6 = icmp ult i32 %i5, %i4
66 %i7 = select i1 %i6, i32 %i5, i32 0
67 %i8 = icmp ugt i32 %i, 31
68 %i9 = select i1 %i8, i32 %i1, i32 %i7
69 ret i32 %i9
70 }
72 define amdgpu_kernel void @s_add_co_br_user(i32 %i) {
73 ; GFX7-LABEL: s_add_co_br_user:
74 ; GFX7: ; %bb.0: ; %bb
75 ; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
76 ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
77 ; GFX7-NEXT: s_add_i32 s0, s2, s2
78 ; GFX7-NEXT: s_cmp_lt_u32 s0, s2
79 ; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0
80 ; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
81 ; GFX7-NEXT: s_or_b32 s0, s0, s1
82 ; GFX7-NEXT: s_cmp_lg_u32 s0, 0
83 ; GFX7-NEXT: s_addc_u32 s0, s2, 0
84 ; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
85 ; GFX7-NEXT: s_cbranch_vccnz .LBB1_2
86 ; GFX7-NEXT: ; %bb.1: ; %bb0
87 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
88 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
89 ; GFX7-NEXT: v_mov_b32_e32 v2, 9
90 ; GFX7-NEXT: flat_store_dword v[0:1], v2
91 ; GFX7-NEXT: s_waitcnt vmcnt(0)
92 ; GFX7-NEXT: .LBB1_2: ; %bb1
93 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
94 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
95 ; GFX7-NEXT: v_mov_b32_e32 v2, 10
96 ; GFX7-NEXT: flat_store_dword v[0:1], v2
97 ; GFX7-NEXT: s_waitcnt vmcnt(0)
98 ; GFX7-NEXT: s_endpgm
99 ;
100 ; GFX9-LABEL: s_add_co_br_user:
101 ; GFX9: ; %bb.0: ; %bb
102 ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x0
103 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
104 ; GFX9-NEXT: s_add_i32 s0, s2, s2
105 ; GFX9-NEXT: s_cmp_lt_u32 s0, s2
106 ; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0
107 ; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0
108 ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
109 ; GFX9-NEXT: s_addc_u32 s0, s2, 0
110 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
111 ; GFX9-NEXT: s_cbranch_vccnz .LBB1_2
112 ; GFX9-NEXT: ; %bb.1: ; %bb0
113 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
114 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
115 ; GFX9-NEXT: v_mov_b32_e32 v2, 9
116 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
117 ; GFX9-NEXT: s_waitcnt vmcnt(0)
118 ; GFX9-NEXT: .LBB1_2: ; %bb1
119 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
120 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
121 ; GFX9-NEXT: v_mov_b32_e32 v2, 10
122 ; GFX9-NEXT: global_store_dword v[0:1], v2, off
123 ; GFX9-NEXT: s_waitcnt vmcnt(0)
124 ; GFX9-NEXT: s_endpgm
125 ;
126 ; GFX10-LABEL: s_add_co_br_user:
127 ; GFX10: ; %bb.0: ; %bb
128 ; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0
129 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
130 ; GFX10-NEXT: s_add_i32 s1, s0, s0
131 ; GFX10-NEXT: s_cmp_lt_u32 s1, s0
132 ; GFX10-NEXT: s_cselect_b32 s1, -1, 0
133 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
134 ; GFX10-NEXT: s_cmpk_lg_u32 s1, 0x0
135 ; GFX10-NEXT: s_addc_u32 s0, s0, 0
136 ; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
137 ; GFX10-NEXT: s_cbranch_vccnz .LBB1_2
138 ; GFX10-NEXT: ; %bb.1: ; %bb0
139 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
140 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
141 ; GFX10-NEXT: v_mov_b32_e32 v2, 9
142 ; GFX10-NEXT: global_store_dword v[0:1], v2, off
143 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
144 ; GFX10-NEXT: .LBB1_2: ; %bb1
145 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
146 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
147 ; GFX10-NEXT: v_mov_b32_e32 v2, 10
148 ; GFX10-NEXT: global_store_dword v[0:1], v2, off
149 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
150 ; GFX10-NEXT: s_endpgm
151 bb:
152 %i1 = add i32 %i, %i
153 %i2 = icmp ult i32 %i1, %i
154 %i3 = zext i1 %i2 to i32
155 %i4 = add nuw nsw i32 %i3, 0
156 %i5 = add i32 %i4, %i
157 %i6 = icmp ult i32 %i5, %i4
158 %i7 = select i1 %i6, i32 %i5, i32 0
159 br i1 %i6, label %bb0, label %bb1
161 bb0:
162 store volatile i32 9, i32 addrspace(1)* null
163 br label %bb1
165 bb1:
166 store volatile i32 10, i32 addrspace(1)* null
167 ret void
168 }